CN101447432A - Manufacturing method of double diffusion field effect transistor - Google Patents

Abstract

The invention discloses a manufacturing method of a double diffusion field effect transistor, comprising the following steps: greatly increasing the saturation currents of the transistor by increasing the overlapped area of a transistor gate and drift region; changing the electric field distribution on the drift region using an extended grid potential so as to increase breakdown voltages; and synchronously, inhibiting the GIDL effect resulted from the overlapped area using the thick silicon dioxide under the gate at the overlapped area so as to reduce drain currents of transistor. In addition, the method can change the high-voltage breakdown position of the transistor from a transverse junction area to a longitudinal junction area, namely, the high-voltage breakdown position of the transistor is at the strongest junction area, thereby improving the voltage endurance of the double diffusion field effect transistor.

Description

Manufacturing method of double diffusion field effect transistor

Technical field

The present invention relates to the manufacture of semiconductor technology, relate in particular to a kind of manufacturing method of double diffusion field effect transistor.

Background technology

For the conventional semiconductor process technique, bilateral diffusion field-effect tranisistor (Double DiffuseDrain MOS is called for short DDDMOS) is the high-voltage device structure of main flow, is widely used in chip for driving and power device.

As shown in Figure 1, in the prior art, all be to make double-diffused transistor as follows generally:

At first, on silicon substrate, carry out ion and inject the formation well region, in described well region, carry out the selectivity ion then and inject, form the drift region;

Then, growth one deck grid silicon oxide layer on well region;

The 3rd step, deposit one deck gate polysilicon layer on the magnificent silicon layer of described grid oxygen;

The 4th step, use known photoetching technique, described gate polysilicon layer is carried out etching, form transistorized grid;

The 5th step, on silicon substrate, carry out the selectivity source and leak the ion injection, form transistorized source electrode and drain electrode, at this moment the cross-section structure of formed double-diffused transistor is as shown in Figure 2.

Because the restriction of the method for above-mentioned common manufacturing double-diffused transistor, make to be difficult to obtain optimized result (promptly guarantee under certain puncture voltage, make saturation current reach maximum) between the saturation current of bilateral diffusion field-effect tranisistor and the puncture voltage.This mainly is because the transistor that above-mentioned common process manufacturing obtains, the dopant profiles of drift region (in a lateral direction) on channel direction does not have certain concentration gradient to change, specifically as shown in Figure 2, so when increasing the drift region doping content in order to improve saturation current when, the puncture voltage of the horizontal abrupt junction of device drift region will descend rapidly owing to the raising of drift region doping content, thereby make the puncture voltage of entire device descend rapidly.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of manufacturing method of double diffusion field effect transistor, can improve the saturation current and the puncture voltage of bilateral diffusion field-effect tranisistor, and reduces its leakage current.

For solving the problems of the technologies described above, the invention provides a kind of manufacturing method of double diffusion field effect transistor, may further comprise the steps:

(1) carries out the selectivity ion in the position of described silicon substrate well region and inject, form the drift region;

(2) at described silicon substrate grown on top layer of silicon dioxide layer;

(3) described silicon dioxide layer is carried out etching, form grid oxygen zone;

(4) one deck gate oxide of in described grid oxygen zone, growing;

(5) on described silicon dioxide layer and gate oxide, deposit one deck grid polycrystalline silicon again, form grid;

(6) on silicon substrate, carry out the selectivity source and leak the ion injection, form source-drain electrode.

The present invention has such beneficial effect owing to adopted technique scheme, promptly by increasing transistor gate and the overlapping area in drift region, transistorized saturation current is increased greatly; And utilize on the silicon dioxide layer polysilicon gate electrode potential of (being the overlapping region of grid polycrystalline silicon and drift region) of extending out to change the distribution of drift region surface field, reach the purpose that improves puncture voltage; Utilize silicon dioxide layer to suppress GIDL (Gate Induced Drain Leakage, the drain terminal leakage current that the grid causes) effect that the overlapping region because of grid and drift region causes simultaneously, reduce the leakage current of device; And, the method of the invention can also make the position of device high-voltage breakdown become vertical tie region from the lateral junction zone, the position that just makes device generation under high pressure puncture occurs in the position of the strongest knot, thereby has improved the voltage endurance of bilateral diffusion field-effect tranisistor.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the process chart of the bilateral diffusion field-effect tranisistor of prior art manufacturing;

Fig. 2 is the structural representation according to the bilateral diffusion field-effect tranisistor of prior art manufacturing;

The flow chart of an embodiment of Fig. 3 manufacturing method of double diffusion field effect transistor of the present invention;

Fig. 4 a-4f is according to the sectional structure chart in the described method manufacturing of Fig. 3 bilateral diffusion field-effect tranisistor process;

Fig. 5 a is the high-voltage breakdown position view to the bilateral diffusion field-effect tranisistor of making according to existing technology;

Fig. 5 b is the high-voltage breakdown position view to the bilateral diffusion field-effect tranisistor of making according to the method for the invention.

Embodiment

In one embodiment, as shown in Figure 3, the method for the invention may further comprise the steps:

The first step is carried out ion and is injected the formation well region on silicon substrate, be the N transistor npn npn if persons skilled in the art should be understood that the transistor that at this moment will make, and then the ion that at this moment need inject should be the boron ion; And if the transistor of making is the P transistor npn npn, then the ion that at this moment need inject should be phosphonium ion.

Second step, carry out the selectivity ion in the position of described silicon substrate well region and inject, form the drift region, cross-section structure at this moment is shown in Fig. 4 a.One of ordinary skill in the art should be understood that then the ion that is at this moment injected should be phosphonium ion if the transistor that will make is the N transistor npn npn; And if the transistor that will make is the P transistor npn npn, then the ion that is at this moment injected should be the boron ion.

In the 3rd step, at described silicon substrate grown on top layer of silicon dioxide layer, cross-section structure at this moment is shown in Fig. 4 b;

The 4th step, use known photoetching technique, described silicon dioxide layer is carried out etching, form a raceway groove, this raceway groove is grid oxygen zone, and cross-section structure at this moment is shown in Fig. 4 c;

The 5th step, one deck gate oxide of in described grid oxygen zone, growing, and described silicon dioxide layer should be greater than 1.5 with the thickness ratio of this gate oxide, and cross-section structure at this moment is shown in Fig. 4 d;

The 6th step deposited one deck grid polycrystalline silicon again on described silicon dioxide layer and gate oxide, use known photoetching technique that described grid polycrystalline silicon is carried out the source and drain areas etching then, thereby formed grid, and cross-section structure at this moment is shown in Fig. 4 e.

The 7th step, on silicon substrate, carry out the selectivity source and leak the ion injection, form source-drain electrode.

The 8th step added the manufacture process of just having finished bilateral diffusion field-effect tranisistor of the present invention behind transistorized gate electrode, source electrode and the drain electrode respectively, and cross-section structure at this moment is shown in Fig. 4 f.

By comparison diagram 1 and Fig. 4 f as can be seen, in the last bilateral diffusion field-effect tranisistor that forms of the present invention, the area of the overlapping region of grid and drift region has increased, the area that promptly wherein not only comprises the overlapping region of grid polycrystalline silicon and gate oxide and drift region, therefore the area that also comprises the overlapping region of grid polycrystalline silicon and silicon dioxide layer and drift region makes the saturation current of described bilateral diffusion field-effect tranisistor obtain obtaining greatly.And the current potential of the polysilicon gate of the overlapping region of grid polycrystalline silicon and drift region can change the Electric Field Distribution on surface, drift region, thereby reaches the purpose that improves puncture voltage; And silicon dioxide layer wherein also can be used to suppress the GIDL effect that causes because of the overlapping region, thereby has also reduced the leakage current of device to a certain extent.

As shown in table 1, for having TCAD (technology and the device technology computer-aided design) simulation result of bilateral diffusion field-effect tranisistor that technology realizes and the bilateral diffusion field-effect tranisistor of realizing according to the present invention now, from this simulation result as can be seen, the present invention is with respect to prior art, puncture voltage (BVdss) and saturation current (Idsat) are improved, and especially saturation current has obtained raising to a great extent; And leakage current (Ioff) has also reduced.

Table 1

And, by comparison diagram 5a and 5b, the method of the invention can also make the position of high-voltage breakdown become vertical tie region by the lateral junction zone as can be seen, the position that just makes device generation under high pressure puncture occurs in the position of the strongest knot, thereby has improved the voltage endurance of bilateral diffusion field-effect tranisistor to a certain extent.

Claims (2)

1, a kind of manufacturing method of double diffusion field effect transistor is characterized in that, may further comprise the steps:

(1) carries out the selectivity ion in the position of described silicon substrate well region and inject, form the drift region;

(2) at described silicon substrate grown on top layer of silicon dioxide layer;

(3) described silicon dioxide layer is carried out etching, form grid oxygen zone;

(4) one deck gate oxide of in described grid oxygen zone, growing;

(5) on described silicon dioxide layer and gate oxide, deposit one deck grid polycrystalline silicon again, form grid;

(6) on silicon substrate, carry out the selectivity source and leak the ion injection, form source-drain electrode.

According to the described manufacturing method of double diffusion field effect transistor of claim 1, it is characterized in that 2, described silicon dioxide layer should be greater than 1.5 with the thickness ratio of described gate oxide.

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