CN103000744A - 背面入射型半导体受光元件 - Google Patents
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Abstract
本发明提供一种能够提高响应速度以及效率的背面入射型半导体受光元件。在n型InP基板(l)上依次设置有n型InP层(2)、InGaAs光吸收层(3)、非掺杂InP层(4)。在非掺杂InP层(4)的一部分设置有掺杂Zn的p型杂质扩散区域(5)。n型InP层(2)和p型杂质扩散区域(5)经由InGaAs光吸收层(3)进行pn接合的部分是接收从n型InP基板(1)的背面入射的入射光的受光部(9)。以在平面视图中包围受光部(9)的方式在n型InP基板(1)的背面设置有槽(10)。
Description
技术领域
本发明涉及入射光从半导体基板的背面侧入射的背面入射型半导体受光元件。
背景技术
伴随近年来的信息通信量的增大,在使用了半导体激光器和光纤的光传输***中,由传输速度的高速化带来的大容量化不断发展。对于在光传输***中使用的半导体受光元件,也强烈要求提高响应速度。在光传输***中使用的半导体受光元件需要吸收1.3μm频带或1.55μm频带的入射光,所以,通常使用采用了InP基板的pin光电二极管。
为了提高pin光电二极管的响应速度而减小受光部(pn结部)的面积并降低元件容量是有效的。例如,为了实现40Gbit/秒的动作而需要使受光部的直径缩小到10μm左右。
但是,在表面入射型pin光电二极管中,入射光被在元件表面设置的电极遮挡而效率下降,所以,减小受光直径是困难的。因此,在要求10Gbit/秒以上的高速响应的***中,即使减小受光直径也难以受到电极的影响的背面入射型光电二极管是合适的。
但是,背面入射型光电二极管也难以应对今后的40Gbit/秒以上的高速响应。此外,考虑到为了减小容量而使光吸收层变厚,但是,在光吸收层内产生的电子和空穴在吸收层内移动的时间变长,响应特性恶化。因此,提出了如下技术:利用在元件外部设置的聚光透镜对光进行聚光,使其入射到受光元件(例如,参照专利文献l)。
专利文献1:日本特开2008-270679号公报。
在制造背面入射型半导体受光元件时,若使半导体基板变薄,则强度降低,在工艺中发生基板破裂。因此,需要使半导体基板的厚度为100μm左右。因此,即使利用聚光透镜对光进行聚光,入射光也在厚的半导体基板内发散,效率下降。越是为了提高响应速度而减小受光面积,越不能够忽视光在半导体基板内的发散。
发明内容
本发明是为了解决上述课题而提出的,其目的在于得到一种能够提高响应速度以及效率的背面入射型半导体受光元件。
本发明提供一种背面入射型半导体受光元件,其特征在于,具有:第一导电型的半导体基板;第一导电型的第一半导体层,设置在所述半导体基板上;光吸收层,设置在所述第一半导体层上;第二半导体层,设置在所述光吸收层上;第二导电型的杂质扩散区域,设置于所述第二半导体层的一部分,所述第一半导体层和所述杂质扩散区域经由所述光吸收层进行pn接合的部分是接收从所述半导体基板的背面入射的入射光的受光部,以在平面视图中包围所述受光部的方式在所述半导体基板的背面设置有槽。
根据本发明,能够提高响应速度以及效率。
附图说明
图1是表示本发明的实施方式1的背面入射型半导体受光元件的剖视图。
图2是表示本发明的实施方式1的背面入射型半导体受光元件的制造工序的剖视图。
图3是表示本发明的实施方式1的背面入射型半导体受光元件的制造工序的剖视图。
图4是表示本发明的实施方式1的背面入射型半导体受光元件的制造工序的剖视图。
图5是表示本发明的实施方式1的背面入射型半导体受光元件的制造工序的剖视图。
图6是表示本发明的实施方式1的背面入射型半导体受光元件的制造工序的剖视图。
图7是表示本发明的实施方式1的背面入射型半导体受光元件的制造工序的剖视图。
图8是表示本发明的实施方式2的背面入射型半导体受光元件的剖视图。
图9是表示本发明的实施方式3的背面入射型半导体受光元件的剖视图。
图10是表示本发明的实施方式4的背面入射型半导体受光元件的剖视图。
图11是表示本发明的实施方式5的背面入射型半导体受光元件的剖视图。
图12是表示本发明的实施方式6的背面入射型半导体受光元件的剖视图。
其中,附图标记说明如下:
1 n型InP基板(半导体基板)
2 n型InP层(第一半导体层)
3 InGaAs光吸收层(光吸收层)
4 非掺杂InP层(第二半导体层)
5 p型杂质扩散区域(杂质扩散区域)
9 受光部
10 槽
14 反射膜
15 低反射膜
16 微透镜(透镜)。
具体实施方式
参照附图对本发明的实施方式的背面入射型半导体受光元件进行说明。对相同或对应的结构要素标注相同的附图标记,有时省略重复说明。
实施方式1
图l是本发明的实施方式1的背面入射型半导体受光元件的剖视图。在n型InP基板1上依次设置有n型InP层2、InGaAs光吸收层3、非掺杂InP层4。
在非掺杂InP层4的一部分设置有掺杂Zn的p型杂质扩散区域5。在p型杂质扩散区域5的两侧设置有InP埋入层6。在非掺杂InP层4以及InP埋入层6上设置有SiN膜7。在SiN膜7上,在p型杂质扩散区域5之上设置有开口。经由该开口,在p型杂质扩散区域5上设置有p侧欧姆电极8。
n型InP层2和p型杂质扩散区域5经由InGaAs光吸收层3进行pn接合的部分是接收从n型InP基板1的背面入射的入射光的受光部9。以在平面视图中包围受光部9的方式在n型InP基板1的背面设置有槽10。
在n型InP基板1的背面设置有n侧欧姆电极11。n侧欧姆电极11具有在平面视图中内包受光部9的开口。在该n侧欧姆电极11的开口内设置有槽10。
接着,对实施方式1的背面入射型半导体受光元件的制造方法进行说明。首先,如图2所示,在n型InP基板l上依次生长n型InP层2、InGaAs光吸收层3、非掺杂InP层4。
接着,如图3所示,以覆盖受光部9的方式在非掺杂InP层4上形成直径为20μm的圆状的SiO2膜12(膜厚为200nm)。将该SiO2膜12作为掩模,从非掺杂InP层4的表面开始刻蚀除去至n型InP层2的中途。此外,SiO2膜12的直径并不限于20μm,选择能够实现所需的元件容量的尺寸即可。
接着,如图4所示,埋入生长InP埋入层6。优选InP埋入层6是高电阻,但是,由于绝缘性的InP的生长是困难的,所以,掺杂例如Fe或Ru等。
接着,如图5所示,除去SiO2膜12,在晶片表面形成SiO2膜13。并且,在受光部9处,在SiO2膜13上形成开口。在SiO2膜13之上形成成为扩散源的ZnO膜,使Zn从晶片表面呈直径为10μm的圆状扩散至受光部9。通过进行热扩散处理,从而形成p型杂质扩散区域5。Zn扩散进行到扩散锋(diffusion front)到达InGaAs光吸收层3内为止。
接着,如图6所示,在除去SiO2膜13和ZnO膜之后,在晶片表面形成SiN膜7作为表面保护膜。在p型杂质扩散区域5上形成p侧欧姆电极8。此外,也可以在非掺杂InP层4上设置InGaAsP或InGaAs等带隙比InP小的接触层。此外,也可以在p侧欧姆电极8和半导体层之间存在一部分SiN膜7。
接着,如图7所示,使n型InP基板1薄到约100μm的厚度。以在平面视图中包围受光部9的方式,利用刻蚀在n型InP基板1的背面形成槽10。槽10的直径是约50μm,宽度是10μm,深度是约10μm。在n型InP基板1的厚度为100μm的情况下,使槽10的直径相对于受光部9的直径扩大30~50μm左右即可。
最后,如图l所示,在n型InP基板l的背面形成n侧欧姆电极11。通过以上的工序制造本实施方式的背面入射型半导体受光元件。
接着,对本实施方式的效果进行说明。入射光是从位于距离受光元件数十~数百μm的场所的光纤或光波导发送来的,所以,不仅包括与n型InP基板l的背面垂直入射的光,而且包括倾斜入射的光。因此,在本实施方式中,以在平面视图中包围受光部9的方式在n型InP基板l的背面设置槽10。由此,倾斜入射的光被包围受光部9的槽10全反射而效率较好地导向受光部9。因此,到达受光部9的入射光增加,所以,效率提高。即使为了提高响应速度而减小受光面积,也得到该效果。因而,根据本实施方式,能够提高响应速度以及效率。
由于槽10越深越能够效率较好地对光进行聚光,所以,优选槽10设置至n型InP基板l和n型InP层2的界面附近为止。由于利用了在槽10内的空气与半导体的边界面的全反射,所以,槽10的宽度并不被限制。
实施方式2
图8是表示本发明的实施方式2的背面入射型半导体受光元件的剖视图。在实施方式1中,利用在槽10内的空气与半导体的边界面的全反射,但是,在本实施方式中,在槽10的侧壁设置对入射光进行反射的反射膜14。
反射膜14是由例如SiN膜和Au膜构成的二层膜。能够利用该反射膜14的Au膜提高在槽10的侧壁的反射率。也可以使用例如Ag、Al、Cu等其他金属或电介质多层膜等来代替Au膜。SiN膜防止n型InP基板1和Au直接接触而发生合金化反应。SiN膜的膜厚d(nm)以如下方式设定:当将SiN的折射率设为nr、将入射光的波长设为λ(nm)时,满足d=λ/(4×nr)。
实施方式3
图9是本发明的实施方式3的背面入射型半导体受光元件的剖视图。在本实施方式中,n型InP基板l的背面和槽10的侧壁的角度小于90度。由此,在槽10的侧壁被全反射的入射光被导向受光部9的中心部。因此,与实施方式1相比,能够进一步提高效率。
作为形成这样的槽10的方法,存在如下方法:将抗蚀剂或绝缘膜作为刻蚀掩模,利用SiC14/Ar或C12/Ar混合气体进行干法刻蚀;利用溴和甲醇的混合液进行刻蚀。
实施方式4
图10是表示本发明的实施方式4的背面入射型半导体受光元件的剖视图。在本实施方式中,在n型InP基板l的背面的被槽10包围的受光区域设置有低反射膜15,该低反射膜15针对具有1.3~1.5μm频带的波长的入射光的反射率为1%以下。
低反射膜15是SiN膜、SiO2膜、Al2O3膜等电介质膜。低反射膜15的膜厚以如下方式设定:相对于入射光的中心波长λ为λ/(4×nr)。此处,nr是低反射膜15的折射率。
在n型InP基板1的背面的受光区域设置低反射膜15,由此,能够抑制基板背面的在半导体与空气的界面的反射,能够不浪费地将入射光导入到半导体内。
实施方式5
图11是表示本发明的实施方式5的背面入射型半导体受光元件的剖视图。在本实施方式中,在n型InP基板l的背面的被槽10包围的受光区域设置有凸状的微透镜16。能够利用微透镜16积极地将入射光取入到受光部9,所以,与实施方式1相比,能够进一步提高效率。
在实施方式1的制造方法中,在使n型InP基板1变薄之后,在受光区域形成抗蚀剂,将该抗蚀剂作为掩模,利用溴水、过氧化氢、纯水的混合液进行刻蚀,由此,形成微透镜16。或者,在受光区域形成抗蚀剂之后,以200℃左右进行烘烤,使抗蚀剂热变形,然后,利用溅射刻蚀进行刻蚀,直到抗蚀剂消失为止,由此,形成微透镜16。
实施方式6
图12是表示本发明的实施方式6的背面入射型半导体受光元件的剖视图。在本实施方式中,从元件表面侧起至n型InP基板1或n型InP层2为止设置有槽17。槽17的侧壁被绝缘膜18覆盖。n侧欧姆电极11在槽10的底部与n型InP基板1或n型InP层2连接,并且在与p侧欧姆电极8同一表面上延伸。
由此,能够在晶片表面侧设置n侧欧姆电极11和p侧欧姆电极8这两者,所以,能够使用倒装接合(flip-chip bonding)。因此,与通常的引线连接相比,能够降低电感,容易得到高速响应特性。
此外,在上述的实施方式1~6中,对波长为1.3μm~1.55μm的入射光进行吸收,所以,使用InGaAs光吸收层3,但是,作为光吸收层,使用能够吸收所需的波长的入射光的材料即可。例如,如果仅将波长为1.3μm频带的入射光作为对象,则作为光吸收层,可以使用InGaAsP。
此外,在上述的实施方式1~6中,使用了pin光电二极管,但是,即便是APD(雪崩光电二极管),也得到同样的效果。
Claims (6)
1.一种背面入射型半导体受光元件,其特征在于,具有:
第一导电型的半导体基板;
第一导电型的第一半导体层,设置在所述半导体基板上;
光吸收层,设置在所述第一半导体层上;
第二半导体层,设置在所述光吸收层上;以及
第二导电型的杂质扩散区域,设置于所述第二半导体层的一部分,
所述第一半导体层和所述杂质扩散区域经由所述光吸收层进行pn接合的部分是接收从所述半导体基板的背面入射的入射光的受光部,
以在平面视图中包围所述受光部的方式在所述半导体基板的背面设置有槽。
2.如权利要求1所述的背面入射型半导体受光元件,其特征在于,
所述槽设置至所述半导体基板和所述第一半导体层的界面附近为止。
3.如权利要求1或2所述的背面入射型半导体受光元件,其特征在于,
还具有设置在所述槽的侧壁并且对所述入射光进行反射的反射膜。
4.如权利要求1或2所述的背面入射型半导体受光元件,其特征在于,
所述半导体基板的背面和所述槽的侧壁的角度小于90度。
5.如权利要求1或2所述的背面入射型半导体受光元件,其特征在于,
还具有:低反射膜,设置在所述半导体基板的背面的被所述槽包围的受光区域,并且,针对所述入射光的反射率为1%以下。
6.如权利要求1或2所述的背面入射型半导体受光元件,其特征在于,
在所述半导体基板的背面的被所述槽包围的受光区域设置有凸状的透镜。
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JP2011196694A JP2013058656A (ja) | 2011-09-09 | 2011-09-09 | 裏面入射型半導体受光素子 |
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CN111801610A (zh) * | 2018-02-19 | 2020-10-20 | 三菱电机株式会社 | 半导体光集成器件 |
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JP2014093482A (ja) | 2012-11-06 | 2014-05-19 | Toshiba Corp | 固体撮像装置の製造方法および固体撮像装置 |
JP2015162576A (ja) * | 2014-02-27 | 2015-09-07 | 住友電気工業株式会社 | 半導体光集積素子、半導体光集積素子を作製する方法 |
US10553742B2 (en) * | 2016-10-28 | 2020-02-04 | Mitsubishi Electric Corporation | Back-surface-incident type light-receiving device and optical module |
WO2020134537A1 (zh) * | 2018-12-25 | 2020-07-02 | 芯思杰技术(深圳)股份有限公司 | 光电芯片、制备方法和安装方法 |
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KR100464333B1 (ko) | 2003-03-28 | 2005-01-03 | 삼성전자주식회사 | 수광소자 및 그 제조방법 |
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- 2012-09-03 KR KR1020120096926A patent/KR101391877B1/ko not_active IP Right Cessation
- 2012-09-07 CN CN2012103290100A patent/CN103000744A/zh active Pending
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US6784512B2 (en) * | 2001-03-23 | 2004-08-31 | Sumitomo Electric Industries, Ltd. | Photodiode and method of producing same |
US6894322B2 (en) * | 2002-02-11 | 2005-05-17 | Jds Uniphase Corporation | Back illuminated photodiodes |
US20070045513A1 (en) * | 2005-08-30 | 2007-03-01 | Lee Ji S | Image sensors with optical trench |
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JP2013058656A (ja) | 2013-03-28 |
KR20130028662A (ko) | 2013-03-19 |
KR101391877B1 (ko) | 2014-05-07 |
US8519501B2 (en) | 2013-08-27 |
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