CN102938374B - The phosphorus of semi-conductor discrete device wafer-level packaging penetrates process - Google Patents
The phosphorus of semi-conductor discrete device wafer-level packaging penetrates process Download PDFInfo
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- CN102938374B CN102938374B CN201210446190.0A CN201210446190A CN102938374B CN 102938374 B CN102938374 B CN 102938374B CN 201210446190 A CN201210446190 A CN 201210446190A CN 102938374 B CN102938374 B CN 102938374B
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Abstract
The phosphorus of semi-conductor discrete device wafer-level packaging penetrates a process, processing step: adopt phosphoric diffusion technology 3 ' (N2)+19′(N2+POCl3)+5′(N2) technology carries out phosphorus prediffusion in reserved phosphorus penetration region; Adopt conventional oxidized diffusion technique 10 ' (O2)+（20~120）′(O2+H2)+10′(O2) carry out phosphorus diffusion technique again, the penetration region designing is diffused out to the phosphorus doping region of subscribing resistance value (0.8 ~ 20.0 Ω), realize chip back electrode and cause front. The present invention penetrates technology by phosphorus the electrode of discrete device different surfaces is caused to homonymy, and making discrete device chip directly be used in complete machine becomes possibility. Discrete device product is made into theoretical minimum dimension by this technique, and then further accelerate the process of miniaturization of electronic products, portability. Reduced chip package secondary operations link, greatly the reliability of boost device simultaneously.
Description
Technical field
The present invention relates to semi-conductor discrete device and realize wafer-level packaging (WLP) technical field, particularly use phosphorus to wearTechnology realizes relative two the surperficial electrodes of discrete device and causes the same face thoroughly, realizes the skill that chip can directly useArt is that a kind of phosphorus of semi-conductor discrete device wafer-level packaging penetrates process specifically.
Background technology
Phosphorus penetrates the critical process that technology is wafer-level packaging (WLP) product, and using can be by wafer after this techniqueThe electrode fabrication of the chip different surfaces of level encapsulation (WLP) product requirement, at homonymy, is realized chip and can be directly used in complete machine,Reduce encapsulation secondary operations, reduce material consumption, shorten chip manufacturing flow process. Along with miniaturization of electronic products, portability demandContinuous lifting, it has been the direction of current electronic devices and components development that chip volume constantly dwindles, wafer-level packaging (WLP) product willMake chip volume be reduced to minimum of a value, further advance the process of miniaturization of electronic products, portability. This technology application is raw simultaneouslyThe product reliability of producing will be promoted greatly owing to reducing chip secondary encapsulation processing link.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of semiconductor that can realize discrete device wafer-level packaging and dividesThe phosphorus of vertical device wafers level encapsulation penetrates process.
Technical problem of the present invention adopts following technical scheme to solve:
The phosphorus of semi-conductor discrete device wafer-level packaging penetrates a process, comprises the following steps:
A) structure of redesign discrete device: in the periphery design phosphorus penetrating region of conventional discrete device part or bodyTerritory, for phosphorus penetrates technology headspace;
B) adopt phosphoric diffusion technology 3 ' (N2)+19′(N2+POCl3)+5′(N2) technology enters in reserved phosphorus penetration regionThe prediffusion of row phosphorus;
C) adopt conventional oxidized diffusion technique 10 ' (O2)+（20~120）′(O2+H2)+10′(O2) carry out phosphorus and spread again workSkill, diffuses out the penetration region designing in the phosphorus doping region of subscribing resistance value (0.8 ~ 20.0 Ω), realizes chip back electricityThe utmost point causes front.
The present invention starts with from chip design, changes conventional discrete device design, is conventional discrete device design phosphorus penetrating regionTerritory, penetrates technology by phosphorus the electrode of discrete device different surfaces is caused to homonymy, for discrete device chip directly usesBecome possibility with complete machine. This technology will advance the large-scale production of discrete device wafer-level packaging (WLP) product greatly, willDiscrete device product is made into theoretical minimum dimension, and then further accelerates the process of miniaturization of electronic products, portability. WaferLevel encapsulation (WLP) product not only can be realized chip volume and minimize, and has reduced chip package secondary operations link simultaneously, reducesChip manufacture flow process, and then created strong condition for the raising of product reliability.
Brief description of the drawings
Fig. 1 is conventional semi-conductor discrete device structure front view;
Fig. 2 is conventional semi-conductor discrete device structural section figure;
Fig. 3 is semi-conductor discrete device partial penetration structural representation of the present invention;
Fig. 4 is semi-conductor discrete device partial penetration structural section figure of the present invention;
Fig. 5 is the periphery penetrant structure front view of semi-conductor discrete device body of the present invention;
Fig. 6 is the periphery penetrant structure sectional view of semi-conductor discrete device body of the present invention.
1. conventional semi-conductor discrete device active areas in figure, the semi-conductor discrete device phosphorus that 2. uses phosphorus to penetrate technique penetratesRegion.
Detailed description of the invention
Below in conjunction with drawings and Examples, the present invention will be further described, taking Schottky barrier commutation diode as example:
Fig. 3 is semi-conductor discrete device partial penetration structure front view of the present invention, in conventional semi-conductor discrete devicePortion makes penetration region (as shown in Figure 3), reaches backplate and guides to positive object, has changed conventional semi-conductor discrete deviceStructural design. Fig. 5 is the periphery penetrant structure front view of semi-conductor discrete device body of the present invention, divides at conventional semiconductorThe periphery of vertical device is made penetration region (as shown in Figure 5), reaches backplate and guides to positive object, has changed routine and has partly ledThe structural design of body discrete device.
Fig. 4 newly-designed semi-conductor discrete device partial penetration structural section figure that attaches most importance to, at conventional semi-conductor discrete deviceInternal production penetration region (as shown in Figure 4), reaches backplate and guides to positive object. Fig. 6 newly-designed semiconductor of attaching most importance toThe periphery penetrant structure sectional view of discrete device body, makes penetration region (as Fig. 6 at the periphery of conventional semi-conductor discrete deviceShown in), reach backplate and guide to positive object.
As can be seen from Figure, the electrode in chip back is directed to front by phosphorus penetration region, reaches chip electricityThe utmost point is in the object of homonymy.
The semi-conductor discrete device that adopts phosphorus to penetrate technology making by comparative descriptions has been realized chip different surfacesElectrode be directed to homonymy, for chip directly uses with complete machine and becomes possibility.
Embodiment 1
1, redesign the structure of discrete device: (2 regions in seeing Fig. 3,4) pass through reticle in conventional discrete device partFigure design, and penetrate diffusion technique making phosphorus penetration region in conjunction with phosphorus;
2, phosphoric diffusion technology process:
1. the wafer cleaning that uses the cleaning method of standard 1# washing lotion+2# washing lotion that penetration region photoetching is completed is clean;
2. wafer is packed into phosphorus diffusion Quartz stove tube, operation process, 1050 DEG C of technological temperatures, 3 ' (N2)+19′(N2+POCl3)+5′(N2)；
3. technique completes wafer to take out and pack in time special oxidation boiler tube into and carries out oxidized diffusion technique; This technology is in advanceThe phosphorus penetration region of staying is carried out phosphorus prediffusion;
3, oxidized diffusion technical process:
1. wafer phosphoric diffusion technology being completed packs special oxidation boiler tube into;
2. operation process, 1050 DEG C of technological temperatures, 10 ' (O2)+20′(O2+H2)+10′(O2)；
3. technique completes and wafer is taken out and sent patterned area, enters conventional schottky processing technology; This phosphorus againDiffusion technique, diffuses out the penetration region designing in the phosphorus doping region of subscribing resistance value 0.8 Ω, realizes chip back electrodeCause front.
Embodiment 2
1, redesign the structure of discrete device: the periphery (as shown in Figure 5,6) at conventional discrete device body passes through lightCarve layout design, and penetrate diffusion technique making phosphorus penetration region in conjunction with phosphorus;
2, phosphoric diffusion technology process:
1. the wafer cleaning that uses the cleaning method of standard 1# washing lotion+2# washing lotion that penetration region photoetching is completed is clean;
2. wafer is packed into phosphorus diffusion Quartz stove tube, operation process, 1050 DEG C of technological temperatures, 3 ' (N2)+19′(N2+POCl3)+5′(N2)；
3. technique completes wafer to take out and pack in time special oxidation boiler tube into and carries out oxidized diffusion technique; This technology is in advanceThe phosphorus penetration region of staying is carried out phosphorus prediffusion;
3, oxidized diffusion technical process: the wafer 1. phosphoric diffusion technology being completed packs special oxidation boiler tube into; 2. move workSkill, 1050 DEG C of technological temperatures, 10 ' (O2)+120′(O2+H2)+10′(O2); 3. technique completes and wafer is taken out and send photoetching districtTerritory, enters conventional schottky processing technology; This phosphorus diffusion technique again, diffuses out the penetration region designing to subscribe electricityThe phosphorus doping region of resistance 20.0 Ω, realizes chip back electrode and causes front.
Embodiment 3
1, redesign the structure of discrete device: (2 regions in seeing Fig. 3,4) pass through reticle in conventional discrete device partFigure design, and penetrate diffusion technique making phosphorus penetration region in conjunction with phosphorus;
2, phosphoric diffusion technology process:
1. the wafer cleaning that uses the cleaning method of standard 1# washing lotion+2# washing lotion that penetration region photoetching is completed is clean;
2. wafer is packed into phosphorus diffusion Quartz stove tube, operation process, 1050 DEG C of technological temperatures, 3 ' (N2)+19′(N2+POCl3)+5′(N2)；
3. technique completes wafer to take out and pack in time special oxidation boiler tube into and carries out oxidized diffusion technique; This technology is in advanceThe phosphorus penetration region of staying is carried out phosphorus prediffusion;
3, oxidized diffusion technical process: the wafer 1. phosphoric diffusion technology being completed packs special oxidation boiler tube into; 2. move workSkill, 1050 DEG C of technological temperatures, 10 ' (O2)+40′(O2+H2)+10′(O2); 3. technique completes and wafer is taken out and send photoetching districtTerritory, enters conventional schottky processing technology; This phosphorus diffusion technique again, diffuses out the penetration region designing to subscribe electricityThe phosphorus doping region of resistance 4.0 Ω, realizes chip back electrode and causes front.
Embodiment 4
1, redesign the structure of discrete device: (2 regions in seeing Fig. 3,4) pass through reticle in conventional discrete device partFigure design, and penetrate diffusion technique making phosphorus penetration region in conjunction with phosphorus;
2, phosphoric diffusion technology process:
1. the wafer cleaning that uses the cleaning method of standard 1# washing lotion+2# washing lotion that penetration region photoetching is completed is clean;
2. wafer is packed into phosphorus diffusion Quartz stove tube, operation process, 1050 DEG C of technological temperatures, 3 ' (N2)+19′(N2+POCl3)+5′(N2)；
3. technique completes wafer to take out and pack in time special oxidation boiler tube into and carries out oxidized diffusion technique; This technology is in advanceThe phosphorus penetration region of staying is carried out phosphorus prediffusion;
3, oxidized diffusion technical process: the wafer 1. phosphoric diffusion technology being completed packs special oxidation boiler tube into; 2. move workSkill, 1050 DEG C of technological temperatures, 10 ' (O2)+80′(O2+H2)+10′(O2); 3. technique completes and wafer is taken out and send photoetching districtTerritory, enters conventional schottky processing technology; This phosphorus diffusion technique again, diffuses out the penetration region designing to subscribe electricityThe phosphorus doping region of resistance 10.0 Ω, realizes chip back electrode and causes front.
Embodiment 5
1, redesign the structure of discrete device: the periphery (as shown in Figure 5,6) at conventional discrete device body passes through lightCarve layout design, and penetrate diffusion technique making phosphorus penetration region in conjunction with phosphorus;
2, phosphoric diffusion technology process:
1. the wafer cleaning that uses the cleaning method of standard 1# washing lotion+2# washing lotion that penetration region photoetching is completed is clean;
2. wafer is packed into phosphorus diffusion Quartz stove tube, operation process, 1050 DEG C of technological temperatures, 3 ' (N2)+19′(N2+POCl3)+5′(N2)；
3. technique completes wafer to take out and pack in time special oxidation boiler tube into and carries out oxidized diffusion technique; This technology is in advanceThe phosphorus penetration region of staying is carried out phosphorus prediffusion;
3, oxidized diffusion technical process:
1. wafer phosphoric diffusion technology being completed packs special oxidation boiler tube into;
2. operation process, 1050 DEG C of technological temperatures, 10 ' (O2)+100′(O2+H2)+10′(O2)；
3. technique completes and wafer is taken out and sent patterned area, enters conventional schottky processing technology; This phosphorus againDiffusion technique, diffuses out the penetration region designing in the phosphorus doping region of subscribing resistance value 16.0 Ω, realizes chip back electricityThe utmost point causes front.
Claims (1)
1. the phosphorus of semi-conductor discrete device wafer-level packaging penetrates a process, it is characterized in that comprising the following steps:
A) structure of redesign discrete device: in the periphery design phosphorus penetration region of conventional discrete device part or body, forPhosphorus penetrates technology headspace;
B) adopt phosphoric diffusion technology 3 ' (N2)+19′(N2+POCl3)+5′(N2), carry out phosphorus pre-expansion in reserved phosphorus penetration regionLoose;
C) adopt conventional oxidized diffusion technique 10 ' (O2)+（20~120）′(O2+H2)+10′(O2) carry out phosphorus diffusion technique again,The penetration region designing is diffused out to the phosphorus doping region of subscribing resistance value 0.8 ~ 20.0 Ω, realize chip back electrode and causePositive.
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| CN102315122A (en) * | 2011-10-20 | 2012-01-11 | 无锡友达电子有限公司 | Process for manufacturing bipolar-type device by adopting two-time stibium buried-layer extending technology |
| CN102629647A (en) * | 2012-05-03 | 2012-08-08 | 上海联孚新能源科技有限公司 | Manufacture method of solar battery |
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| CN102315122A (en) * | 2011-10-20 | 2012-01-11 | 无锡友达电子有限公司 | Process for manufacturing bipolar-type device by adopting two-time stibium buried-layer extending technology |
| CN102629647A (en) * | 2012-05-03 | 2012-08-08 | 上海联孚新能源科技有限公司 | Manufacture method of solar battery |
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