CN202534653U - Mesa-type unidirectional negative resistance diode chip - Google Patents
Mesa-type unidirectional negative resistance diode chip Download PDFInfo
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- CN202534653U CN202534653U CN2011205016775U CN201120501677U CN202534653U CN 202534653 U CN202534653 U CN 202534653U CN 2011205016775 U CN2011205016775 U CN 2011205016775U CN 201120501677 U CN201120501677 U CN 201120501677U CN 202534653 U CN202534653 U CN 202534653U
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- diffusion layer
- negative resistance
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Abstract
The utility model discloses a mesa-type unidirectional negative resistance diode chip. An impurity which has an opposite conduction type with a silicon chip is doped in a side of the silicon chip to form a first diffusion layer and a first PN junction. An impurity which has the same conduction type with the silicon chip is doped on a surface of the first diffusion layer, impurity concentration being higher than dosage concentration of the first diffusion layer, so as to form a second diffusion layer and a second PN junction. A distance between the first PN junction and the second PN junction is 2-15 micrometers. A passivation layer is disposed on outside ends of the first PN junction and the second PN junction which are exposed on side walls of a boss. Metal layers are disposed on a table of the boss and on a bottom of the silicon chip. The mesa-type unidirectional negative resistance diode chip is characterized by relative low manufacture cost, simple manufacturing method, and can realize a full-automatic work mode, etc.
Description
Technical field
The utility model relates to a kind of semiconductor device, and is especially relevant with the unidirectional negative resistance diode chip of mesa.
Background technology
Generally use bidirectional trigger diode in the electricity-saving lamp half-bridge inverter start-up circuit, this device can be considered open base, the NPN transistor of emitter and collector symmetry.Because the needs of characteristic, the width of bidirectional trigger diode base is about about 40um.Present manufacturing process mainly is divided into two-sided synchronous diffusion or adopts the planar technique manufacturing, and the former manufacturing technology difficulty when two-sided etching is bigger, and the fragmentation loss is higher; Latter's manufacturing technology equipment input cost is higher.Consider that bidirectional trigger diode only is applied to the characteristic of one of them PN junction in electricity-saving lamp half-bridge inverter start-up circuit, research and development manufacturing cost novel semi-conductor device lower, that manufacturing approach is simple, replaceable bidirectional trigger diode is used in electricity-saving lamp half-bridge inverter start-up circuit is the main thought of the utility model.
Summary of the invention
The purpose of the utility model provides a kind of low cost of manufacture, simple, the replaceable unidirectional negative resistance diode chip of mesa that is applied to bidirectional trigger diode in the energy-conservation lamp half-bridge inverter start-up circuit of manufacturing approach.
For achieving the above object; The utility model is realized through following technical scheme: the unidirectional negative resistance diode chip of mesa; Comprise silicon chip, silicon chip wherein the impurity that mixes with the silicon chip conductivity type opposite of one side form first diffusion layer and first PN junction, identical at the first diffusion layer surface doping with the silicon chip conduction type; But impurity concentration is higher than the impurity of the high impurity concentration C2 of first diffusion layer; Form second diffusion layer and second PN junction, wherein, the high impurity concentration C2 of first diffusion layer is 10～100 times of silicon chip impurity concentration C1; The high impurity concentration C3 of second diffusion layer is 10～1000 times of the high impurity concentration C2 of first diffusion layer; The spacing of first PN junction and second PN junction is 2～15 microns, is exposed to that the two ends outside of first PN junction and second PN junction is provided with passivation layer on the sidewall of boss, is provided with metal level at the table top of boss and the bottom surface of silicon chip.
The unidirectional negative resistance diode chip of described mesa, its passivation layer are glass passivation layer or CVD deposited film, and silicon chip is an abrasive sheet.
The utility model is owing to adopted technique scheme; Compared with prior art have the following advantages: (one) has solved two table top wafers problem of middle survey automatically: for two table top wafers; Need test respectively on the branch two sides during underway survey, therefore can't realize the full-automatic probe test of wafer.First PN junction of electrical parameter only need test to(for) the utility model gets final product, and has saved the half the testing time, can realize full-automatic middle survey of wafer; (2) can realize full-automatic operation: test, get ready for two table top wafer sort time-division faces; When manipulator is got material; The figure of getting ready that is positioned at the crystal grain back side can't be by machine recognition, and therefore two table top wafers can't be realized full-automatic operation, and wherein one side is electrical owing to only needing test for the utility model; Test, get ready all and can accomplish, therefore can realize full-automatic operation in one side; Adopt single face photoetching, corroding method during (three) for two plane PN junction close together, it is simple to operate, and mesa technique realizes that easily rate of finished products is higher; (4) the unidirectional negative resistance diode chip of mesa, its first PN junction and second PN junction are according to different positive-negative-positive or the NPN types of forming of the conduction type of silicon chip; (5) the unidirectional negative resistance diode chip of mesa that adopts technique scheme to make when in electricity-saving lamp half-bridge inverter start-up circuit, using, only needs the first PN junction reverse bias, and the second PN junction forward bias can satisfy instructions for use.
Description of drawings
Fig. 1 is existing bidirectional trigger diode characteristic curve sketch map.
Fig. 2 is the unidirectional negative resistance diode characteristic curve of a utility model mesa sketch map.
Fig. 3 is the two table top bidirectional trigger diode chip structural representations of existing NPN type.
Fig. 4 is the unidirectional negative resistance diode chip structure of a utility model NPN type mesa sketch map.
Fig. 5 is each conductive layer Impurity Distribution sketch map of the unidirectional negative resistance diode chip of the utility model mesa.
Embodiment
Embodiment to the utility model is described in further detail below in conjunction with accompanying drawing.
Like Fig. 4 and shown in Figure 5, the unidirectional negative resistance diode chip of mesa comprises silicon chip 1; Silicon chip 1 wherein the impurity that mixes with silicon chip 1 conductivity type opposite of one side form first diffusion layer 2 and first PN junction 4; Identical at first diffusion layer, 2 surface dopings with silicon chip 1 conduction type, but impurity concentration is higher than the impurity of first diffusion layer, 2 high impurity concentration C2, forms second diffusion layer 3 and second PN junction 5; Wherein, The high impurity concentration C2 of first diffusion layer 2 is 30 times of silicon chip 1 impurity concentration C1, and the high impurity concentration C3 of second diffusion layer 3 is 100 times of first diffusion layer, 2 high impurity concentration C2, and the spacing 6 of first PN junction 4 and second PN junction 5 is 5 microns; Be exposed to that the two ends outside of first PN junction 4 and second PN junction 5 is provided with passivation layer 9 on the sidewall 8 of boss 7; Be provided with metal level 12 at the table top 10 of boss 7 and the bottom surface 11 of silicon chip 1, passivation layer 9 is glass passivation layer or CVD deposited film, and silicon chip 1 is an abrasive sheet.
Claims (2)
1. unidirectional negative resistance diode chip of mesa; Comprise silicon chip (1); It is characterized in that: wherein be respectively equipped with first diffusion layer (2) and first PN junction (4) and second diffusion layer (3) and second PN junction (5) on the one side at silicon chip (1); The spacing (6) of first PN junction (4) and second PN junction (5) is 2～15 microns; Be exposed to last first PN junction of sidewall (8) (4) of boss (7) and the two ends outside of second PN junction (5) and be provided with passivation layer (9), be provided with metal level (12) at the table top (10) of boss (7) and the bottom surface (11) of silicon chip (1).
2. the unidirectional negative resistance diode chip of mesa according to claim 1 is characterized in that: passivation layer (9) is glass passivation layer or CVD deposited film, and silicon chip (1) is an abrasive sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205016775U CN202534653U (en) | 2011-12-06 | 2011-12-06 | Mesa-type unidirectional negative resistance diode chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205016775U CN202534653U (en) | 2011-12-06 | 2011-12-06 | Mesa-type unidirectional negative resistance diode chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202534653U true CN202534653U (en) | 2012-11-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205016775U Expired - Lifetime CN202534653U (en) | 2011-12-06 | 2011-12-06 | Mesa-type unidirectional negative resistance diode chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202534653U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437199A (en) * | 2011-12-06 | 2012-05-02 | 绍兴旭昌科技企业有限公司 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
-
2011
- 2011-12-06 CN CN2011205016775U patent/CN202534653U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437199A (en) * | 2011-12-06 | 2012-05-02 | 绍兴旭昌科技企业有限公司 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: ZHEJIANG MINGDE MICROELECTRONICS CO., LTD. Free format text: FORMER NAME: SHAOXING RISING-SUN TECHNOLOGY CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 312000 Longshan Software Park, Shaoxing Economic Development Zone, Shaoxing, Zhejiang Patentee after: ZHEJIANG MINGDE MICROELECTRONIC CO., LTD. Address before: 312000 Longshan science and Technology Park, East Mountain Road, Shaoxing Economic Development Zone, Shaoxing, Zhejiang Patentee before: Shaoxing Rising-sun Technology Co., Ltd. |
|
| CX01 | Expiry of patent term |
Granted publication date: 20121114 |
|
| CX01 | Expiry of patent term |