CN106209722A - A kind of multi-path digital down conversion method for baseband signal receiver - Google Patents

Abstract

The invention belongs to communication technical field, relate to a kind of multi-path digital down conversion method for baseband signal receiver.The present invention is mainly by the restructuring of intermediate frequency data, windowing, FFT computing and phase compensation three part, it is achieved that tradition DDC down coversion and all functions of extraction, meets the requirement that multidiameter delay processes simultaneously.The number of channel depends on that FFT counts, and is theoretically obtainable arbitrarily large.Make use of the high efficiency of FFT, promote the parallel efficiency received and process multichannel Time-domain aliasing sub-channel signal.By window function, reduce interfering of interchannel, promote demodulation performance.With the every sub-channels of lasting detecting of full probability, and can not lose data.The method can obtain the highest spectral resolution, turn avoid the wave filter design of complexity, compared to tradition DDC parallel organization or optimize structure, it is to avoid wave filter design, optimizes design, the difficulty of hardware design etc. and complexity.

Description

A kind of multi-path digital down conversion method for baseband signal receiver

Technical field

The invention belongs to communication technical field, relate to a kind of multi-path digital down coversion side for baseband signal receiver Method.

Background technology

Multidiameter delay receiver is capable of large-scale parallel and launches the reception of signal and demodulation, thousands of transmitting nodes with The signal of Time-domain aliasing launched by machine, and multidiameter delay receiver needs the transmission information of all nodes of parallel demodulation.It is applicable to such as thing The application that the terminal node quantity such as networking (Internet of Things) are the hugest.

Such multidiameter delay receiver there is also some problems to be had to be solved, and one of them important problem is how Carry out multi-path parallel signal down-conversion operation efficiently.For the multiple signals of Time-domain aliasing, it is necessary first to each road is believed Number carry out down coversion respectively, obtain separating and down-sampling Hou Ge road signal.Due to the concurrency processed, it is impossible to multiplexing down coversion Module, be that each channel distributes Digital Down Convert (DDC) module.Need to consume substantial amounts of resource, along with terminal node The increase of quantity, resource problem will become the bottleneck of whole system design.

Parallel DDC module can be optimized for the knot of multiphase digital bank of filters by the conventional methods solving receiver bottleneck Structure, the mode utilizing the withdrawal device heterogeneous branching filter of connection to couple FFT again realizes, to reduce amount of calculation and resource consumption.But Need nonetheless remain for distributing an independent heterogeneous branching filter for every subchannels, for the application of big quantum channel no matter Be resource consumption or implementation complexity the most not ideal enough.

Summary of the invention

Problem to be solved by this invention is to improve in parallel duplex signal receiver, the utilization of resources of down conversion module Rate so that in the application such as such as Internet of Things, center service end can manage more terminal node with lower cost.

The technical scheme is that a kind of multi-path digital down conversion method for baseband signal receiver, its feature Being, after radio-frequency front-end sampling obtains the multichannel intermediate frequency data signal of Time-domain aliasing, receiver follows the steps below:

A. according to the form of multichannel down conversion module demand in receiver, the signal received is recombinated, particularly as follows: set Input signal is X [n], and with the sliding window segmentation of a length of N, each slip sampling point of window is D, and length of window N is by intermediate frequency Signal sampling rate fs and system subchannel interval fbin determines, N=fs/fbin, and the signal after restructuring is expressed as:

Xnew [m]=X [n+Dm], n=0,1 ... N-1；

B. the signal after restructuring is carried out windowing process；

C., signal after windowing sequentially inputs multichannel down conversion module, and described multichannel down conversion module is according to subchannel The FFT module that parameter sets；

D. phasing is carried out, to compensate the phase contrast that intermediate-freuqncy signal restructuring introduces, if i is subchannel label, every height The phase place of channel compensation is:

$\exp (-j2\mathrm{\π}\frac{i}{N}Dm)$

The each subchannels time-domain information after down coversion is obtained after correction.

Beneficial effects of the present invention is, by the restructuring of intermediate frequency data, windowing, FFT computing and phase compensation three part, real Show all functions of traditional DDC down coversion and extraction, meet the requirement that multidiameter delay processes simultaneously.The number of channel depends on FFT Count, be theoretically obtainable arbitrarily large.Make use of the high efficiency of FFT, promote parallel reception and process multichannel Time-domain aliasing The efficiency of channel signal.By window function, reduce interfering of interchannel, promote demodulation performance.Can holding with full probability The every sub-channels of continuous detecting, and do not lose data.Due to frequency spectrum resource and the factor such as Internet of Things communication data rate is low, Internet of Things should In with, subchannel often has the narrowest bandwidth, and the method can obtain the highest spectral resolution, turn avoid the filter of complexity Ripple device designs, compared to tradition DDC parallel organization or optimize structure, it is to avoid wave filter design, optimizes design, and hardware realizes The difficulty of design etc. and complexity.

Accompanying drawing explanation

Fig. 1 is multidiameter delay transmitter block diagram based on FFT；

Fig. 2 is multidiameter delay receiver block diagram based on FFT.

Detailed description of the invention

Below in conjunction with the accompanying drawings and embodiment, technical scheme is described in detail:

Embodiment

The handling process of baseband digital information, system is told about with the data receiver link of a DBPSK system for example As shown in Figure 1 and Figure 2, link includes far end radio frequency transmitter and parallel signal reception machine to block diagram.Transmitted in parallel machine comprises RF and (penetrates Frequency circuit), the Time-domain aliasing number modulated of ADC (D/A converter module), FPGA (field programmable gate array) and Matlab According to.Parallel receiver includes RF (radio circuit), is made up of ADC (D/A converter module), FPGA (field programmable gate array) Baseband board, receive circuit.

The present embodiment specific implementation process is as follows:

Transmitter sends 1000 road DBPSK modulated signals of Time-domain aliasing, and a width of 200hz of sub-channel, baud rate is 100bps, signal frame form is as shown in table 1；

Data frame format launched by table 1

Leading

Device identification

Data length

Timestamp

Ciphertext

MAC Address

Check bit

0xAA 0xF0 0x99

6bytes

5bits

19bits

0to20bytes

24bits

16bits

Parallel receiver receives 1000 road Time-domain aliasing signals of distant transmitter, and is converted to digital medium-frequency signal, in Frequency sampling rate is 409.6khz；

Parallel receiver completes data recombination, illustrates according to this patent scheme, and restructuring uses the cunning of a length of 2048 Dynamic windowed segments, each slip sampling point of window is 256；

Recombination data is carried out windowing, the present embodiment has been selected rectangular window, has then carried out FFT calculating；

FFT module completes calculating and carries out phase compensation, and it is 2048 that FFT counts；

Successively 1000 subchannels signals are carried out phase compensation；

Carry out valid frame detection, extract the useful signal on each channel；

Each channel valid frame signal is timed synchronization and frequency offset correction；

It is finally completed DBPSK demodulation, and compares the calculating bit error rate with transmitter.

Obviously, those skilled in the art should be understood that each module of the present invention or each step can be with general calculating Device realizes, and they can concentrate on single calculating device, or is distributed in the network that multiple calculating device is formed On, alternatively, they can realize with calculating the executable program code of device, such that it is able to be stored in storage dress Perform by calculating device in putting, or they are fabricated to respectively each integrated circuit modules, or multiple by them Module or step are fabricated to single integrated circuit module and realize.So, the present invention is not restricted to any specific hardware and soft Part combines.It addition, the present embodiment is only to tell from the point of view of DBPSK communication link, but it is not limited only to DBPSK receiving terminal link.It also may be used To include the various communication systems of other modulation systems.

Claims (1)

1. the multi-path digital down conversion method for baseband signal receiver, it is characterised in that comprise the following steps:

A. according to the form of multichannel down conversion module demand in receiver, the signal received is recombinated, particularly as follows: set input Signal is X [n], and with the sliding window segmentation of a length of N, each slip sampling point of window is D, and length of window N is by intermediate-freuqncy signal Sample rate f s and system subchannel interval fbin determine, N=fs/fbin, and the signal after restructuring is expressed as:

Xnew [m]=X [n+Dm], n=0,1 ... N-1；

B. the signal after restructuring is carried out windowing process；

C., signal after windowing sequentially inputs multichannel down conversion module, and described multichannel down conversion module is according to subchannel parameter The FFT module set；

D. phasing is carried out, to compensate the phase contrast that intermediate-freuqncy signal restructuring introduces, if i is subchannel label, every sub-channels The phase place compensated is:

$\exp (-j2\mathrm{\π}\frac{i}{N}Dm)$

The each subchannels time-domain information after down coversion is obtained after correction.