CN102842550B - 功率mosfet芯片的dfn封装结构 - Google Patents

功率mosfet芯片的dfn封装结构 Download PDF

Info

Publication number
CN102842550B
CN102842550B CN201210302426.3A CN201210302426A CN102842550B CN 102842550 B CN102842550 B CN 102842550B CN 201210302426 A CN201210302426 A CN 201210302426A CN 102842550 B CN102842550 B CN 102842550B
Authority
CN
China
Prior art keywords
welding disk
conductive welding
mosfet chip
weld zone
pin area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210302426.3A
Other languages
English (en)
Other versions
CN102842550A (zh
Inventor
胡乃仁
杨小平
李国发
钟利强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Good Ark Electronics Co Ltd
Original Assignee
Suzhou Good Ark Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Good Ark Electronics Co Ltd filed Critical Suzhou Good Ark Electronics Co Ltd
Priority to CN201210302426.3A priority Critical patent/CN102842550B/zh
Publication of CN102842550A publication Critical patent/CN102842550A/zh
Application granted granted Critical
Publication of CN102842550B publication Critical patent/CN102842550B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明公开一种功率MOSFET芯片的DFN封装结构，包括导电基盘、第一导电焊盘和第二导电焊盘，所述导电基盘由散热区和基盘引脚区组成，此基盘引脚区由若干个相间排列的漏极引脚组成，此漏极引脚一端与散热区端面电连接，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料层电连接；所述第一导电焊盘和第二导电焊盘位于MOSFET芯片另一侧，第一导电焊盘和第二导电焊盘均包括焊接区和引脚区，焊接区与引脚区的连接处具有一折弯部；所述软焊料层由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。本发明DFN封装结构有利于进一步缩小器件的体积，同时减少封装体中部件的数目；且提升器件MOSFET芯片散热效率，热阻相比现有技术降低75%。

Description

功率MOSFET芯片的DFN封装结构
技术领域
本发明涉及MOSFET芯片技术领域，具体涉及一种功率MOSFET芯片的DFN封装结构。
背景技术
随着电子产品的发展，例如笔记本电脑、手机、迷你CD、掌上电脑、CPU、数码照相机等消费类电子产品越来越向小型化方向发展。随着产品的做小做薄，工IC中的数百万个晶体管所产生的热量如何散发出去就变为一个不得不考虑的问题。现有技术中，虽然可以通过提升工IC制程能力来降低电压等方式来减小发热量，但是仍然不能避免发热密度增加的趋势。散热问题不解决，会使得工器件因过热而影响到产品的可靠性，严重地会缩短产品寿命甚至造成产品损毁。
现有技术，如附图1所示是一种典型的DFN封装结构的剖面示意图，包括芯片900,散热片920、引线框架930、多个导线940，以及包裹上述结构的绝缘胶950。芯片900粘附在散热片920上，引线框架930具有多个相互绝缘的管脚，芯片900表面的焊盘通过导线940连接在引线框架93。相应的管脚上。绝缘胶950将上述结构全部包裹起来，以将其同外界隔离，仅将引线框架930的各个管脚和散热片920与芯片900相对的表面暴露在空气中。引线框架930暴露出来的管脚用于实现被封装的芯片900同外界的电学连接，而散热片920暴露出来的作用在于将芯片900工作时产生的热量通过暴露的表面散发到环境中去；附图二为另一种典型的封装结构，其同样为引脚和散热片分离，且引脚外露，仍然存在体积大而不利于散热的技术问题。
发明内容
本发明目的是提供一种功率MOSFET芯片的DFN封装结构，此DFN封装结构有利于进一步缩小器件的体积，同时减少封装体中部件的数目；且提升器件MOSFET芯片散热效率，热阻相比现有技术降低75%。
为达到上述目的，本发明采用的技术方案是：一种功率MOSFET芯片的DFN封装结构，包括MOSFET芯片、环氧树脂层，所述MOSFET芯片上表面设有源极和栅极，下表面设有漏极；还包括导电基盘、第一导电焊盘和第二导电焊盘，所述导电基盘由散热区和基盘引脚区组成，此基盘引脚区由若干个相间排列的漏极引脚组成，此漏极引脚一端与散热区端面电连接，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料层电连接；所述第一导电焊盘和第二导电焊盘位于MOSFET芯片另一侧，第一导电焊盘和第二导电焊盘均包括焊接区和引脚区，焊接区与引脚区的连接处具有一折弯部，从而使得焊接区高于引脚区；若干根第一金属线跨接于所述MOSFET芯片的源极与第一导电焊盘的焊接区之间，第二金属线跨接于所述MOSFET芯片的栅极与第二导电焊盘的焊接区之间；所述软焊料层由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。
上述技术方案中进一步改进的方案如下：
1、上述方案中，所述第一导电焊盘和第二导电焊盘各自的焊接区与MOSFET芯片位于同一水平面。
2、上述方案中，所述第一金属线的数目为至少四根。
3、上述方案中，所述第一导电焊盘的引脚区由至少四根源极引脚组成。
4、上述方案中，所述第二导电焊盘的引脚区由一根栅极引脚组成。
5、上述方案中，所述漏极引脚的数目为四根。
由于上述技术方案运用，本发明与现有技术相比具有下列优点和效果：
1、本发明DFN封装结构中导电基盘，其同时兼备了现有技术中导电焊盘、散热片和基岛三个部件功能，既有利于进一步缩小器件的体积，也减少器件中部件的数目，同时由于散热区和基盘引脚区为一个整体，提高了电性能的稳定性。
2、本发明DFN封装结构中导电基盘，其同时兼备了现有技术中导电焊盘、散热片和基岛三个部件功能，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料层电连接且所述软焊料层由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%，进一步提高了导电基盘的散热性能。
3、本发明DFN封装结构中焊接区与引脚区的连接处具有一折弯部，从而使得焊接区高于引脚区，并保证了第一、第二导电焊盘的焊接区与MOSFET芯片的栅极在同一水平面，从而有效避免了由于连接栅极的第二金属线较细在使用中容易断的技术缺陷，从而延长了产品的使用寿命并提高了可靠性。
4、本发明DFN封装结构中基盘引脚区由若干个相间排列的漏极引脚组成，第一导电焊盘的引脚区由至少四根源极引脚组成，充分考虑到MOSFET芯片漏极和源极相对栅极电流大的差异，从而有利于减少热量的产生，并进一步提高了电性能指标。
附图说明
图1为现有技术结构示意图一；
图2为现有技术结构示意图二；
图3为本发明功率MOSFET芯片的DFN封装结构示意图；
图4为附图3中沿A-A线的剖视图。
以上附图中：1、MOSFET芯片；2、环氧树脂层；3、导电基盘；31、散热区；32、基盘引脚区；321、漏极引脚；4、第一导电焊盘；5、第二导电焊盘；6、软焊料层；7、焊接区；8、引脚区；9、折弯部；10、第一金属线；11、第二金属线。
具体实施方式
下面结合实施例对本发明作进一步描述：
实施例1：一种功率MOSFET芯片的DFN封装结构，包括MOSFET芯片1、环氧树脂层2，所述MOSFET芯片上表面1设有源极和栅极，下表面设有漏极，还包括导电基盘3、第一导电焊盘4和第二导电焊盘5，所述导电基盘3由散热区31和基盘引脚区32组成，此基盘引脚区32由若干个相间排列的漏极引脚321组成，此漏极引脚321一端与散热区31端面电连接，所述散热区31位于MOSFET芯片1正下方且与MOSFET芯片1下表面之间通过软焊料层6电连接；所述第一导电焊盘4和第二导电焊盘5位于MOSFET芯片1另一侧，第一导电焊盘4和第二导电焊盘5均包括焊接区7和引脚区8，焊接区7与引脚区8的连接处具有一折弯部9，从而使得焊接区7高于引脚区8；若干根第一金属线10跨接于所述MOSFET芯片1的源极与第一导电焊盘4的焊接区7之间，第二金属线11跨接于所述MOSFET芯片1的栅极与第二导电焊盘5的焊接区7之间；所述软焊料层6由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。
上述第一导电焊盘4和第二导电焊盘5各自的焊接区7与MOSFET芯片位于同一水平面。
实施例2：一种功率MOSFET芯片的DFN封装结构，包括MOSFET芯片1、环氧树脂层2，所述MOSFET芯片上表面1设有源极和栅极，下表面设有漏极，还包括导电基盘3、第一导电焊盘4和第二导电焊盘5，所述导电基盘3由散热区31和基盘引脚区32组成，此基盘引脚区32由若干个相间排列的漏极引脚321组成，此漏极引脚321一端与散热区31端面电连接，所述散热区31位于MOSFET芯片1正下方且与MOSFET芯片1下表面之间通过软焊料层6电连接；所述第一导电焊盘7和第二导电焊盘8位于MOSFET芯片1另一侧，第一导电焊盘4和第二导电焊盘5均包括焊接区7和引脚区8，焊接区7与引脚区8的连接处具有一折弯部9，从而使得焊接区7高于引脚区8；若干根第一金属线10跨接于所述MOSFET芯片1的源极与第一导电焊盘4的焊接区7之间，第二金属线11跨接于所述MOSFET芯片1的栅极与第二导电焊盘5的焊接区7之间；所述软焊料层6由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。
上述第一金属线10的数目为至少四根。
上述第一导电焊盘4的引脚区由至少四根源极引脚组成。
上述第二导电焊盘5的引脚区由一根栅极引脚组成。
上述漏极引脚321的数目为四根。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (5)

1.一种功率MOSFET芯片的DFN封装结构，包括MOSFET芯片（1）、环氧树脂层（2），所述MOSFET芯片上表面（1）设有源极和栅极，下表面设有漏极，其特征在于：还包括导电基盘（3）、第一导电焊盘（4）和第二导电焊盘（5），所述导电基盘（3）由散热区（31）和基盘引脚区（32）组成，此基盘引脚区（32）由若干个相间排列的漏极引脚（321）组成，此漏极引脚（321）一端与散热区（31）端面电连接，所述散热区（31）位于MOSFET芯片（1）正下方且与MOSFET芯片（1）下表面之间通过软焊料层（6）电连接；所述第一导电焊盘（4）和第二导电焊盘（5）位于MOSFET芯片（1）另一侧，第一导电焊盘（4）和第二导电焊盘（5）均包括焊接区（7）和引脚区（8），焊接区（7）与引脚区（8）的连接处具有一折弯部（9），从而使得焊接区（7）高于引脚区（8）；若干根第一金属线（10）跨接于所述MOSFET芯片（1）的源极与第一导电焊盘（4）的焊接区（7）之间，第二金属线（11）跨接于所述MOSFET芯片（1）的栅极与第二导电焊盘（5）的焊接区（7）之间；所述软焊料层（6）由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%；所述第一导电焊盘（4）和第二导电焊盘（5）各自的焊接区（7）与MOSFET芯片位于同一水平面。
2.根据权利要求1所述的DFN封装结构，其特征在于：所述第一金属线（10）的数目为至少四根。
3.根据权利要求1所述的DFN封装结构，其特征在于：所述第一导电焊盘（4）的引脚区由至少四根源极引脚组成。
4.根据权利要求1所述的DFN封装结构，其特征在于：所述第二导电焊盘（5）的引脚区由一根栅极引脚组成。
5.根据权利要求1所述的DFN封装结构，其特征在于：所述漏极引脚（321）的数目为四根。
CN201210302426.3A 2012-08-23 2012-08-23 功率mosfet芯片的dfn封装结构 Active CN102842550B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210302426.3A CN102842550B (zh) 2012-08-23 2012-08-23 功率mosfet芯片的dfn封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210302426.3A CN102842550B (zh) 2012-08-23 2012-08-23 功率mosfet芯片的dfn封装结构

Publications (2)

Publication Number Publication Date
CN102842550A CN102842550A (zh) 2012-12-26
CN102842550B true CN102842550B (zh) 2015-12-16

Family

ID=47369771

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210302426.3A Active CN102842550B (zh) 2012-08-23 2012-08-23 功率mosfet芯片的dfn封装结构

Country Status (1)

Country Link
CN (1) CN102842550B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108598179B (zh) * 2015-01-19 2023-01-31 苏州固锝电子股份有限公司 电子产品用大电流整流芯片
CN109727943A (zh) * 2019-02-27 2019-05-07 无锡新洁能股份有限公司 一种具有低热阻的半导体器件封装结构及其制造方法
CN110556366A (zh) * 2019-09-28 2019-12-10 华南理工大学 一种GaN基级联型功率器件及其制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101512759A (zh) * 2005-06-10 2009-08-19 万国半导体股份有限公司 可降低电阻的双向无引脚半导体封装结构

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768105B2 (en) * 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101512759A (zh) * 2005-06-10 2009-08-19 万国半导体股份有限公司 可降低电阻的双向无引脚半导体封装结构

Also Published As

Publication number Publication date
CN102842550A (zh) 2012-12-26

Similar Documents

Publication Publication Date Title
JP2006512778A (ja) 横方向伝導装置用の空間効率パッケージ
CN102983114B (zh) 具有超薄封装的高性能功率晶体管
CN112018049B (zh) 一种芯片封装结构及一种电子设备
CN102842550B (zh) 功率mosfet芯片的dfn封装结构
CN102842549B (zh) 四方扁平无引脚的功率mosfet封装体
CN201946588U (zh) 一种功率半导体器件的封装结构
CN102339811A (zh) 具有cob封装功率器件的电路板
CN203118935U (zh) 整流芯片的dfn封装结构
CN203118939U (zh) 四方扁平型功率器件封装体
CN201689898U (zh) 聚光型太阳能电池的封装结构
CN203118936U (zh) 整流半导体芯片封装结构
CN203277352U (zh) 高导热型功率整流半导体器件
CN202796930U (zh) 用于mosfet芯片的封装体
CN202796917U (zh) 无引脚的功率mosfet器件
CN209104141U (zh) 一种芯片外露型封装结构
CN209515657U (zh) 一种封装结构
CN102842548A (zh) 四方扁平型功率mos芯片封装结构
CN218585975U (zh) 一种半导体封装结构
CN204558445U (zh) 半导体封装结构
CN202796931U (zh) 功率mosfet的器件结构
CN206789535U (zh) 一种电力电子器件的扇出型封装结构
CN202796918U (zh) 四方扁平无引脚的mos封装结构
CN206877981U (zh) 超结金属栅场效应晶体管封装结构
CN202796919U (zh) 无引脚mosfet封装结构
CN103219315A (zh) 肖特基整流芯片封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant