CN102842549B - 四方扁平无引脚的功率mosfet封装体 - Google Patents

四方扁平无引脚的功率mosfet封装体 Download PDF

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CN102842549B
CN102842549B CN201210302402.8A CN201210302402A CN102842549B CN 102842549 B CN102842549 B CN 102842549B CN 201210302402 A CN201210302402 A CN 201210302402A CN 102842549 B CN102842549 B CN 102842549B
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welding disk
conductive welding
mosfet chip
weld zone
pin
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CN102842549A (zh
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胡乃仁
杨小平
李国发
钟利强
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Suzhou Good Ark Electronics Co Ltd
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Abstract

本发明公开一种四方扁平无引脚的功率MOSFET封装体，其导电基盘由散热区和基盘引脚区组成，此基盘引脚区由若干个相间排列的漏极引脚组成，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料层电连接；所述第一导电焊盘和第二导电焊盘位于MOSFET芯片另一侧，第一导电焊盘和第二导电焊盘均包括焊接区和引脚区，焊接区与引脚区的连接处具有一折弯部；一铝导体带跨接于所述MOSFET芯片的源极与第一导电焊盘的焊接区之间，所述铝导体带与MOSFET芯片的源极的焊接条至少为2条且相间排列；所述软焊料层由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。本发明功率MOSFET封装体有利于减少欧姆接触电阻，提高了电性能指标，同时也减少热量的产生。

Description

四方扁平无引脚的功率MOSFET封装体
技术领域
本发明涉及MOSFET芯片技术领域，具体涉及一种四方扁平无引脚的功率MOSFET封装体。
背景技术
随着电子制造技术的快速发展，消费电子产品越来越向小型、便携的趋势发展，这也导致了这些电子产品的内部能够用于布置电学元件的空间变得越来越有限。在此情况下，采用的电学元件势必越薄越好，这也成为了目前电子元件制造也的发展趋势。四方扁平无引脚封装(DFN)工艺恰好可以满足这一需求。
附图1所示是现有技术中一种典型的DFN封装结构的剖面示意图，包括芯片900,散热片920、引线框架930、多个导线940，以及包裹上述结构的绝缘胶950。芯片900粘附在散热片920上，引线框架930具有多个相互绝缘的管脚，芯片900表面的焊盘通过导线940连接在引线框架93。相应的管脚上。绝缘胶950将上述结构全部包裹起来，以将其同外界隔离，仅将引线框架930的各个管脚和散热片920与芯片900相对的表面暴露在空气中。引线框架930暴露出来的管脚用于实现被封装的芯片900同外界的电学连接，而散热片920暴露出来的作用在于将芯片900工作时产生的热量通过暴露的表面散发到环境中去。
发明内容
本发明目的是提供一种四方扁平无引脚的功率MOSFET封装体，此功率MOSFET封装体有利于减少欧姆接触电阻，提高了电性能指标，同时也减少热量的产生。
为达到上述目的，本发明采用的技术方案是：一种四方扁平无引脚的功率MOSFET封装体，包括MOSFET芯片、环氧树脂层，所述MOSFET芯片上表面设有源极和栅极，下表面设有漏极，其特征在于：还包括导电基盘、第一导电焊盘和第二导电焊盘，所述导电基盘由散热区和基盘引脚区组成，此基盘引脚区由若干个相间排列的漏极引脚组成，此漏极引脚一端与散热区端面电连接，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料层电连接；所述第一导电焊盘和第二导电焊盘位于MOSFET芯片另一侧，第一导电焊盘和第二导电焊盘均包括焊接区和引脚区，焊接区与引脚区的连接处具有一折弯部，从而使得焊接区高于引脚区；一铝导体带跨接于所述MOSFET芯片的源极与第一导电焊盘的焊接区之间，所述铝导体带与MOSFET芯片的源极的焊接条至少为2条且相间排列；一金属线跨接于所述MOSFET芯片的栅极与第二导电焊盘的焊接区之间；所述软焊料层由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。
上述技术方案中进一步改进的方案如下：
1、上述方案中，所述第一导电焊盘和第二导电焊盘各自的焊接区与MOSFET芯片位于同一水平面。
2、上述方案中，所述铝导体带宽厚比为1：10?15。
3、上述方案中，所述至少2条焊接条的排列方式为平行设置。
4、上述方案中，所述第一导电焊盘的引脚区由至少四根源极引脚组
成。
5、上述方案中，所述第二导电焊盘的引脚区由一根栅极引脚组成。
6、上述方案中，所述漏极引脚的数目为四根。
由于上述技术方案运用，本发明与现有技术相比具有下列优点和效果：
1、本发明封装体中导电基盘，其同时兼备了现有技术中导电焊盘、散热片和基岛三个部件功能，既有利于进一步缩小器件的体积，也减少器件中部件的数目，同时由于散热区和基盘引脚区为一个整体，提高了电性能的稳定性。
2、本发明封装体中导电基盘，其同时兼备了现有技术中导电焊盘、散热片和基岛三个部件功能，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料层电连接且所述软焊料层由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%，进一步提高了导电基盘的散热性能。
3、本发明封装体中焊接区与引脚区的连接处具有一折弯部，从而使得焊接区高于引脚区，并保证了第一、第二导电焊盘的焊接区与MOSFET芯片的栅极在同一水平面，从而有效避免了由于连接栅极的第二金属线较细在使用中容易断的技术缺陷，从而延长了产品的使用寿命并提高了可靠性。
4、本发明此基盘引脚区由若干个相间排列的漏极引脚组成，第一导电焊盘的引脚区由至少四根源极引脚组成，充分考虑到MOSFET芯片漏极和源极相对栅极电流大的差异，从而有利于减少热量的产生，并进一步提高了电性能指标。
5、本发明所述MOSFET芯片的源极与第一导电焊盘的焊接区之间跨接有铝导体带，且所述铝导体带与MOSFET芯片的源极的焊接条至少为2条且相间排列，这种结构设计从而有利于减少欧姆接触电阻，提高了电性能指标，同时也减少热量的产生。
附图说明
图1为现有技术结构示意图；
图2为本发明功率MOSFET封装体结构示意图；
图3为附图2中沿A-A线的剖视图。
以上附图中：1、MOSFET芯片；2、环氧树脂层；3、导电基盘；31、散热区；32、基盘引脚区；321、漏极引脚；4、第一导电焊盘；5、第二导电焊盘；6、软焊料层；7、焊接区；8、引脚区；9、折弯部；10、铝导体带；11、金属线；12、焊接条。
具体实施方式
下面结合实施例对本发明作进一步描述：
实施例1：一种四方扁平无引脚的功率MOSFET封装体，包括MOSFET芯片1、环氧树脂层2，所述MOSFET芯片上表面1设有源极和栅极，下表面设有漏极，还包括导电基盘3、第一导电焊盘4和第二导电焊盘5，所述导电基盘3由散热区31和基盘引脚区32组成，此基盘引脚区32由若干个相间排列的漏极引脚321组成，此漏极引脚321一端与散热区31端面电连接，所述散热区31位于MOSFET芯片1正下方且与MOSFET芯片1下表面之间通过软焊料层6电连接；所述第一导电焊盘4和第二导电焊盘5位于MOSFET芯片1另一侧，第一导电焊盘4和第二导电焊盘5均包括焊接区7和引脚区8，焊接区7与引脚区8的连接处具有一折弯部9，从而使得焊接区7高于引脚区8；一铝导体带10跨接于所述MOSFET芯片1的源极与第一导电焊盘4的焊接区7之间，所述铝导体带10与MOSFET芯片1的源极的焊接条12至少为2条且相间排列；一金属线11跨接于所述MOSFET芯片1的栅极与第二导电焊盘5的焊接区7之间；所述软焊料层6由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。
上述第一导电焊盘4和第二导电焊盘5各自的焊接区7与MOSFET芯片位于同一水平面。
上述漏极引脚321的数目为四根。
实施例2：一种四方扁平无引脚的功率MOSFET封装体，包括MOSFET芯片1、环氧树脂层2，所述MOSFET芯片上表面1设有源极和栅极，下表面设有漏极，还包括导电基盘3、第一导电焊盘4和第二导电焊盘5，所述导电基盘3由散热区31和基盘引脚区32组成，此基盘引脚区32由若干个相间排列的漏极引脚321组成，此漏极引脚321一端与散热区31端面电连接，所述散热区31位于MOSFET芯片1正下方且与MOSFET芯片1下表面之间通过软焊料层6电连接；所述第一导电焊盘4和第二导电焊盘5位于MOSFET芯片1另一侧，第一导电焊盘4和第二导电焊盘5均包括焊接区7和引脚区8，焊接区7与引脚区8的连接处具有一折弯部9，从而使得焊接区7高于引脚区8；一铝导体带10跨接于所述MOSFET芯片1的源极与第一导电焊盘4的焊接区7之间，所述铝导体带10与MOSFET芯片1的源极的焊接条12至少为2条且相间排列；一金属线11跨接于所述MOSFET芯片1的栅极与第二导电焊盘5的焊接区7之间；所述软焊料层6由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%。
上述铝导体带10宽厚比为1：10?15。
上述至少2条焊接条12的排列方式为平行设置。上述第一导电焊盘4的引脚区由至少四根源极引脚组成。
上述第二导电焊盘5的引脚区由一根栅极引脚组成。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (5)

1.一种四方扁平无引脚的功率MOSFET封装体，包括MOSFET芯片（1）、环氧树脂层（2），所述MOSFET芯片上表面（1）设有源极和栅极，下表面设有漏极，其特征在于：还包括导电基盘（3）、第一导电焊盘（4）和第二导电焊盘（5），所述导电基盘（3）由散热区（31）和基盘引脚区（32）组成，此基盘引脚区（32）由若干个相间排列的漏极引脚（321）组成，此漏极引脚（321）一端与散热区（31）端面电连接，所述散热区（31）位于MOSFET芯片（1）正下方且与MOSFET芯片（1）下表面之间通过软焊料层（6）电连接；所述第一导电焊盘（4）和第二导电焊盘（5）位于MOSFET芯片（1）另一侧，第一导电焊盘（4）和第二导电焊盘（5）均包括焊接区（7）和引脚区（8），焊接区（7）与引脚区（8）的连接处具有一折弯部（9），从而使得焊接区（7）高于引脚区（8）；一铝导体带（10）跨接于所述MOSFET芯片（1）的源极与第一导电焊盘（4）的焊接区（7）之间，所述铝导体带（10）与MOSFET芯片（1）的源极的焊接条（12）至少为2条且相间排列；一金属线（11）跨接于所述MOSFET芯片（1）的栅极与第二导电焊盘（5）的焊接区（7）之间；所述软焊料层（6）由以下质量百分含量的组分组成：铅92.5%，锡5%，银2.5%；
所述第一导电焊盘（4）和第二导电焊盘（5）各自的焊接区（7）与MOSFET芯片位于同一水平面；所述铝导体带（10）宽厚比为1：10~15。
2.根据权利要求1所述的功率MOSFET封装体，其特征在于：所述至少2条焊接条（12）的排列方式为平行设置。
3.根据权利要求1所述的功率MOSFET封装体，其特征在于：所述第一导电焊盘（4）的引脚区由至少四根源极引脚组成。
4.根据权利要求1所述的功率MOSFET封装体，其特征在于：所述第二导电焊盘（5）的引脚区由一根栅极引脚组成。
5.根据权利要求1所述的功率MOSFET封装体，其特征在于：所述漏极引脚（321）的数目为四根。
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