CN209104141U - 一种芯片外露型封装结构 - Google Patents

一种芯片外露型封装结构 Download PDF

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CN209104141U
CN209104141U CN201821685407.2U CN201821685407U CN209104141U CN 209104141 U CN209104141 U CN 209104141U CN 201821685407 U CN201821685407 U CN 201821685407U CN 209104141 U CN209104141 U CN 209104141U
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chip
wiring board
encapsulating structure
exposed type
type encapsulating
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陈建华
陆鸿兴
赵亮
游志文
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Siliconware Technology SuZhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本实用新型揭示了一种芯片外露型封装结构，该封装结构包括芯片、金属凸块和线路板，所述芯片的下方设置有线路板，芯片与线路板之间均通过金属凸块进行信号互连，芯片与线路板之间均通过粘结物质实现固接，芯片的四周与线路板之间均通过塑封体进行填充塑封，芯片有且仅有一面为用于与散热片接触的裸露面。所述线路板为单层线路板或多层线路板。本方案解决了目前IC集尘电路散热性能不佳的问题。该结构散热能力强，环氧树脂半包裹IC硅芯片，芯片表面露出树脂，终端应用贴散热片于胶体表面，散热片与硅芯片直接接触，通过硅芯片自身导热，散热性能佳，可降低器件功耗，降低生产成本。

Description

一种芯片外露型封装结构
技术领域
本实用新型涉及一种芯片外露型封装结构，可用于半导体封装技术领域。
背景技术
传统的芯片封装形式的散热方式主要采用包覆芯片与线路板之间的塑封体为散热传导工具或途径，而这种传统封装方式的散热传导不足点在于：
1、通过塑封体吸收芯片热量再传导至外界，散热效果差。
2、对于塑封体本身的材质具有较高的要求，需要添加金属氧化物提升散热能力，成本高，且环氧树脂包裹整颗IC硅芯片，终端应用贴散热片于胶体表面，散热片与树脂接触，因树脂导热系数较硅材差，此设计散热性能差。
实用新型内容
本实用新型的目的就是为了解决现有技术中存在的上述问题，提出一种芯片外露型封装结构。
本实用新型的目的将通过以下技术方案得以实现：一种芯片外露型封装结构，包括芯片、金属凸块和线路板，所述芯片的下方设置有线路板，芯片与线路板之间均通过金属凸块进行信号互连，芯片与线路板之间均通过粘结物质实现固接，芯片的四周与线路板之间均通过塑封体进行填充塑封，芯片有且仅有一面为用于与散热片接触的裸露面。
优选地，所述线路板为单层线路板或多层线路板。
优选地，所述芯片为单层线路板时，芯片与单层线路板的最上层接触。
优选地，所述芯片为多层线路板时，芯片与多层线路板的最上层线路板接触。
优选地，所述单层线路板为单层树脂线路板，多层线路板为多层树脂线路板。
优选地，所述粘结物质为不导电的导热粘接物质。
优选地，所述金属凸块为柱状结构。
优选地，所述金属凸块的材质为锡、金或合金。
优选地，所述塑封体为环氧树脂。
本实用新型技术方案的优点主要体现在：本方案解决了目前IC集尘电路散热性能不佳的问题。该结构散热能力强，环氧树脂半包裹IC硅芯片，芯片表面露出树脂，终端应用贴散热片于胶体表面，散热片与硅芯片直接接触，通过硅芯片自身导热，散热性能佳。
通过芯片外露面将芯片自身热能快速传导到封装体外界，散热能力强，可以应用在一般的封装体及封装工艺使其成为高散热IC，如BGA可以成为ED-BGA,LGA可以成为ED-LGA, QFN可以成为ED-QFN,FPS可以成为ED-FPS……，通过快速散热途径降低原件功耗，降低生产成本。
附图说明
图1为本实用新型的一种芯片外露型封装结构的示意图。
图2为图1的俯视图。
图中附图标记：1---芯片，2---金属凸块，3---树脂线路板，4---塑封体，5---粘结物质。
具体实施方式
本实用新型的目的、优点和特点，将通过下面优选实施例的非限制性说明进行图示和解释。这些实施例仅是应用本实用新型技术方案的典型范例，凡采取等同替换或者等效变换而形成的技术方案，均落在本实用新型要求保护的范围之内。
本实用新型揭示了一种芯片外露型封装结构，如图1和图2所示，该芯片外露型封装结构包括芯片1、金属凸块2和线路板3，所述芯片的下方设置有线路板3，所述线路板3为单层线路板或多层线路板，具体地，所述芯片为单层线路板时，芯片与单层线路板的最上层接触。所述芯片为多层线路板时，芯片与多层线路板的最上层线路板接触。所述单层线路板为单层树脂线路板，多层线路板为多层树脂线路板。
在本技术方案中，所述芯片的下方优选地设置有一层线路板3，所述线路板3为单层树脂线路板，本技术方案中，不对所述线路板的材质做具体地限定。
芯片与线路板之间均通过金属凸块进行信号互连，芯片与线路板之间均通过粘结物质5实现固接，所述粘结物质为不导电的导热粘接物质。所述金属凸块2为柱状结构，所述金属凸块2的材质为锡、金或合金。该金属凸块能够适应高密度封装，并且具有较好的应力特征，能够提高封装的电学稳定性和力学稳定性。
芯片的四周与线路板之间均通过塑封体进行填充塑封，所述塑封体为环氧树脂。芯片有且仅有一面为用于与散热片接触的裸露面，即芯片上方无塑封体包裹，通过芯片外露面将热能快速传导到封装体外界，不需要使用高散热性能塑封体材料。
该方法解决了目前IC集尘电路散热性能不佳的问题。环氧树脂半包裹IC 硅芯片，芯片表面露出树脂，终端应用贴散热片于胶体表面，散热片与硅芯片直接接触，通过硅芯片自身导热，此设计散热性能佳。
本实用新型尚有多种实施方式，凡采用等同变换或者等效变换而形成的所有技术方案，均落在本实用新型的保护范围之内。

Claims (9)

1.一种芯片外露型封装结构，其特征在于：包括芯片、金属凸块和线路板，所述芯片的下方设置有线路板，芯片与线路板之间均通过金属凸块进行信号互连，芯片与线路板之间均通过粘结物质实现固接，芯片的四周与线路板之间均通过塑封体进行填充塑封，芯片有且仅有一面为用于与散热片接触的裸露面。
2.根据权利要求1所述的一种芯片外露型封装结构，其特征在于：所述线路板为单层线路板或多层线路板。
3.根据权利要求2所述的一种芯片外露型封装结构，其特征在于：所述芯片为单层线路板时，芯片与单层线路板的最上层接触。
4.根据权利要求2所述的一种芯片外露型封装结构，其特征在于：所述芯片为多层线路板时，芯片与多层线路板的最上层线路板接触。
5.根据权利要求2所述的一种芯片外露型封 装结构，其特征在于：所述单层线路板为单层树脂线路板，多层线路板为多层树脂线路板。
6.根据权利要求1所述的一种芯片外露型封装结构，其特征在于：所述粘结物质为不导电的导热粘结物质。
7.根据权利要求1所述的一种芯片外露型封装结构，其特征在于：所述金属凸块为柱状或球状结构。
8.根据权利要求1所述的一种芯片外露型封装结构，其特征在于：所述金属凸块的材质为锡、金或合金。
9.根据权利要求1所述的一种芯片外露型封装结构，其特征在于：所述塑封体为环氧树脂。
CN201821685407.2U 2018-10-17 2018-10-17 一种芯片外露型封装结构 Active CN209104141U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128994A (zh) * 2019-12-27 2020-05-08 华为技术有限公司 一种***级封装结构及其封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128994A (zh) * 2019-12-27 2020-05-08 华为技术有限公司 一种***级封装结构及其封装方法

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