CN102707083B - Motor speed calculating method - Google Patents
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- CN102707083B CN102707083B CN 201210224259 CN201210224259A CN102707083B CN 102707083 B CN102707083 B CN 102707083B CN 201210224259 CN201210224259 CN 201210224259 CN 201210224259 A CN201210224259 A CN 201210224259A CN 102707083 B CN102707083 B CN 102707083B
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Abstract
The invention discloses a motor speed calculating method, which carries out low-pass filter treatment on pulse input A and pulse input B. Each one of the filtered pulse input A and pulse input B is output in two paths for pulse selection and direction judgment. In the direction judgment, a current speed direction is judged according to a phase difference of the pulse input A and the pulse input B, and a direction signal is output. In the pulse selection, one pulse suitable for calculation is selected from the pulse input A and the pulse input B and is output by dividing into three paths for frequency calculation, zero-speed judgment and duty ratio calculation. In the zero-speed judgment, a zero-speed identifier is output when a current speed sensor has no output pulse. In the frequency calculation, a pulse frequency is processed, calculated and output. In the duty ratio calculation, a duty ratio signal under the current pulse is processed, calculated and output.. With the adoption of the motor speed calculating method provided by the invention, the technical problems that the motor speed calculating method in the prior art has low instantaneity, accuracy and stability, and is not suitable for multipath input signal treatment and parallel calculation function can be solved.
Description
Technical field
The present invention relates to a kind of control method of motor, especially relate to a kind of speed calculation method of multifunctional modular motor.
Background technology
The speed pickup of main flow all is pulsed at present, namely characterizes current velocity of rotation and direction with a set of pulses, and the user need calculate frequency and the phase relation of pulse, to draw actual speed and direction.For present most controllers, rate signal is important key parameter, as long as there be the inaccurate of short time will cause significant trouble.And in actual application, rate signal often is subject to disturb, and polytrope is arranged, and this just requires its acquiring and processing method must possess real-time, accuracy, stability and anti-interference.
Existing computing method are to use the pulse capture module of processor to receive signal, and calculate cycle of pulse by the form of interrupting, and are aided with processing means such as filtering, calculating again and finally draw velocity amplitude, do not possess direction determining and dutycycle computing function.Because prior art uses processor and software language to realize, the stable and real-time of calculating will lean on the optimization degree of performance of processors and software language to guarantee, has risk.Because prior art uses the interrupt mode of processor to calculate, and when pulsed frequency is higher, can makes processor respond interruption frequently, thereby take a large amount of processor resources, even make it at a standstill.Because prior art uses the capture module of processor to carry out the reception of pulse, so be subject to the hardware resource of processor itself, when the input pulse number more for a long time, system will need the cooperation of multi-disc processor just can finish the reception of all input pulses, this has increased cost on the one hand greatly, also makes the synchronism of these speed sampling values be subjected to loss on the other hand.Simultaneously, prior art does not also possess the velocity reversal decision-making function, does not possess the zero-speed decision-making function, does not possess the pulse duty factor computing function.
Summary of the invention
The purpose of this invention is to provide a kind of motor speed computing method, real-time, accuracy and stability that this method has solved the prior art existence are not high, are not suitable for the technical matters of the processing of multichannel input signal and concurrent operation function.
In order to realize the foregoing invention purpose, the present invention specifically provides a kind of technic relization scheme of motor speed computing method, and this method specifically may further comprise the steps:
S10: will carry out low-pass filtering treatment from one group of speed pulse signal pulse input A and the pulse input B of the speed pickup of motor output;
S11: will export through pulse input A and pulse input B each minute two-way that filtering is handled, wherein one road treated pulse input A and pulse input B carry out the pulse choice processing, other one road treated pulse input A and pulse input B travel direction determination processing;
S12: when treated pulse input A and pulse input B travel direction determination processing, judge current velocity reversal according to the phase differential of pulse input A and pulse input B, and direction signal is exported; When treated pulse input A and pulse input B carry out the pulse choice processing, selecting a pulse input signal that is fit to calculate from pulse input A and two pulses of pulse input B divides three the tunnel to export respectively, one road pulse input signal carries out frequency computation part to be handled, one road pulse input signal carries out the zero-speed determination processing, and one road pulse input signal carries out the dutycycle computing;
S13: one road pulse input signal carries out the zero-speed determination processing, when judging current speed pickup no-output pulse, and output zero-speed id signal; When one road pulse input signal carries out the frequency computation part processing, calculate and the output pulse frequency signal; When one road pulse input signal carries out the dutycycle computing, calculate and export current duty of ratio signal.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, the motor speed computing method are moved based on FPGA, and pulse input A and pulse input B are from the IO pin input of described FPGA, and low-pass filtering treatment is carried out in the inside of FPGA.
Further improvement as a kind of motor speed computing method of the present invention technical scheme, pulse input A and pulse input B through low-pass filtering treatment carry out the pulse choice processing, the pulse choice processing is selected a pulse input signal that is fit to calculate according to following rule and is divided three tunnel outputs, carries out frequency computation part processing, zero-speed determination processing and dutycycle computing respectively:
When pulse input A and pulse input B exist simultaneously, output pulse input A;
A is normal when the pulse input, when pulse input B loses, and output pulse input A;
B is normal when the pulse input, when pulse input A loses, and output pulse input B.
Further improvement as a kind of motor speed computing method of the present invention technical scheme, when treated pulse input A and pulse input B travel direction determination processing, the process of judging current velocity reversal according to the phase differential of pulse input A and pulse input B further may further comprise the steps:
S121: judge at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to; If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to;
S122: the high level time that calculates composite pulse output, and the cycle of calculating pulse input A, the high level time that the cycle that A is imported in pulse dwindles after half with composite pulse output again compares, if half high level time less than composite pulse output in pulse input A cycle, illustrate that then the dutycycle of composite pulse output greater than 50%, then exports the A turn signal; If half high level time greater than composite pulse output in pulse input A cycle is then exported the B turn signal.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, from pulse input A and two pulses of pulse input B, select a pulse input signal that is fit to calculate and carry out the process that frequency computation part handles and further may further comprise the steps:
S131: after the rising edge of pulse input signal arrives, at first count, will latch as the cycle of this subpulse through the clocking value that counts to get, and the cycle of a last pulse is latched;
S132: when next pulse input signal is imported, restart counting, carry out timing next time; The periodic quantity of the periodic quantity of this subpulse and a last pulse is subtracted each other and is compared, if fiducial value greater than a default maximum period of change limit value, then Shu Chu recurrence interval value signal Period is the periodic quantity of a last pulse; If fiducial value is less than a default maximum period of change limit value, Shu Chu the recurrence interval value signal Period periodic quantity of subpulse for this reason then;
S133: recurrence interval value signal Period and computation period preset value compare, and, then the recurrence interval value signal of input is sued for peace less than the computation period preset value as if the recurrence interval value signal, and pulse number signal Num is carried out from adding 1 operation;
S134: when the recurrence interval value signal summing value of input during greater than the computation period preset value, the signal of computation period signal Time for the recurrence interval value signal of input is sued for peace, divide operations is carried out in pulse number signal Num and computation period signal Time output, and will carry out the result of sum operation and pulse number signal Num to the recurrence interval value signal of input from all zero clearings of result of add operation;
S135: if the recurrence interval value signal is during greater than the computation period preset value, then pulse number signal Num is 1, computation period signal Time is current pulse-period signal, and pulse number signal Num and computation period signal Time output carried out divide operations, and with computation period signal Time and all zero clearings of pulse number signal Num;
S136: divide operations result's output signal is carried out filtering and is handled back output pulse frequency signal.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, from pulse input A and two pulses of pulse input B, select the process that a pulse input signal that is fit to calculate carries out the zero-speed determination processing and further may further comprise the steps:
The rising edge of paired pulses input signal catches and carries out timing and operate, timing operation output signal compares with the maximum impulse periodic signal of presetting, if do not receive the rising edge of pulse input signal in the cycle in maximum impulse, namely think the no pulse input, and the speed of judging this moment is zero, the output of present speed sensor no pulse, and output zero-speed sign.
As the further improvement of a kind of motor speed computing method of the present invention technical scheme, from pulse input A and two pulses of pulse input B, select the process that a pulse input signal that is fit to calculate carries out the dutycycle computing and further may further comprise the steps:
Calculate the high level time of pulse according to the pulse input signal of input, according to the cycle of the pulse input signal calculating pulse of importing, pulse high level time signal and pulse-period signal are carried out division arithmetic, obtain the dutycycle of pulse input signal.
By implementing the technical scheme of a kind of motor speed computing method of the invention described above, have following technique effect:
(1) the present invention can handle the pulsed rate signal processing that reaches tens of ways simultaneously, and the pulsed frequency wide ranges that receives, and the velocity amplitude error of output is minimum;
(2) the accessible input pulse frequency range of the present invention is 0.1 ~ 500KHz, can satisfy most engineering demands, possesses higher applicability;
(3) the present invention can simultaneously treated input pulse quantity be 1 ~ 16 the tunnel, and expands under the condition that hardware can be supported, possesses higher practicality and cost performance;
(4) the velocity amplitude error of the present invention's output is very little, and the measurement error when the input pulse frequency is 10KHz is 0.005%, possesses high accuracy and resolution;
(5) the present invention possesses the velocity reversal decision-making function;
(6) the present invention possesses the zero-speed decision-making function;
(7) the present invention possesses the pulse duty factor computing function;
(8) the present invention is integrated in functions such as rate signal filtering, velocity amplitude calculating, the judgement of speed zero-speed, velocity reversal judgement, pulse duty factor calculating on the FPGA with hardware description language is modular, can effectively utilize the FPGA aboundresources, ability with high speed processing, concurrent operation, modular design possesses higher stability, confidentiality and integrated level simultaneously.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the system architecture diagram of a kind of embodiment of the applied motor speed calculation element of motor speed computing method of the present invention.
Fig. 2 is the working timing figure of a kind of embodiment low-pass filtering module of the applied motor speed calculation element of motor speed computing method of the present invention.
Fig. 3 is the working timing figure of a kind of embodiment direction determining of the applied motor speed calculation element of motor speed computing method of the present invention module.
Fig. 4 is the structural principle block diagram of a kind of embodiment pulse choice of the applied motor speed calculation element of motor speed computing method of the present invention module.
Fig. 5 is the structural principle block diagram of a kind of embodiment frequency computation part of the applied motor speed calculation element of motor speed computing method of the present invention module.
Fig. 6 is a kind of work wave synoptic diagram that possesses the speed pickup of direction deixis.
Fig. 7 is the structural principle block diagram of a kind of embodiment zero-speed of the applied motor speed calculation element of motor speed computing method of the present invention determination module.
Fig. 8 is the structural principle block diagram of a kind of embodiment dutycycle of the applied motor speed calculation element of motor speed computing method of the present invention computing module.
Among the figure: 1-low-pass filtering module, 2-pulse choice module, 3-direction determining module, 4-frequency computation part module, 5-zero-speed determination module, 6-dutycycle computing module, the 7-data outputting module, 31-pulse synthesizer, 32-timer one, 33-timer two, 34-comparer one, 401-timer three, 402-latch one, 403-latch two, 404-comparer two, 405-comparer three, 406-is from adding device one, and 407-is from adding device two, the 408-subtracter, 409-divider one, 410-wave filter, 51-timer four, 52-comparer four, 61-pulse high level timer, 62-recurrence interval timer, 63-divider two.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
A kind of motor speed computing method specifically may further comprise the steps:
S10: will carry out low-pass filtering treatment from one group of speed pulse signal pulse input A and the pulse input B of the speed pickup of motor output;
S11: will export through pulse input A and pulse input B each minute two-way that filtering is handled, wherein one road treated pulse input A and pulse input B carry out the pulse choice processing, other one road treated pulse input A and pulse input B travel direction determination processing;
S12: when treated pulse input A and pulse input B travel direction determination processing, judge current velocity reversal according to the phase differential of pulse input A and pulse input B, and direction signal is exported; When treated pulse input A and pulse input B carry out the pulse choice processing, selecting a pulse input signal that is fit to calculate from pulse input A and two pulses of pulse input B divides three the tunnel to export respectively, one road pulse input signal carries out frequency computation part to be handled, one road pulse input signal carries out the zero-speed determination processing, and one road pulse input signal carries out the dutycycle computing;
S13: one road pulse input signal carries out the zero-speed determination processing, when judging current speed pickup no-output pulse, and output zero-speed id signal; When one road pulse input signal carries out the frequency computation part processing, calculate and the output pulse frequency signal; When one road pulse input signal carries out the dutycycle computing, calculate and export current duty of ratio signal.
To shown in the accompanying drawing 8, provided the specific embodiment of a kind of motor speed computing method of the present invention as accompanying drawing 1, the invention will be further described below in conjunction with the drawings and specific embodiments.
As shown in Figure 1 be the embodiment of the applied motor speed calculation element of a kind of motor speed computing method of the present invention, the motor speed calculation element comprises: low-pass filtering module 1, pulse choice module 2, direction determining module 3, frequency computation part module 4, zero-speed determination module 5, dutycycle computing module 6 and data outputting module 7.One group of velocity pulse from the output of the speed pickup of motor, pulse input A and pulse input B input low-pass filtering module 1 carry out filtering, and the pulse input A and the pulse input B that handle through filtering export direction determining module 3 and pulse choice module 2 respectively to.Direction determining module 3 is judged current velocity reversal according to the phase differential of pulse input A and pulse input B, and exports direction signal to data outputting module 7.Pulse choice module 2 is selected a pulse that is fit to calculate and is exported frequency computation part module 4, zero-speed determination module 5 respectively to from pulse input A and two pulses of pulse input B, and dutycycle computing module 6.The output zero-speed identified to data outputting module 7 when zero-speed determination module 5 was responsible for judging current speed pickup no-output pulse.The 4 responsible calculating of frequency computation part module and output pulse frequency are to data outputting module 7.Dutycycle computing module 6 is responsible for calculating and exporting current duty of ratio signal to data outputting module 7.
As a kind of preferred implementation, the motor speed calculation element is further based on FPGA(Field Programmable Gate Array, field programmable gate array) design, pulse input A and pulse input B are one group of velocity pulse of speed pickup output.Pulse input A and pulse input B carry out filtering from the low-pass filtering module 1 that the IO pin of FPGA inputs to FPGA inside.Owing to exist electromagnetic environment abominable when practical engineering application, speed pickup is to many unfavorable factors such as the control system transmission range are long, and velocity pulse can produce the burr of high frequency because of external interference in transmission course.These burrs can have a strong impact on the accuracy of calculating, and as shown in Figure 2, the described technical scheme of the specific embodiment of the invention uses low-pass filtering module 1 to remove burr.Wherein, t is minimum pulse-high level or the low level width that can pass through.Owing to adopted based on FPGA and finished the design of motor speed calculation element with hardware description language, made the described technical scheme of the specific embodiment of the invention have very high stability and high efficiency, and higher confidentiality is arranged.The structure flexibly that possesses based on FPGA and powerful processing power, the reception that the present invention can be synchronous fully and computing possess high accuracy simultaneously than the multichannel input pulse, and the highest computational accuracy of reality can reach 0.005%.But based on field programming and modular design function, make the present invention can be transplanted to new design easily.
Pulse input A and the further input pulse of pulse input B through low-pass filtering module 1 filtering are selected module 2, pulse choice module 2 is selected a pulse that is fit to calculate according to following rule and is exported frequency computation part module 4, zero-speed determination module 5 respectively to, and dutycycle computing module 6:
When pulse input A and pulse input B exist simultaneously, pulse choice module 2 output pulses input A;
A is normal when the pulse input, when pulse input B loses, and pulse choice module 2 output pulse input A;
B is normal when the pulse input, when pulse input A loses, and pulse choice module 2 output pulse input B.
A lot of speed pickups possess the direction deixis, this function generally has the pulse of phase relation to realize by exporting two, works as signal A preceding as JT-2007-027D_JD118A type speed pickup regulation, and signal B has " A turns to " when the back, otherwise " B turns to " arranged, as shown in Figure 6.For distinguishing speed direction correctly, and avoid the influence that dutycycle and phase differential bring, direction determining module 3 also further comprises pulse synthesizer 31, timer 1, timer 2 33 and comparer 1.The present invention at first arranges a pulse synthesizer 31, and its sequential chart as shown in Figure 3.Pulse synthesizer 31 judges at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to.If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to.Timer 1 calculates the high level time of composite pulse output, and timer 2 33 calculates the cycle of pulse input A.The cycle of pulse input A compares by the high level time of comparer 1 with composite pulse output after dwindling half again, if half high level time less than composite pulse output in pulse input A cycle, the dutycycle of composite pulse output then is described greater than 50%, then by comparer one 34 output A turn signals.If half high level time greater than composite pulse output in pulse input A cycle is then by comparer one 34 output B turn signals.FPGA realizes schematic diagram as shown in Figure 4.
Frequency computation part module 4 is cores of whole invention technical scheme, and is main in order to realize the computing function of pulsed frequency.Its schematic diagram as shown in Figure 5.Frequency computation part module 4 also further comprise timer 3 401, latch 1, latch 2 403, comparer 2 404, comparer 3 405, certainly add device 1, add device 2 407, subtracter 408, divider 1, wave filter 410 and several MUX MUX certainly.MUX comprises the first MUX MUX1, the second MUX MUX2 and the 3rd MUX MUX3.Pulse input signal incoming frequency computing module 4 from pulse choice module 2, after the rising edge of pulse input signal arrives, counted by timer 3 401, latch 1 latchs the clocking value of timer 3 401 as the cycle of this subpulse, latch 2 403 latchs the cycle of a last pulse.When next pulse input signal is imported, restart timer 3 401, carry out timing next time.Value in value in the latch 1 and the latch 2 403 is subtracted each other as a comparison in subtracter 408, if fiducial value is greater than a default maximum period of change limit value, then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 2 403, if fiducial value is less than a default maximum period of change limit value, then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 1.Recurrence interval value signal Period and computation period preset value compare in comparer 2 404, if the recurrence interval value signal, adds device 2 407 certainly less than the computation period preset value recurrence interval value signal of input are sued for peace, and add device 1 certainly and add 1.When the recurrence interval value signal summing value of input during greater than the computation period preset value, the signal of computation period signal Time for the recurrence interval value signal of input is sued for peace, to export divider 1 to the computation period signal Time that is exported by the 3rd MUX MUX3 by the pulse number signal Num of second MUX MUX2 output and carry out divide operations, and will add device 1 certainly and add all zero clearings of device 2 407 certainly.If the recurrence interval value signal is during greater than the computation period preset value, then pulse number signal Num is 1, computation period signal Time is current pulse-period signal, and will export divider 1 to by the pulse number signal Num of second MUX MUX2 output and computation period signal Time by the 3rd MUX MUX3 output and carry out divide operations, and will add device one 406(certainly and be pulse number signal Num in the device 1 from adding) be computation period signal Time from adding device two 407(in the device 2 407 from adding) all zero clearings.The output signal of divider 1 is carried out output pulse frequency signal after the filtering via wave filter 410.
Output zero-speed sign when zero-speed determination module 5 is responsible for judging current speed pickup no pulse output.In the specific embodiment of the present invention, be provided with a maximum impulse cycle, after maximum impulse does not receive the rising edge of pulse in the cycle, namely think the no pulse input, and judge that the speed of this moment is zero, output zero-speed sign, its principle as shown in Figure 7.Zero-speed determination module 5 also further comprises timer 4 51 and comparer 4 52.Pulse input signal input zero-speed determination module 5 from pulse choice module 2, the rising edge of timer 4 51 paired pulses input signals catches, the output timing signal of timer 4 51 compares in comparer 4 52 with the maximum impulse periodic signal of presetting, after maximum impulse does not receive the rising edge of pulse in the cycle, namely think the no pulse input, and judge that speed at this moment is zero, the output of present speed sensor no pulse, and output zero-speed sign.
The function of dutycycle computing module 6 is to calculate each cycle length and the high level time of pulse input signal in real time, and high level time can be obtained dutycycle divided by the cycle, and its principle as shown in Figure 8.Dutycycle computing module 6 also further comprises pulse high level timer 61, recurrence interval timer 62 and divider 2 63, from the pulse input signal input duty cycle computing module 6 of pulse choice module 2.Pulse high level timer 61 calculates the high level time of pulse according to the pulse input signal of input, recurrence interval timer 62 calculates the cycle of pulse according to the pulse input signal of input, by divider 2 63 will from the pulse high level time signal of pulse high level timer 61 with carry out division arithmetic from the pulse-period signal of recurrence interval timer 62, obtain the dutycycle of pulse input signal.
Signal definition in accompanying drawing 4,5,7,8 is as follows: CLK is clock signal, and Input is input signal, and Output is output signal, and Reset is reset signal, and Start is commencing signal, and Enable is enable signal, and Update is update signal.
A kind of embodiment of utilizing the motor speed computing method that above-mentioned motor speed calculation element calculates, this method may further comprise the steps:
S10: one group of speed pulse signal pulse input A and pulse input B input low-pass filtering module 1 from the output of the speed pickup of motor carry out filtering;
S11: the pulse input A and the pulse input B that handle through filtering export pulse choice module 2 and direction determining module 3 respectively to;
S12: direction determining module 3 is judged current velocity reversal according to the phase differential of pulse input A and pulse input B, and exports direction signal to data outputting module 7; Pulse choice module 2 is selected a pulse that is fit to calculate and is exported frequency computation part module 4, zero-speed determination module 5 respectively to from pulse input A and two pulses of pulse input B, and dutycycle computing module 6;
S13: when zero-speed determination module 5 was judged current speed pickup no-output pulse, the output zero-speed identified to data outputting module 7; 4 calculating of frequency computation part module and output pulse frequency are to data outputting module 7; Dutycycle computing module 6 calculates and exports current duty of ratio signal to data outputting module 7.
The motor speed computing method are moved based on FPGA, and pulse input A and pulse input B are from the IO pin input of described FPGA, and low-pass filtering treatment is carried out in the inside of FPGA.
When pulse input A and pulse input B exist simultaneously, pulse choice module 2 output pulses input A;
A is normal when the pulse input, when pulse input B loses, and pulse choice module 2 output pulse input A;
B is normal when the pulse input, when pulse input A loses, and pulse choice module 2 output pulse input B.
The process that direction determining module 3 is judged current velocity reversal according to the phase differential of pulse input A and pulse input B further may further comprise the steps:
S121: pulse synthesizer 31 judges at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to; If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to;
S122: timer 1 calculates the high level time of composite pulse output, timer 2 33 calculates the cycle of pulse input A, the cycle of pulse input A compares by the high level time of comparer 1 with composite pulse output after dwindling half again, if half high level time less than composite pulse output in pulse input A cycle, the dutycycle of composite pulse output then is described greater than 50%, then by comparer one 34 output A turn signals; If half high level time greater than composite pulse output in pulse input A cycle is then by comparer one 34 output B turn signals.
S131: from the pulse input signal incoming frequency computing module 4 of pulse choice module 2, after the rising edge of pulse input signal arrives, counted by timer 3 401, latch 1 latchs the clocking value of timer 3 401 as the cycle of this subpulse, latch 2 403 latchs the cycle of a last pulse;
S132: when next pulse input signal is imported, restart timer 3 401, carry out timing next time; Value in value in the latch 1 and the latch 2 403 is subtracted each other as a comparison in subtracter 408, if fiducial value is greater than a default maximum period of change limit value, then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 2 403; If fiducial value is less than a default maximum period of change limit value, then the recurrence interval value signal Period by first MUX MUX1 output is the value of latch 1;
S133: recurrence interval value signal Period and computation period preset value compare in comparer 2 404, if the recurrence interval value signal, adds device 2 407 certainly less than the computation period preset value recurrence interval value signal of input are sued for peace, and add device 1 certainly and add 1;
S134: when the recurrence interval value signal summing value of input during greater than the computation period preset value, the signal of computation period signal Time for the recurrence interval value signal of input is sued for peace, export pulse number signal Num and computation period signal Time to divider 1 and carry out value average period that divide operations obtains pulse input signal, and will add certainly device 1 with from adding all zero clearings of device 2 407;
S135: if the recurrence interval value signal is during greater than the computation period preset value, then pulse number signal Num is 1, computation period signal Time is current pulse-period signal, and export pulse number signal Num and computation period signal Time to divider 1 and carry out divide operations, and will add certainly device 1 with from adding all zero clearings of device 2 407;
S136: the output signal of divider 1 is carried out output pulse frequency signal after the filtering via wave filter 410.
The process of output zero-speed sign further may further comprise the steps when zero-speed determination module 5 was judged current speed pickup no-output pulse:
Pulse input signal input zero-speed determination module 5 from pulse choice module 2, the rising edge of timer 4 51 paired pulses input signals catches, the output timing signal of timer 4 51 compares in comparer 4 52 with the maximum impulse periodic signal of presetting, after maximum impulse does not receive the rising edge of pulse in the cycle, namely think the no pulse input, and judge that speed at this moment is zero, the output of present speed sensor no pulse, and output zero-speed sign.
The process that dutycycle computing module 6 calculated and exported current duty of ratio signal further may further comprise the steps:
Pulse input signal input duty cycle computing module 6 from pulse choice module 2, pulse high level timer 61 calculates the high level time of pulse according to the pulse input signal of input, recurrence interval timer 62 calculates the cycle of pulse according to the pulse input signal of input, by divider 2 63 will from the pulse high level time signal of pulse high level timer 61 with carry out division arithmetic from the pulse-period signal of recurrence interval timer 62, obtain the dutycycle of pulse input signal.
The present invention uses FPGA and hardware description language to finish design, and changes all algorithms into hardware circuit and be solidificated on the FPGA, possesses higher real-time, accuracy and stability.The present invention uses FPGA to calculate, and it possesses concurrency completely, and under the situation of FPGA internal resource abundance, can reach the calculating of tens of way input pulses simultaneously in 0.1 ~ 500KHz frequency range.The present invention uses the igniter module of FPGA to carry out pulse capture, can walk abreast easily to catch the multichannel input pulse.The present invention supports velocity reversal judgement, zero-speed decision-making function and pulse duty factor computing function on the basis that speed pickup possesses corresponding function.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet is not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, be equal to replacements, equivalence changes and modify, all still belong in the scope that technical solution of the present invention protects.
Claims (7)
1. motor speed computing method is characterized in that, may further comprise the steps:
S10: will carry out low-pass filtering treatment from one group of speed pulse signal pulse input A and the pulse input B of the speed pickup of motor output;
S11: will export through pulse input A and pulse input B each minute two-way that filtering is handled, wherein one road treated pulse input A and pulse input B carry out the pulse choice processing, other one road treated pulse input A and pulse input B travel direction determination processing;
S12: when treated pulse input A and pulse input B travel direction determination processing, judge current velocity reversal according to the phase differential of pulse input A and pulse input B, and direction signal is exported; When treated pulse input A and pulse input B carry out the pulse choice processing, selecting a pulse input signal that is fit to calculate from pulse input A and two pulses of pulse input B divides three the tunnel to export respectively, one road pulse input signal carries out frequency computation part to be handled, one road pulse input signal carries out the zero-speed determination processing, and one road pulse input signal carries out the dutycycle computing;
S13: one road pulse input signal carries out the zero-speed determination processing, when judging current speed pickup no-output pulse, and output zero-speed id signal; When one road pulse input signal carries out the frequency computation part processing, calculate and the output pulse frequency signal; When one road pulse input signal carries out the dutycycle computing, calculate and export current duty of ratio signal.
2. a kind of motor speed computing method according to claim 1, it is characterized in that: described motor speed computing method are moved based on FPGA, pulse input A and pulse input B are from the IO pin input of described FPGA, and low-pass filtering treatment is carried out in the inside of FPGA.
3. a kind of motor speed computing method according to claim 2, it is characterized in that: pulse input A and pulse input B through low-pass filtering treatment carry out the pulse choice processing, the pulse choice processing is selected a pulse input signal that is fit to calculate according to following rule and is divided three tunnel outputs, carries out frequency computation part processing, zero-speed determination processing and dutycycle computing respectively:
When pulse input A and pulse input B exist simultaneously, output pulse input A;
A is normal when the pulse input, when pulse input B loses, and output pulse input A;
B is normal when the pulse input, when pulse input A loses, and output pulse input B.
4. according to the described a kind of motor speed computing method of arbitrary claim in the claim 1 to 3, it is characterized in that: when treated pulse input A and pulse input B travel direction determination processing, the process of judging current velocity reversal according to the phase differential of pulse input A and pulse input B further may further comprise the steps:
S121: judge at the rising edge of input system clock whether pulse input A rising edge occurred in last system clock cycle, if then composite pulse output transfers high level to; If pulse input B rising edge occurred in last system clock cycle, then composite pulse output transfers low level to;
S122: the high level time that calculates composite pulse output, and the cycle of calculating pulse input A, the high level time that the cycle that A is imported in pulse dwindles after half with composite pulse output again compares, if half high level time less than composite pulse output in pulse input A cycle, illustrate that then the dutycycle of composite pulse output greater than 50%, then exports the A turn signal; If half high level time greater than composite pulse output in pulse input A cycle is then exported the B turn signal.
5. a kind of motor speed computing method according to claim 4 is characterized in that: select a pulse input signal that is fit to calculate and carry out the process that frequency computation part handles and further may further comprise the steps from pulse input A and two pulses of pulse input B:
S131: after the rising edge of pulse input signal arrives, at first count, will latch as the cycle of this subpulse through the clocking value that counts to get, and the cycle of a last pulse is latched;
S132: when next pulse input signal is imported, restart counting, carry out timing next time; The periodic quantity of the periodic quantity of this subpulse and a last pulse is subtracted each other and is compared, if fiducial value greater than a default maximum period of change limit value, then Shu Chu recurrence interval value signal is the periodic quantity of a last pulse; If fiducial value is less than a default maximum period of change limit value, Shu Chu the recurrence interval value signal periodic quantity of subpulse for this reason then;
S133: recurrence interval value signal and computation period preset value compare, and, then the recurrence interval value signal of input is sued for peace less than the computation period preset value as if the recurrence interval value signal, and pulse number signal Num is carried out from adding 1 operation;
S134: when the recurrence interval value signal summing value of input during greater than the computation period preset value, the signal of computation period signal Time for the recurrence interval value signal of input is sued for peace, divide operations is carried out in pulse number signal Num and computation period signal Time output, and will carry out the result of sum operation and pulse number signal Num to the recurrence interval value signal of input from all zero clearings of result of add operation;
S135: if the recurrence interval value signal is during greater than the computation period preset value, then pulse number signal Num is 1, computation period signal Time is current pulse-period signal, and pulse number signal Num and computation period signal Time output carried out divide operations, and with computation period signal Time and all zero clearings of pulse number signal Num;
S136: divide operations result's output signal is carried out filtering and is handled back output pulse frequency signal.
6. a kind of motor speed computing method according to claim 5 is characterized in that: select the process that a pulse input signal that is fit to calculate carries out the zero-speed determination processing and further may further comprise the steps from pulse input A and two pulses of pulse input B:
The rising edge of paired pulses input signal catches and carries out timing and operate, timing operation output signal compares with the maximum impulse periodic signal of presetting, if do not receive the rising edge of pulse input signal in the cycle in maximum impulse, namely think the no pulse input, and the speed of judging this moment is zero, the output of present speed sensor no pulse, and output zero-speed sign.
7. a kind of motor speed computing method according to claim 6 is characterized in that: select the process that a pulse input signal that is fit to calculate carries out the dutycycle computing and further may further comprise the steps from pulse input A and two pulses of pulse input B:
Calculate the high level time of pulse according to the pulse input signal of input, according to the cycle of the pulse input signal calculating pulse of importing, pulse high level time signal and pulse-period signal are carried out division arithmetic, obtain the dutycycle of pulse input signal.
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| CN105628955B (en) * | 2015-12-25 | 2018-10-30 | 南京南瑞集团公司 | A kind of speed measuring device and its speed-measuring method of pump-storage generator static frequency changer |
| CN106089598B (en) * | 2016-06-02 | 2019-08-16 | 三一重能有限公司 | A kind of wind power generator rotor detection method and system |
| CN106444459B (en) * | 2016-11-15 | 2023-04-28 | 贵州大学 | Control device for detecting duty ratio of rectangular wave signal in real time and implementation method |
| CN108013838B (en) * | 2017-10-31 | 2020-12-11 | 北京视觉世界科技有限公司 | Monitoring method, device and equipment for cleaning equipment and storage medium |
| CN108226761B (en) * | 2017-12-28 | 2020-06-02 | 合肥工大高科信息科技股份有限公司 | Method for real-time acquisition and alternate self-inspection of speed of rail transit vehicle |
| CN110579618B (en) * | 2019-09-17 | 2021-08-20 | 西安翔迅科技有限责任公司 | Motor rotating speed acquisition and analysis device and method based on FPGA |
| CN114109794B (en) * | 2021-11-26 | 2023-08-04 | 广东美的暖通设备有限公司 | Steering determination method, apparatus, readable storage medium, and air conditioning device |
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