CN104079265B - High-frequency clock dutycycle detecting system - Google Patents
High-frequency clock dutycycle detecting system Download PDFInfo
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Abstract
The invention discloses a kind of high-frequency clock dutycycle detecting system, it includes the first detection loop and the second detection loop, first detection loop includes the first sampler, the first multiphase clock generator and Digital Logical Circuits, first multiphase clock generator produces n phase clock pulses according to high-frequency clock to be measured, high-frequency clock to be measured is sampled by the first sampler according to n phase clock pulses, the dutycycle of the first high-speed clock signal of Digital Logical Circuits counting input；Second detection loop is connected between the first multiphase clock generator and mathematical logic circuit, its a pair adjacent clock exported according to the first multiphase clock generator and produce m phase clock pulses, and under m phase clock pulses, high-frequency clock to be measured is sampled, the dutycycle of the second high-speed clock signal of Digital Logical Circuits counting input.The dutycycle detecting system of the present invention can detect the dutycycle of high-frequency clock to be measured rapidly, and testing result is accurate, precision is high, and shared chip area is little, low in energy consumption, applied widely.
Description
Technical field
The present invention relates to integrated circuit fields, relate more specifically to a kind of high-frequency clock dutycycle detecting system.
Background technology
High speed integrated circuit design is more and more higher to the quality of clock signal.Clock signal quality is except traditional
Outside clock jitter, clock duty cycle increasingly becomes the key factor affecting high speed integrated circuit performance.So
It is very important for detecting the dutycycle of high-frequency clock in real time.
But, the mode of the dutycycle detecting high-frequency clock the most in integrated circuits is to introduce in chip periphery
One high-frequency clock, carries out multiple repairing weld, but the peripheral high-frequency clock introduced general more high-frequency clock to be measured
For the twice or more of high-frequency clock frequency to be measured, due to the shadow of the factors such as chip package, test equipment
Ring, easily cause the change of the dutycycle of the high-frequency clock of introducing, frequency, so that the duty that detection obtains
Ratio result inaccuracy.
Therefore, it is necessary to provide the high-frequency clock dutycycle detecting system of a kind of improvement to overcome drawbacks described above.
Summary of the invention
It is an object of the invention to provide a kind of high-frequency clock dutycycle detecting system, the dutycycle detection of the present invention
System can detect the dutycycle of high-frequency clock to be measured rapidly, and testing result is accurate, precision is high, this
Chip area shared by bright detecting system is little, low in energy consumption, applied widely.
For achieving the above object, the present invention provides a kind of high-frequency clock dutycycle detecting system, and it includes first
Detection loop and the second detection loop, when described first detection loop includes the first sampler, the first leggy
Clock generator and Digital Logical Circuits, described first multiphase clock generator produces n according to high-frequency clock to be measured
Phase clock pulses, and n phase clock pulses input extremely described first sampler that will produce, n is for being more than or equal to
The natural number of 3, the high-frequency clock to be measured of input is entered by described first sampler according to the n phase clock pulses received
Row sampling, the first high-speed clock signal after sampling is inputted described Digital Logical Circuits by described first sampler,
Described Digital Logical Circuits counts the dutycycle of the first high-speed clock signal of input and exports the first counting knot
Really；Described second detection loop is connected to described first multiphase clock generator and described mathematical logic circuit
Between, a pair rising edge that described second detection loop exports according to described first multiphase clock generator/under
Fall produces m phase clock pulses along the adjacent clock changed, and m is the natural number more than or equal to 3,
And under described m phase clock pulses, described high-frequency clock to be measured is sampled, and by high for second after sampling
Speed clock signal input is to described Digital Logical Circuits, and the second of described Digital Logical Circuits counting input is at a high speed
The dutycycle of clock signal also exports the second count results.
It is preferred that described second detection loop include edge logic decision circuitry, clock selector, more than second
Phase clock generator and the second sampler, described edge logic decision circuitry judges that described first sampler is defeated
The rising edge of the first high-speed clock signal gone out/trailing edge change, described clock selector is patrolled according to described edge
The judged result collecting decision circuitry is selected in the n phase clock pulses of described first multiphase clock generator output
Select the adjacent two phase clock that rising edge/trailing edge changes, and by the input of this two phase clock to described more than second
Phase clock generator, described second multiphase clock generator produces between the phase place of this adjacent two phase clock
Raw m phase clock pulses, described second sampler is according to the m phase clock pulses the received high speed to be measured to input
Clock is sampled, and by the second high-speed clock signal input after sampling to described Digital Logical Circuits, institute
State the dutycycle of the second high-speed clock signal of Digital Logical Circuits counting input and export the second count results.
It is preferred that described m phase clock pulses includes the adjacent two phase clock pulse that described clock selector exports,
And the first phase clock pulses of described m phase clock pulses is that in described adjacent two phase clock pulse, phase place is forward
One phase clock pulses, last phase clock pulses of described m phase clock pulses is described adjacent two phase clock arteries and veins
A phase place phase clock pulses rearward in punching.
It is preferred that described first sampler was treated described within a clock cycle of described high-frequency clock to be measured
Survey high-frequency clock and carry out n sampling.
It is preferred that described edge logic decision circuitry is right within a clock cycle of described high-frequency clock to be measured
First high-speed clock signal of described first sampler output carries out the judgement of rising edge/trailing edge change.
Compared with prior art, the high-frequency clock dutycycle detecting system of the present invention is owing to including the first detection ring
Road and the second detection loop so that described first detection loop and the second detection loop are all to high-frequency clock to be measured
Dutycycle detect, draw the first count results and the second count results, and described second detection respectively
Loop selects a pair rising edge/trailing edge to change among the n phase clock pulses that the first detection loop is sampled
Adjacent clock and produce m phase clock pulses, again high-frequency clock to be measured is entered under this m phase clock pulses
Row sampling, thus the dutycycle again detecting described high-frequency clock to be measured detects；Therefore the height of the present invention
Clock duty cycle detecting system testing result is accurate, precision is high for speed；It is and shared chip area is little, low in energy consumption,
Applied widely.
By description below and combine accompanying drawing, the present invention will become more fully apparent, and these accompanying drawings are used for explaining
The present invention.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of high-frequency clock dutycycle detecting system of the present invention.
Fig. 2 is the working timing figure of high-frequency clock dutycycle detecting system.
Detailed description of the invention
With reference now to accompanying drawing, describing embodiments of the invention, element numbers similar in accompanying drawing represents similar unit
Part.As it has been described above, the invention provides a kind of high-frequency clock dutycycle detecting system, the dutycycle of the present invention
Detecting system can detect the dutycycle of high-frequency clock to be measured rapidly, and testing result is accurate, precision is high,
Chip area shared by the detecting system of the present invention is little, low in energy consumption, applied widely.
Refer to the structured flowchart that Fig. 1, Fig. 1 are high-frequency clock dutycycle detecting system of the present invention.As it can be seen,
The high-frequency clock dutycycle detecting system of the present invention, including the first detection loop and the second detection loop, described
The dutycycle of high-frequency clock to be measured is all detected by the first detection loop with the second detection loop.Described first
Detection loop includes the first sampler, the first multiphase clock generator and Digital Logical Circuits；High speed to be measured
Clock CLK input to described first multiphase clock generator, described first multiphase clock generator according to
High-frequency clock CLK to be measured produces n phase clock pulses (CLKO1, CLKO2 ... CLKOn), and will produce
Raw clock pulses (CLKO1, CLKO2 ... CLKOn) input is to described first sampler, wherein,
N phase clock pulses (CLKO1, CLKO2 ... CLKOn) is different from high-frequency clock CLK to be measured except phase place
Outward, other parameter is all identical with high-frequency clock CLK to be measured；In the present invention, n is more than or equal to 3
Natural number；Described first sampler is according to the n phase clock pulses (CLKO1, CLKO2 ... CLKOn) received
Within a clock cycle of described high-frequency clock CLK to be measured, described high-frequency clock CLK to be measured is carried out n
Secondary sampling, thus obtain the first high-speed clock signal after sampling (O1, O2 ... On), and by described
One high-speed clock signal (O1, O2 ... On) inputs described Digital Logical Circuits；Described Digital Logical Circuits
Count the dutycycle of first high-speed clock signal (O1, O2 ... On) of input and export the first count results
A, and precision is 1/n, it should be apparent that, described first high-speed clock signal (O1, O2 ... On) accounts for
Empty is identical than the dutycycle with high-frequency clock CLK to be measured, because described first high-speed clock signal
The phase parameter of (O1, O2 ... On) and described n phase clock pulses (CLKO1, CLKO2 ...
CLKOn) phase parameter is identical, and only phase place has difference；Here, due to described first detection loop
Precision be 1/n, therefore through described Digital Logical Circuits counting output the first count results A be only described in treat
Survey the integer part that the dutycycle coarse adjustment of high-frequency clock CLK is interval.Described second detection loop is connected to described
Between first multiphase clock generator and described mathematical logic circuit, described second detection loop is according to described
First multiphase clock generator exports adjacent clock that a pair rising edge/trailing edge change and produces m phase
Clock pulses, m is the natural number more than or equal to 3, and to described to be measured under described m phase clock pulses
High-frequency clock CLK samples, and obtains the second high-speed clock signal after sampling, and during by the second high speed
The input of clock signal is to described Digital Logical Circuits, the second high-frequency clock of described Digital Logical Circuits counting input
The dutycycle of signal also exports the second count results；And the precision of sampled result is 1/m, due to described m phase
Clock pulses be according to described first multiphase clock generator output a pair adjacent clock and produce, therefore
Through the duty that dutycycle result is described high-frequency clock CLK to be measured that described second detection loop detection obtains
The integer part more interval than fine tuning；Thus on the basis of described first detection loop, described second detection ring
Road carries out detection meter to the integer part that the fine tuning of the dutycycle of described high-frequency clock CLK to be measured is interval further
Number, therefore, testing result is accurate, precision is high.
Specifically, described second detection loop include edge logic decision circuitry, clock selector, more than second
Phase clock generator and the second sampler.Described edge logic decision circuitry is at described high-frequency clock to be measured
One clock cycle of CLK interior the first high-speed clock signal to described first sampler output (O1,
O2 ... On) the change of rising edge/trailing edge judge, namely judge clock pulses (CLKO1,
CLKO2 ... CLKOn) the change of rising edge/trailing edge, and will determine that result input is selected to described clock
Select device；Described clock selector according to the judged result of described edge logic decision circuitry described first heterogeneous
The n phase clock pulses (CLKO1, CLKO2 ... CLKOn) of bit clock generator output selects to rise
The adjacent two phase clock pulse that edge/trailing edge changes, and by the input of this two phase clock to the most described second heterogeneous
Bit clock generator, i.e. when described edge logic decision circuitry judge described first high-speed clock signal (O1,
O2 ... On) in clock signal On-x and clock signal O-x-1 (x is the natural number less than n) upper
Rise edge/trailing edge when all changing, described clock selector then select n phase clock pulses (CLKO1,
CLKO2 ... CLKOn) in two corresponding clock pulses CLKOn-x and CLKOn-x-1, and by this two
Clock pulses input to described second multiphase clock generator, at this by this two clock pulses CLKOn-x with
CLKOn-x-1 is expressed as CLKx1 Yu CLKx2 (as shown in Figure 1).Described second multiphase clock occurs
Device produce between the phase place of this two phase clock pulse CLKx1 and CLKx2 m phase clock pulses (CLKP1,
CLKP2 ... CLKPm), and input to described second sampler；Described second sampler is according to the m received
The high-frequency clock CLK to be measured of input is carried out by phase clock pulses (CLKP1, CLKP2 ... CLKPm)
Sampling, the second high-speed clock signal (P1, P2 ... Pm) after sampling is inputted institute by described second sampler
State Digital Logical Circuits, the second high-speed clock signal of described Digital Logical Circuits counting input (P1, P2 ...
Pm) dutycycle also exports the second count results B；It should be evident that described second high-speed clock signal (P1,
P2 ... Pm) dutycycle and two clock pulses CLKx1 selected by described clock selector and CLKx2
Dutycycle be identical, only phase place has difference, separately, as it has been described above, described two clock pulses CLKx1
It is only rising edge/trailing edge in n phase clock pulses (CLKO1, CLKO2 ... CLKOn) with CLKx2
Adjacent two clock pulses all changed, therefore through the second counting of described Digital Logical Circuits counting output
Result B is the integer part in the dutycycle fine tuning interval of described high-frequency clock CLK to be measured, and its precision is
1/n*m.Therefore, count results A exported by described Digital Logical Circuits can be accurately detected with B
Go out the dutycycle knot of described high-frequency clock CLK to be measured, and testing result is accurate, precision is high.
In a preferred embodiment of the invention, the m phase clock of described second multiphase clock generator output
Pulse (CLKP1, CLKP2 ... CLKPm) includes the adjacent two phase clock that described clock selector exports
Pulse CLKx1 and CLKx2, and described m phase clock pulses (CLKP1, CLKP2 ... CLKPm)
The first phase clock pulses be that in described adjacent two phase clock pulse CLKx1 with CLKx2, phase place is forward one
Phase clock pulses, last phase clock pulses of described m phase clock pulses is described adjacent two phase clock pulse
A phase place phase clock pulses rearward in CLKx1 Yu CLKx2.I.e., specifically, when described clock pulses
When the phase place of CLKx1 is ahead of the phase place of described clock pulses CLKx2, m phase clock pulses (CLKP1,
CLKP2 ... CLKPm) in the first phase clock pulses CLKP1 be clock pulses CLKx1；And work as
When the phase place of described clock pulses CLKx2 lags behind the phase place of described clock pulses CLKx1, m phase clock
Last phase clock pulses CLKPm in pulse (CLKP1, CLKP2 ... CLKPm) is clock
Pulse CLKx；Vice versa.To ensure described m phase clock pulses (CLKP1, CLKP2 ... CLKPm)
Phase place all fall within described clock selector select two phase clock pulse CLKx1 Yu CLKx2 phase place it
Between, thus ensure that the accuracy rate of result B of described Digital Logical Circuits counting output.
Below in conjunction with Fig. 1 and Fig. 2, the operation principle of high-frequency clock dutycycle detecting system of the present invention is described.Institute
State n phase clock pulses that the first multiphase clock generator produces according to high-frequency clock CLK to be measured (CLKO1,
CLKO2 ... CLKOn) height (low) level of high-frequency clock CLK is sampled, as in figure 2 it is shown, and
State the first sampler to sample in a clock cycle (Tp) of high-frequency clock CLK.At this clock
In cycle (Tp), when n phase clock pulses (CLKO1, CLKO2 ... CLKOn) is equivalent to high speed
Clock CLK has carried out n over-sampling of sampling, and the precision of sampling is 1/n, and first obtained sampling is high
Speed clock signal (O1, O2 ... On) input is to described edge logic decision circuitry and Digital Logical Circuits.
Described edge logic decision circuitry according to first high-speed clock signal (O1, O2 ... On) of described input,
In a clock cycle (Tp) of high-frequency clock CLK to adjacent two adjacent first high-speed clock signals (O1,
O2 ... On) carry out judging the change of rising edge/trailing edge, thus show that judged result gives the choosing of described clock
Select device, for choosing the adjacent clock pair required for the second sampler samples.Described clock selector is according to institute
State the judged result n phase clock in described first multiphase clock generator output of edge logic decision circuitry
Adjacent two that in pulse (CLKO1, CLKO2 ... CLKOn), selection rising edge/trailing edge changes
Phase clock pulses (adjacent clock to), and this two phase clock CLKx1 with CLKx2 (is illustrated in figure 2
Clock pulses CLKO1 and CLKO2) input extremely described second multiphase clock generator, described more than second
Phase clock generator produces m phase clock between the phase place of this two phase clock pulse CLKx1 and CLKx2
Pulse (CLKP1, CLKP2 ... CLKPm), described second sampler is according to the m phase clock arteries and veins received
The high-frequency clock CLK to be measured of input is sampled by punching (CLKP1, CLKP2 ... CLKPm), and
The second high-speed clock signal (P1, P2 ... Pm) after sampling is inputted described Digital Logical Circuits.Described
The result that Digital Logical Circuits is exported according to the first sampler and the second sampler, high-frequency clock CLK's
In one clock cycle, the first high-speed clock signal (O1, O2 ... On) sampled is counted,
Draw the first count results A；The second high-speed clock signal (P1, P2 ... Pm) sampled is counted
Number, draws the second count results B.
Can obtain by calculating, dutycycle DCD of high-frequency clock CLK to be measured is:
DCD=A ÷ n+B ÷ n ÷ m
Wherein: the value of n, m can design according to practical situation, it is commonly known that ground, n, m value is the biggest,
The precision of the above results is the highest.In the present invention, the dutycycle accuracy of detection of described high-frequency clock CLK to be measured
For 1/n*m, testing result is accurate, precision is high.
Above in association with most preferred embodiment, invention has been described, but the invention is not limited in disclosed above
Embodiment, and amendment, the equivalent combinations that the various essence according to the present invention is carried out should be contained.
Claims (5)
1. a high-frequency clock dutycycle detecting system, it is characterised in that include the first detection loop and second
Detection loop, described first detection loop includes the first sampler, the first multiphase clock generator and numeral
Logic circuit, described first multiphase clock generator produces n phase clock pulses according to high-frequency clock to be measured,
And n phase clock pulses input extremely described first sampler that will produce, n is the natural number more than or equal to 3,
The high-frequency clock to be measured of input is sampled by described first sampler according to the n phase clock pulses received, institute
State the first sampler and the first high-speed clock signal after sampling is inputted described Digital Logical Circuits, described numeral
Logic circuit counts the dutycycle of the first high-speed clock signal of input and exports the first count results；Described
Two detection loop are connected between described first multiphase clock generator and described Digital Logical Circuits, described
Second detection loop becomes according to a pair rising edge/trailing edge of described first multiphase clock generator output
The adjacent clock changed and produce m phase clock pulses, m is the natural number more than or equal to 3, and at described m
Under phase clock pulses, described high-frequency clock to be measured is sampled, and by the second high-speed clock signal after sampling
Input counts the second high-speed clock signal of input to described Digital Logical Circuits, described Digital Logical Circuits
Dutycycle also exports the second count results.
2. high-frequency clock dutycycle detecting system as claimed in claim 1, it is characterised in that described second
Detection loop includes edge logic decision circuitry, clock selector, the second multiphase clock generator and second
Sampler, described edge logic decision circuitry judges the first high-speed clock signal of described first sampler output
The change of rising edge/trailing edge, described clock selector is according to the judged result of described edge logic decision circuitry
Rising edge/trailing edge is selected to become in the n phase clock pulses of described first multiphase clock generator output
The adjacent two phase clock changed, and by the input of this two phase clock to described second multiphase clock generator, described
Second multiphase clock generator produces m phase clock pulses between the phase place of this adjacent two phase clock, described
The high-frequency clock to be measured of input is sampled by the second sampler according to the m phase clock pulses received, and will adopt
The second high-speed clock signal input after sample is to described Digital Logical Circuits, and described Digital Logical Circuits counting is defeated
The dutycycle of the second high-speed clock signal entered also exports the second count results.
3. high-frequency clock dutycycle detecting system as claimed in claim 2, it is characterised in that described m phase
Clock pulses includes the adjacent two phase clock pulse that described clock selector exports, and described m phase clock pulses
The first phase clock pulses be the phase clock pulses that in described adjacent two phase clock pulse, phase place is forward, described m
Last phase clock pulses of phase clock pulses is a phase place phase time rearward in described adjacent two phase clock pulse
Clock.
4. high-frequency clock dutycycle detecting system as claimed in claim 2, it is characterised in that described first
Described high-frequency clock to be measured was carried out n time adopting within a clock cycle of described high-frequency clock to be measured by sampler
Sample.
5. high-frequency clock dutycycle detecting system as claimed in claim 2, it is characterised in that described edge
Described first sampler was exported within a clock cycle of described high-frequency clock to be measured by logic judging circuit
First high-speed clock signal carries out the judgement of rising edge/trailing edge change.
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| KR102408439B1 (en) * | 2017-12-26 | 2022-06-14 | 에스케이하이닉스 주식회사 | Clock monitoring circuit |
| CN114155903B (en) * | 2020-09-07 | 2023-08-25 | 长鑫存储技术有限公司 | Test system and test method |
| CN113300692A (en) * | 2021-05-08 | 2021-08-24 | 黑芝麻智能科技(上海)有限公司 | System and method for monitoring clock duty cycle |
| CN117250480B (en) * | 2023-11-08 | 2024-02-23 | 英诺达(成都)电子科技有限公司 | Loop detection method, device, equipment and storage medium of combinational logic circuit |
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| CN101629978A (en) * | 2008-12-26 | 2010-01-20 | 和芯微电子(四川)有限公司 | Method and circuit for realizing real-time monitoring for duty ratio |
| CN202586900U (en) * | 2012-04-05 | 2012-12-05 | 四川和芯微电子股份有限公司 | Frequency multiplier circuit having function of automatically regulating output signal duty ratio |
| CN203951450U (en) * | 2014-06-23 | 2014-11-19 | 四川和芯微电子股份有限公司 | High-frequency clock duty ratio detection system |
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| CN101645702B (en) * | 2009-08-03 | 2011-11-02 | 四川和芯微电子股份有限公司 | Dutyfactor adjusting method and circuit |
| US20130207703A1 (en) * | 2012-02-10 | 2013-08-15 | International Business Machines Corporation | Edge selection techniques for correcting clock duty cycle |
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| CN101629978A (en) * | 2008-12-26 | 2010-01-20 | 和芯微电子(四川)有限公司 | Method and circuit for realizing real-time monitoring for duty ratio |
| CN202586900U (en) * | 2012-04-05 | 2012-12-05 | 四川和芯微电子股份有限公司 | Frequency multiplier circuit having function of automatically regulating output signal duty ratio |
| CN203951450U (en) * | 2014-06-23 | 2014-11-19 | 四川和芯微电子股份有限公司 | High-frequency clock duty ratio detection system |
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