CN102902879A - Synchronous phasor calculation method based on discrete Fourier transform (DFT) recursion of field programmable gate array (FPGA) hardware - Google Patents

Abstract

The invention relates to a synchronous phasor calculation method based on DFT recursion of FPGA hardware. An FPGA is configured through a central processing unit (CPU) and controls an analog-digital (AD) converter to complete a sampling process under the 1 pulse per second signal (1PPS) synchronization, and the cycle DFT calculation and the recursion DFT calculation are utilized for eliminating accumulated errors of the recursion DFT calculation; and a complex phasor compensation algorithm is completed by the CPU. The FPGA and the CPU are matched to complete an acquisition calculation compensation process of synchronous phasors, and both the high-speed parallel computing capability of the FPGA and the flexible floating-point operation function of the CPU are used. The recursion DFP operation which is long in consumed time is completed by the FPGA, and the CPU loads are small, so that the communication response instantaneity of the CPU is guaranteed, and further, the communication reliability of a power management unit (PMU) is improved.

Description

A kind of synchronized phasor computing method based on FPGA hardware DFT recursion

Technical field

A kind of synchronized phasor computing method based on FPGA hardware DFT recursion belong to the Automation of Electric Systems field of measuring technique.

Background technology

Along with the development of China's power grid construction, grid structure is day by day perfect, also becomes increasingly complex, and strengthens the dynamic security monitoring capacity of electrical network in the urgent need to new technological means is arranged, and improves the electricity net safety stable level.Tradition SCADA system acquisition be the steady state data that second level refreshes, fault oscillograph provides before and after the fault fast transient Wave data in a period of time, the Dynamic Phasors data that provide the network-wide basis inter-sync to gather of all having no idea.Synchronous phasor measuring device (PMU) then utilizes the satellite synchronizing clock system to provide unified sampling pulse and the standard time for the whole network synchronized sampling in the wide scope; so that identical time reference point and sampling reference point have been arranged between each website; the dynamic process that resulting synchronized phasor can the accurate description real system at synchronized sampling and after calculating,, observing and controlling novel protected for electric system, safety and stability is controlled that new data source is provided.

Traditional synchronized phasor computing method generally adopt CPU or the sampling of the advanced row of DSP data, again sampled data is carried out reality and the section's imaginary part information that the DFT recursive operation obtains phasor, put in the DFT coefficient buffer zone, then according to the requirement of main website, periodically from this buffer zone, extract phasor real part imaginary part, calculate the amplitude phase angle of this phasor, and stamp the precise time label, send to main website.Such disposal route requires the CPU of PMU device that stronger data-handling capacity will be arranged, particularly a present PMU device generally gathers the electric parameters of a plurality of elements, operand is huge, the taller speed of PMU device sends the synchronized phasor data that calculate toward main website in real time in addition, the fastest every 5ms will send a frame message, need CPU that stronger communication capacity is arranged.Traditional like this disposal route often causes cpu load too high, possibly can't accomplish even transmission to the synchronized phasor data message that main website sends, and is unfavorable for that the data of main website are processed.There is the problem of deviation accumulation in traditional DFT recursive operation simultaneously, particularly in the situation that floating-point operation is easy to cause error calculated to become large.

Summary of the invention

For overcoming the prior art deficiency, the present invention seeks to be to provide a kind ofly by CPU FPGA to be configured, the sampling interruption computation process that operand is large is put among the FPGA to be finished, and adopt cycle DFT computing and DFT recursive computing to eliminate the synchronized phasor computing method based on FPGA hardware DFT recursion of the cumulative errors of DFT recursive computing, guaranteed the real-time communication of PMU.。

For achieving the above object, method of the present invention comprises following steps:

(1) (1) FPGA adopts parallel bus to be connected with CPU at hardware, and the look-at-me of FPGA is connected to the external interrupt pin of CPU, and FPGA is by parallel bus control AD chip;

(2) CPU is configured FPGA, the original coefficient of appointing system rated frequency, every cycle sampling number N, phasor calculation cycle T k, DFT recursive;

(3) after externally standard second pulse of FPGA (1PPS) signal is calibrated, draw the inside 1PPS ' signal that is synchronized with outside 1PPS signal;

(4) FPGA is synchronously lower sampling of inner 1PPS ' signal, and carries out the DFT recursive operation and the order component calculates, and after specifying phasor calculation cycle T k to arrive, stamps accurate absolute time label, deposits result of calculation in appointed buffer, supplies CPU to read.

The formula of described DFT recursive is:

$\mathrm{Ac}1\left(k\right)=\mathrm{Ac}1(k-1)+\frac{2}{N}[x\left(k\right)-x(k-1)]\cos \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

$\mathrm{As}1\left(k\right)=\mathrm{As}1(k-1)+\frac{2}{N}[x\left(k\right)-x(k-1)]\sin \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

Ac1 (k): the k time recursion fundamental phasors real part

As1 (k): the k time recursion fundamental phasors imaginary part

Ac1 (k-1): the k time recursion fundamental phasors real part initial value

As1 (k-1): the k time recursion fundamental phasors imaginary part initial value

N: every cycle sampling number

X (k): k sampled point in the sampling buffer

Described order component computing formula is as follows:

U1r=Uar-(Ubr+Ucr)*0.5+(Ucm-Ubm)*0.866

U1m=Uam-(Ubm+Ucm)*0.5+(Ubr-Ucr)*0.866

U2r=Uar-(Ubr+Ucr)*0.5+(Ubm-Ucm)*0.866

U2m=Uam-(Ubm+Ucm)*0.5-(Ubr-Ucr)*0.866

U0r=(Uar+Ubr+Ucr)/3

U0m=(Uam+Ubm+Ucm)/3

Uar, Ubr, Ucr UA, UB, the real part of UC phasor

Uam, Ubm, Ucm UA, UB, the real part of UC phasor

U1r, U2r, U0r positive sequence (U1), negative phase-sequence (U2), the real part of zero sequence (U0) phasor

U1m, U2m, U0m positive sequence (U1), negative phase-sequence (U2), the real part of zero sequence (U0) phasor;

(5) FPGA carries out a DFT computing after the 1PPS signal, and uses the next time initial value of DFT recursive of its result's conduct, to solve the cumulative errors problem of DFT recursive;

The formula of described DFT computing is as follows:

${\mathrm{<figure-callout\; id="1"\; label="Ac"\; filenames="HDA00002064375900012.png"\; state="\{\{state\}\}">Ac</figure-callout>}1}^{\&prime;}=\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x\left(j\right)\cos \left(\frac{2*j*\mathrm{Pi}}{N}\right)$

${\mathrm{As}1}^{\&prime;}=\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x\left(j\right)\sin \left(\frac{2*j*\mathrm{Pi}}{N}\right)$

The fundamental phasors real part of a cycle DFT computing after the Ac1':1PPS signal

The fundamental phasors imaginary part of a cycle DFT computing after the As1':1PPS signal

X (0) ... x (N-1): the sampled data of a cycle after each 1PPS pulse

The formula of the N+1 point DFT recursive after the described 1PPS signal is as follows:

$\mathrm{Ac}1\left(k\right)=\mathrm{<figure-callout\; id="1"\; label="Ac"\; filenames="HDA00002064375900012.png"\; state="\{\{state\}\}">Ac</figure-callout>}{1}^{\&prime;}+\frac{2}{N}[x\left(k\right)-x(k-1)]\cos \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

$\mathrm{As}1\left(k\right)=\mathrm{As}{1}^{\&prime;}+\frac{2}{N}[x\left(k\right)-x(k-1)]\sin \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

Ac1 (k): the k time recursion fundamental phasors real part

As1 (k): the k time recursion fundamental phasors imaginary part

The fundamental phasors real part of a cycle DFT computing after the Ac1':1PPS signal

The fundamental phasors imaginary part of a cycle DFT computing after the As1':1PPS signal

(6) CPU response FPGA interrupts, and reads sampled data and DFT recursion result, according to positive sequence phasor calculation frequency, judges whether to enable the phasor backoff algorithm according to frequency again;

Described frequency computation part formula is as follows:

$f=f0+\frac{\mathrm{\&Delta;\&theta;}}{2*\mathrm{\&pi;}*\mathrm{Tk}}$

Δ θ: the phase changing capacity of the fundamental positive sequence voltage phasor in the Tk time

F0: system's rated frequency (50Hz or 60Hz)

F: system's actual frequency

Tk: phasor calculation interval time

Error between phasor measurements and the theoretical value is related with the departure degree of system frequency and rated frequency, and formula is as follows:

$F^{\&prime;}*\frac{\sin \left(\frac{\mathrm{\&pi;\&Delta;f}}{50}\right)}{N*\sin \left(\frac{\mathrm{\&pi;\&Delta;f}}{50N}\right)}{\mathrm{<figure-callout\; id="2"\; label="e"\; filenames="HDA00002064375900012.png"\; state="\{\{state\}\}">e</figure-callout>}}^{\frac{2\mathrm{\&pi;}*\mathrm{\&Delta;f}*j}{50N}i}$

N: every cycle sampling number

Δ f: the bias of system frequency and rated frequency

F': original phasor value

F: the phasor value after the compensation

Adopt high speed parallel bus to connect between being specially of described step (2): CPU and the FPGA, FPGA leaves the external interrupt pin of IO interface access CPU, interrupts in order to trigger CPU.FPGA has accessed 1PPS signal and the B code time signal of standard time clock.CPU is configured by parallel bus FPGA, such as original coefficient of system's rated frequency, every cycle sampling number N, phasor calculation cycle T k, DFT recursive etc.

Described step (3) is specially: FPGA carries out the smothing filtering in 512 cycles to satellite clock signal 1PPS, the randomized jitter of satellite clock disappears, output is synchronized with the good inside 1PPS ' (in fact this signal has represented the ideal value of satellite 1PPS signal) that tames of satellite clock signal, even externally during the 1PPS dropout, inner 1PPS ' signal still can guarantee the synchronization accuracy in the certain hour;

Described step (4) is specially: FPGA inner 1PPS ' signal synchronously under sample, and carry out recursive operation according to above-mentioned DFT recursive formula, calculate simultaneously the order component, after specifying phasor calculation cycle T k to arrive, stamp accurate absolute time label, deposit result of calculation in appointed buffer, read for CPU.In order to realize above-mentioned DFT recursive computing, in the calculating process of FPGA, all coefficients have carried out 65536 times amplification, in cumulative process, have used 64 digit counters, guarantee that calculating process does not overflow.

Described step (5) is specially: when FPGA arrives at 1PPS ' signal, a DFT computing is carried out in the utilization after this sampled data of a cycle (N point), and utilize acquired results Ac1 (k) ', As1 (k) ' to arrive the initial value of the DFT recursive behind the cycle as 1PPS ' signal, be to carry out a DFT computing in the per second, the initial value that DFT recursive will occur behind 1PPS ' signal one cycle is replaced, to solve the cumulative errors problem of DFT recursive.

Described step (6) is specially: CPU response FPGA interrupts, read real part, the imaginary data of all sampled values and all phasors by parallel bus, according to positive sequence phasor calculation system frequency, whether according to the departure degree of system frequency and rated frequency, differentiating needs to start the phasor backoff algorithm.

The another kind of way of realization of described step (6) is specially: adopt independent DSP to carry out the calculating of frequency and the compensation operation of phasor.

The invention has the beneficial effects as follows: the ability that the present invention utilizes the high-speed parallel of FPGA to calculate, synchronal data sampling process and DFT recursive computing and other numerous long computation processes consuming time are placed among the FPGA finish, thereby with CPU from sampling frequently interrupt and heavy DFT calculating process free, main task is concentrated in the order of response main website, guaranteed the real-time communication of PMU.Simultaneously the present invention adopts cycle DFT computing+DFT recursive computing to eliminate the cumulative errors of DFT recursive computing, has both utilized the rapidity of DFT recursive computing, has utilized again the DFT computing can eliminate the characteristic of cumulative errors.

Description of drawings

Fig. 1 is the block scheme that step among the present invention (1) is implemented;

Fig. 2 is the schematic diagram that step among the present invention (4) is implemented;

Embodiment

For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with accompanying drawing 1 and accompanying drawing 2, further set forth the present invention.

Referring to Fig. 1 and Fig. 2, a kind of synchronized phasor computing method based on FPGA hardware DFT recursion of the present invention is characterized in that the method includes the steps of:

(1) FPGA is connected in 32 of hardware employings or 64 bit parallel buses 1 with CPU, and FPGA has look-at-me to be connected to the external interrupt pin of CPU, and FPGA accesses 1PPS signal and the B code time signal of standard time clock, and FPGA is by parallel bus 2 control AD chips;

(2) at FPGA side definition sampling configuration register (CONFIG_REG), sampling buffer register (DATA_REG), the original register of DFT coefficient (DFT_COEF), DFT result buffer register (DFT_REG);

(3) CPU writes predefined DFT coefficient the predefine register DFT_COEF of FPGA, and system's rated frequency, every cycle sampling number N, synchronized phasor computation period Tk are write sampling configuration register (CONFIG_REG);

(4) FPGA carries out the smothing filtering in 512 cycles to satellite clock signal 1PPS, the randomized jitter of satellite clock disappears, output is synchronized with the good inside 1PPS ' (in fact this signal has represented the ideal value of satellite 1PPS signal) that tames of satellite clock signal, even externally during the 1PPS dropout, inner 1PPS ' signal still can guarantee the synchronization accuracy in the certain hour;

(5) FPGA carries out frequency multiplication according to the configuration sampling rate to inner 1PPS ', draw the sampling pulse synchronous with inner 1PPS ' signal, and under this sampling pulse, carry out AD and sample, sample and stamp accurate absolute time label after complete, deliver to sampling buffer register DATA_REG, read for CPU;

The formula of DFT recursive is:

$\mathrm{Ac}1\left(k\right)=\mathrm{Ac}1(k-1)+\frac{2}{N}[x\left(k\right)-x(k-1)]\cos \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

$\mathrm{As}1\left(k\right)=\mathrm{As}1(k-1)+\frac{2}{N}[x\left(k\right)-x(k-1)]\sin \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

Ac1 (k): the k time recursion fundamental phasors real part

As1 (k): the k time recursion fundamental phasors imaginary part

Ac1 (k-1): the k time recursion fundamental phasors real part initial value

As1 (k-1): the k time recursion fundamental phasors imaginary part initial value

N: every cycle sampling number

X (k): k sampled point in the sampling buffer

Described order component computing formula is as follows:

U1r=Uar-(Ubr+Ucr)*0.5+(Ucm-Ubm)*0.866

U1m=Uam-(Ubm+Ucm)*0.5+(Ubr-Ucr)*0.866

U2r=Uar-(Ubr+Ucr)*0.5+(Ubm-Ucm)*0.866

U2m=Uam-(Ubm+Ucm)*0.5-(Ubr-Ucr)*0.866

U0r=(Uar+Ubr+Ucr)/3

U0m=(Uam+Ubm+Ucm)/3

Uar, Ubr, Ucr UA, UB, the real part of UC phasor

Uam, Ubm, Ucm UA, UB, the real part of UC phasor

U1r, U2r, U0r positive sequence (U1), negative phase-sequence (U2), the real part of zero sequence (U0) phasor

U1m, U2m, U0m positive sequence (U1), negative phase-sequence (U2), the real part of zero sequence (U0) phasor;

(6) FPGA carries out that DFT recursive operation and order component phasor (positive sequence, negative phase-sequence, zero sequence) are calculated, power calculation, according to institute's configuration synchronization phasor calculation cycle, periodically real part and the imaginary part parameter with the synchronized phasor that calculates deposits DFT result buffer register (DFT_REG) in, and cut-off CPU reads in the generation; In order to realize above-mentioned DFT recursive computing, in the calculating process of FPGA, all coefficients have carried out 65536 times amplification, in cumulative process, have used 64 digit counters, guarantee that calculating process does not overflow.

(7) FPGA carries out the DFT computing that a time N order after inner 1PPS ' signal arrives, and the initial value of N+1 point DFT recursive after utilizing acquired results as the 1PPS signal, with the cumulative errors problem of solution DFT recursive.Namely carry out simultaneously N point DFT and DFT recursive computing in the cycle after 1PPS, and use the result of DFT computing to replace the initial value of DFT recursive at the N+1 point, as shown in Figure 2.

CPU response FPGA interrupts, and reads real part, the imaginary data of all sampled values and all phasors, and according to positive sequence phasor calculation system frequency, whether according to the departure degree of system frequency and rated frequency, differentiating needs to start the phasor backoff algorithm; Described frequency computation part formula is as follows:

$f=\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="HDA00002064375900012.png"\; state="\{\{state\}\}">f</figure-callout>}0+\frac{\mathrm{\&Delta;\&theta;}}{2*\mathrm{\&pi;}*\mathrm{Tk}}$

Δ θ: the phase changing capacity of the fundamental positive sequence voltage phasor in the Tk time

F0: system's rated frequency (50Hz or 60Hz)

F: system's actual frequency

TK: phasor calculation interval time

Error between phasor measurements and the theoretical value is related with the departure degree of system frequency and rated frequency, and formula is as follows:

$F^{\&prime;}*\frac{\sin \left(\frac{\mathrm{\&pi;\&Delta;f}}{50}\right)}{N*\sin \left(\frac{\mathrm{\&pi;\&Delta;f}}{50N}\right)}{\mathrm{<figure-callout\; id="2"\; label="e"\; filenames="HDA00002064375900012.png"\; state="\{\{state\}\}">e</figure-callout>}}^{\frac{2\mathrm{\&pi;}*\mathrm{\&Delta;f}*j}{50N}i}$

N: every cycle sampling number

Δ f: the bias of system frequency and rated frequency

F': original phasor value

F: the phasor value after the compensation

(8) CPU mails to main website with all synchronized phasor data and other result of calculations according to standard agreement and main website configuration requirement (CFG2).

What the present invention relates to is a kind of synchronized phasor computing method based on FPGA hardware DFT recursion, it is configured FPGA by CPU, FPGA controls AD at the 1PPS signal synchronously and finishes sampling process, and adopts cycle DFT computing+DFT recursive computing to eliminate the cumulative errors of DFT recursive computing; Complicated phasor backoff algorithm is then finished by CPU.FPGA and CPU cooperate the collection computing compensation process of finishing synchronized phasor together, namely utilize the high-speed parallel computing power of FPGA, utilize again flexibly floating-point operation function of CPU.Because long DFT recursive computing consuming time is finished by FPGA, cpu load is less, has guaranteed the real-time of CPU communication response, thereby has improved the communication reliability of PMU.

Above demonstration and described ultimate principle of the present invention and principal character and advantage of the present invention.The technician of the industry should understand; the present invention is not restricted to the described embodiments; that describes in above-described embodiment and the instructions just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.

Claims (6)

1. the synchronized phasor computing method based on FPGA hardware DFT recursion is characterized in that, may further comprise the steps:

(1) FPGA adopts parallel bus to be connected with CPU at hardware, and the look-at-me of FPGA is connected to the external interrupt pin of CPU, and FPGA is by parallel bus control AD chip;

(2) CPU is configured FPGA, the original coefficient of appointing system rated frequency, every cycle sampling number N, phasor calculation cycle T k, DFT recursive;

(3) after externally standard second pulse of FPGA (1PPS) signal is calibrated, draw the inside 1PPS ' signal that is synchronized with outside 1PPS signal;

(4) FPGA is synchronously lower sampling of inner 1PPS ' signal, and carries out the DFT recursive operation and the order component calculates, and after specifying phasor calculation cycle T k to arrive, stamps accurate absolute time label, deposits result of calculation in appointed buffer, supplies CPU to read;

Described DFT recursive operation formula is:

$\mathrm{Ac}1\left(k\right)=\mathrm{Ac}1(k-1)+\frac{2}{N}[x\left(k\right)-x(k-1)]\cos \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

$\mathrm{As}1\left(k\right)=\mathrm{As}1(k-1)+\frac{2}{N}[x\left(k\right)-x(k-1)]\sin \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

Ac1 (k): the k time recursion fundamental phasors real part

As1 (k): the k time recursion fundamental phasors imaginary part

N: every cycle sampling number

X (k): k the described order component of sampled point computing formula in the sampling buffer is as follows:

U1r=Uar-(Ubr+Ucr)*0.5+(Ucm-Ubm)*0.866

U1m=Uam-(Ubm+Ucm)*0.5+(Ubr-Ucr)*0.866

U2r=Uar-(Ubr+Ucr)*0.5+(Ubm-Ucm)*0.866

U2m=Uam-(Ubm+Ucm)*0.5-(Ubr-Ucr)*0.866

U0r=(Uar+Ubr+Ucr)/3

U0m=(Uam+Ubm+Ucm)/3

Uar, Ubr, Ucr UA, UB, the real part of UC phasor

Uam, Ubm, Ucm UA, UB, the real part of UC phasor

U1r, U2r, U0r positive sequence (U1), negative phase-sequence (U2), the real part of zero sequence (U0) phasor

U1m, U2m, U0m positive sequence (U1), negative phase-sequence (U2), the real part of zero sequence (U0) phasor

(5) FPGA carries out N point DFT computing after the 1PPS signal, and uses its result as the initial value of N+1 point DFT recursive;

The formula of described DFT computing is as follows:

${\mathrm{Ac}1}^{\&prime;}=\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x\left(j\right)\cos \left(\frac{2*j*\mathrm{Pi}}{N}\right)$

${\mathrm{As}1}^{\&prime;}=\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x\left(j\right)\sin \left(\frac{2*j*\mathrm{Pi}}{N}\right)$

The fundamental phasors real part of a cycle DFT computing after the Ac1':1PPS signal

The fundamental phasors imaginary part of a cycle DFT computing after the As1':1PPS signal

X (0) ... x (N-1): the sampled data of a cycle after each 1PPS pulse

The formula of the N+1 point DFT recursive after the described 1PPS signal is as follows:

$\mathrm{Ac}1\left(k\right)=\mathrm{Ac}{1}^{\&prime;}+\frac{2}{N}[x\left(k\right)-x(k-1)]\cos \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

$\mathrm{As}1\left(k\right)=\mathrm{As}{1}^{\&prime;}+\frac{2}{N}[x\left(k\right)-x(k-1)]\sin \left(\frac{2*k*\mathrm{Pi}}{N}\right)$

Ac1 (k): the k time recursion fundamental phasors real part

As1 (k): the k time recursion fundamental phasors imaginary part

The fundamental phasors real part of a cycle DFT computing after the Ac1':1PPS signal

The fundamental phasors imaginary part of a cycle DFT computing after the As1':1PPS signal

(6) CPU response FPGA interrupts, and reads sampled data and DFT recursion result, according to positive sequence phasor calculation frequency, judges whether to enable the phasor backoff algorithm according to frequency again; CPU response FPGA interrupts, and reads sampled data and DFT recursion result, according to positive sequence phasor calculation frequency, judges whether to enable the phasor backoff algorithm according to frequency again;

Described frequency computation part formula is as follows:

$f=f0+\frac{\mathrm{\&Delta;\&theta;}}{2*\mathrm{\&pi;}*\mathrm{Tk}}$

Δ θ: the phase changing capacity of the fundamental positive sequence voltage phasor in the Tk time

F0: system's rated frequency (50Hz or 60Hz)

F: system's actual frequency

Tk: phasor calculation interval time

Described phasor backoff algorithm formula is as follows:

$F^{\&prime;}*\frac{\sin \left(\frac{\mathrm{\&pi;\&Delta;f}}{50}\right)}{N*\sin \left(\frac{\mathrm{\&pi;\&Delta;f}}{50N}\right)}{e}^{\frac{2\mathrm{\&pi;}*\mathrm{\&Delta;f}*j}{50N}i}$

N: every cycle sampling number

Δ f: the bias of system frequency and rated frequency

F': original phasor value

F: the phasor value after the compensation.

2. require described a kind of synchronized phasor computing method based on FPGA hardware DFT recursion such as right 1, it is characterized in that, comprise that also fpga chip introduced 1PPS signal and the B code clock signal of satellite standard synchronous clock.

3. require described a kind of synchronized phasor computing method based on FPGA hardware DFT recursion such as right 1, it is characterized in that, also comprise, after the 1PPS signal, carry out simultaneously DFT recursive and DFT computing in the cycle, and adopt later on the result of DFT computing as the initial value of DFT recursive at a cycle.

4. require described a kind of synchronized phasor computing method based on FPGA hardware DFT recursion such as right 2, it is characterized in that, in the described step (3), FPGA carries out the smothing filtering in 512 cycles to satellite clock signal 1PPS, disappear the randomized jitter of satellite clock, output is synchronized with the good inside 1PPS ' that tames of satellite clock signal.

5. require described a kind of synchronized phasor computing method based on FPGA hardware DFT recursion such as right 1, it is characterized in that, in the described step (4), when described FPGA arrives at 1PPS ' signal, a DFT computing is carried out in the utilization after this sampled data of a cycle (N point), and utilize acquired results Ac1 (k) ', As1 (k) ' to arrive the initial value of the DFT recursive behind the cycle as 1PPS ' signal, be to carry out a DFT computing in the per second, the initial value that DFT recursive will occur behind 1PPS ' signal one cycle is replaced.

6. require described a kind of synchronized phasor computing method based on FPGA hardware DFT recursion such as right 1, it is characterized in that, in the described step (6), CPU response FPGA interrupts, read real part, the imaginary data of all sampled values and all phasors by parallel bus, according to positive sequence phasor calculation system frequency, whether according to the departure degree of system frequency and rated frequency, differentiating needs to start the phasor backoff algorithm.

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