CN102683308B - Through-silicon-vias structure and formation method thereof - Google Patents
Through-silicon-vias structure and formation method thereof Download PDFInfo
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Abstract
The invention relates to a through-silicon-vias structure and a formation method thereof. The formation method includes that a semiconductor substrate is provided, the semiconductor substrate includes an upper surface and a lower surface which are opposite to each other, the upper surface of the semiconductor substrate is subjected to an etching to form an opening, a conducting material is filled in the opening to form first connecting pegs, the lower surface of the semiconductor substrate is subjected to the etching to form a groove, the first connecting pegs are exposed at the bottom of the groove, a conducting material which is capable of being etched is filled in the groove, the conducting material which is capable of being etched is subjected to the etching to form second connecting pegs, each of the second connecting pegs is vertically connected with each of the first connecting pegs, and dielectric layers are filled gaps between the second connecting pegs and the semiconductor substrate and gaps between adjacent second connecting pegs. The through-silicon-vias structure and the formation method thereof have the advantages that the reliability of the through-silicon-vias structure is improved, and the cavity defect is prevented.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly one wears through-silicon via structure and forming method thereof.
Background technology
The integrated circuit vertical stacking of two panels or more is encapsulated in same chip by 3D encapsulation, thus the space taken can be reduced, the substrate of bearing integrated conventional in 3D encapsulation often has wears through-silicon via structure (TSV, Through-Silicon-Vias).Wear through-silicon via structure and replace traditional edge line by adopting and carry out 3D encapsulation, can in a little device package (footprint) integrated more logic function.In addition, employing is worn through-silicon via structure and effectively can be shortened critical path (critical path), reduces to postpone, improves device speed.
Wear through-silicon via structure and mainly form the through hole run through on a semiconductor substrate, and fill formation connected nail (nail) wherein, to be connected with the interconnection structure on another wafer or another chip by connected nail afterwards and to realize 3D and encapsulate, its formation method has multiple, comprise: wear through-silicon via structure precedence method, first formed before formation circuit and wear through-silicon via structure; Mid-term, through-silicon via structure method was worn in formation, before completing after road technique (after forming device), carry out postchannel process before (before forming interconnection structure) formed and wear through-silicon via structure; Through-silicon via structure method is worn in rear formation, after the circuit has been completed, is formed and wear through-silicon via structure after namely forming device and interconnection structure; After bonding formed wear through-silicon via structure method, by two wafers or by a wafer and chip piece bonding after formed wear through-silicon via structure method.
Prior art wear through-silicon via structure mainly based on copper wiring technique formed, Fig. 1 to Fig. 5 shows a kind of profile wearing the intermediate structure of the formation method of through-silicon via structure of prior art.
With reference to figure 1, provide Semiconductor substrate 10, described Semiconductor substrate 10 can be formed with semiconductor device, as MOS transistor, also can be formed with semiconductor device and interconnection structure, or also can not comprise semiconductor device and interconnection structure.
With reference to figure 2, the upper surface of described Semiconductor substrate 10 is etched, form opening 11.
With reference to figure 3, form barrier layer 12, cover the upper surface of the bottom of described opening, sidewall and described Semiconductor substrate 10, metallic copper 13 is formed by galvanoplastic afterwards on described barrier layer 12, fill described opening, form inculating crystal layer (seedlayer) being formed on the surface being also included in described barrier layer 12 before metallic copper 13.
With reference to figure 4, planarization is carried out to the metallic copper covered over the semiconductor substrate 10 and barrier layer 12, to the upper surface exposing described Semiconductor substrate 10, form connected nail 13a.
With reference to figure 5, carry out thinning from the lower surface of described Semiconductor substrate 10 to it, to exposing described connected nail 13a, making described opening become the through hole running through whole Semiconductor substrate 10, completing the forming process of wearing through-silicon via structure.
Be no matter adopt wear through-silicon via structure precedence method, mid-term formed wear through-silicon via structure method, rear formation forms after wearing through-silicon via structure method or bonding and wears through-silicon via structure method, wears based on copper wiring technique the filling problem that the larger challenge of in the forming process of through-silicon via structure one is metallic copper.Such as, at such as MEMS (micro electro mechanical system) (MEMS, Micro-electromechanical System) etc. application in, transducer needs to be connected with control circuit, described transducer and control circuit can be produced in different Semiconductor substrate respectively, and adopt and wear through-silicon via structure each subelement in transducer is connected with each subelement correspondence in control unit, thus simplified design and production process, raising yield.
But this kind of application often needs to be formed on a semiconductor substrate highdensityly wears through-silicon via structure, and what namely form greater number in unit are wears through-silicon via structure.In order to meet the demand of density, the diameter wearing through-silicon via structure must become very little, but simultaneously in order to ensure the mechanical strength of Semiconductor substrate itself, the thickness of Semiconductor substrate needs enough large, and this just causes the depth-to-width ratio (aspect ratio) of wearing silicon through hole to become very large.Along with the continuous increase of depth-to-width ratio of wearing through hole in through-silicon via structure, when particularly depth-to-width ratio is greater than 10: 1, formation continuous print barrier layer and inculating crystal layer become very difficult, cavity blemish (void) is there is in the connected nail that the discontinuous meeting of barrier layer and inculating crystal layer is formed after causing electroplating filling, make reliability decrease, even likely cause open circuit problem.
About more detailed descriptions of wearing through-silicon via structure, please refer to the patent No. is 7,683,459 and 7,633, the United States Patent (USP) of 165.
Summary of the invention
The problem that the present invention solves is along with depth-to-width ratio increases, based on the problem of wearing through-silicon via structure reliability decrease of copper wiring technique in prior art.
For solving the problem, the invention provides one and wearing through-silicon via structure, comprising:
Semiconductor substrate, described Semiconductor substrate is formed with groove, is filled with dielectric layer in described groove;
Run through the connected nail of described Semiconductor substrate and described dielectric layer, described connected nail comprises the first connected nail and the second connected nail that connect up and down, described first connected nail is embedded in described Semiconductor substrate, described second connected nail is embedded in described dielectric layer, and the material of described second connected nail is the electric conducting material that can etch.
Alternatively, the described electric conducting material etched is selected from aluminium, the polysilicon of doping or the polycrystalline silicon germanium of doping.
Alternatively, the material of described dielectric layer is selected from silica, silicon oxynitride or low k dielectric materials.
Alternatively, the material of described first connected nail is selected from the polysilicon of copper, tungsten, aluminium or doping.
Present invention also offers a kind of formation method of wearing through-silicon via structure, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises relative upper surface and lower surface;
The upper surface of described Semiconductor substrate is etched, forms opening;
Filled conductive material in said opening, forms the first connected nail;
Etch the lower surface of described Semiconductor substrate, form groove, described bottom portion of groove exposes described first connected nail;
In described groove, fill the electric conducting material that can etch, and etch the described electric conducting material etched, form the second connected nail, described second connected nail connects up and down with described first connected nail;
Filled media layer in space between described second connected nail and described Semiconductor substrate and the space between the second adjacent connected nail.
Alternatively, the described electric conducting material etched is selected from aluminium, the polysilicon of doping or the polycrystalline silicon germanium of doping.
Alternatively, the described electric conducting material etched is aluminium, uses physical vapour deposition (PVD) or chemical vapour deposition (CVD) in described groove, fill the electric conducting material that can etch.
Alternatively, the material of described dielectric layer is selected from silica, silicon oxynitride or low k dielectric materials.
Alternatively, after described first connected nail of formation, before forming described groove, described formation method also comprises:
The upper surface of described Semiconductor substrate is fixed on bearing substrate;
Carry out thinning to the lower surface of described Semiconductor substrate.
Alternatively, before the upper surface of described Semiconductor substrate is fixed on bearing substrate, described formation method also comprises: form photoetching alignment mark (lithographyalignment mark) at the upper surface of described Semiconductor substrate, the degree of depth of described photoetching alignment mark is greater than the degree of depth of described first connected nail.
Alternatively, the described lower surface to described Semiconductor substrate carry out thinning after, expose described photoetching alignment mark.
Alternatively, described bearing substrate is silicon substrate or glass substrate.
Alternatively, described electric conducting material is copper, and the described material of filled conductive in said opening, forms the first connected nail and comprise:
Barrier layer and copper seed layer is formed successively in the bottom of described opening and sidewall;
Fill metallic copper in said opening, described metallic copper covers described copper seed layer;
Planarization is carried out, to the upper surface exposing described Semiconductor substrate to the surface of described metallic copper.
Alternatively, described electric conducting material is tungsten or aluminium, uses physical vapour deposition (PVD) (PVD) or chemical vapour deposition (CVD) (CVD) filled conductive material in said opening.
Alternatively, described electric conducting material is the polysilicon of doping, uses chemical vapour deposition (CVD) filled conductive material in said opening.
Alternatively, after the described dielectric layer of formation, described formation method also comprises: carry out planarization to the surface of described dielectric layer, to exposing described second connected nail.
Compared with prior art, embodiments of the invention have the following advantages:
The embodiment of the present invention wear in the formation method of through-silicon via structure, first the opening of depth-to-width ratio appropriateness is formed at the upper surface of Semiconductor substrate, and fill formation first connected nail wherein, usually, the depth-to-width ratio of described opening selects comparatively moderate numerical value, to improve the filling effect of described first connected nail, avoid wherein occurring the problems such as cavity blemish; Groove is formed afterwards at the lower surface of described Semiconductor substrate, in described groove, fill the electric conducting material that can etch and form the second connected nail after it is etched, usually, the groove that width is larger can be formed, namely described groove has less depth-to-width ratio, to improve the filling effect of the described electric conducting material that can etch, thus avoid the cavity blemish problem in the second connected nail formed by etching.Therefore, what the present embodiment was formed wears through-silicon via structure and can also have higher reliability while having large depth-to-width ratio.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is a kind of cross-sectional view of wearing the formation method of through-silicon via structure of prior art;
Fig. 6 is the schematic flow sheet that the present invention wears the embodiment of the formation method of through-silicon via structure;
Fig. 7 to Figure 19 is the cross-sectional view that the present invention wears the embodiment of the formation method of through-silicon via structure.
Embodiment
In prior art, formation wears the method for through-silicon via structure mainly based on copper wiring technique, along with the increase of wearing through-silicon via structure density, its depth-to-width ratio also increases accordingly, cause copper diffusion barrier layer and copper seed layer possibly cannot cover the inner surface of through hole completely, thus produce cavity blemish in the connected nail formed after making to electroplate filling, cause the reliability decrease of wearing through-silicon via structure, even occur open circuit problem.
The embodiment of the present invention wear in the formation method of through-silicon via structure, first the opening of depth-to-width ratio appropriateness is formed at the upper surface of Semiconductor substrate, and fill formation first connected nail wherein, usually, the depth-to-width ratio of described opening selects comparatively moderate numerical value, to improve the filling effect of described first connected nail, avoid wherein occurring the problems such as cavity blemish; Groove is formed afterwards at the lower surface of described Semiconductor substrate, in described groove, fill the electric conducting material that can etch and form the second connected nail after it is etched, usually, the groove that width is larger can be formed, namely described groove has less depth-to-width ratio, to improve the filling effect of the described electric conducting material that can etch, thus avoid the cavity blemish problem in the second connected nail formed by etching.Therefore, what the present embodiment was formed wears through-silicon via structure and can also have higher reliability while having large depth-to-width ratio.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
Fig. 6 shows the schematic flow sheet wearing the embodiment of the formation method of through-silicon via structure of the present invention, comprising:
Step S21, provides Semiconductor substrate, and described Semiconductor substrate comprises relative upper surface and lower surface;
Step S22, etches the upper surface of described Semiconductor substrate, forms opening;
Step S23, in said opening filled conductive material, form the first connected nail;
Step S24, etches the lower surface of described Semiconductor substrate, and form groove, described bottom portion of groove exposes described first connected nail;
Step S25, in described groove, fill the electric conducting material that can etch, and etch the described electric conducting material etched, form the second connected nail, described second connected nail connects up and down with described first connected nail;
Step S26, filled media layer in the space between described second connected nail and described Semiconductor substrate and the space between the second adjacent connected nail.
Fig. 7 to Figure 19 shows generalized section of wearing the embodiment of the formation method of through-silicon via structure of the present invention, is described in detail to the first embodiment below in conjunction with Fig. 6 and Fig. 7 to Figure 19.
Composition graphs 6 and Fig. 7, perform step S21, provide Semiconductor substrate 20, described Semiconductor substrate 20 comprises relative upper surface 20a and lower surface 20b.Particularly, described Semiconductor substrate 20 can be silicon substrate, germanium silicon substrate, iii-v element compound substrate, silicon carbide substrates or its laminated construction, or silicon on insulated substrate, or well known to a person skilled in the art other semiconductive material substrate.In the present embodiment, described Semiconductor substrate 20 is silicon substrate, wherein can be formed with transducer or control circuit etc., also can be blank silicon substrate.
Composition graphs 6 and Fig. 8, perform step S22, etch the upper surface 20a of described Semiconductor substrate 20, forms opening 20c.Exemplarily, the number of the opening 20c formed in Fig. 8 is 3.The forming process of described opening 20c can comprise: on the upper surface 20a of described Semiconductor substrate 20, form photoresist layer and graphically, define the figure of described opening 20c; With described graphical after photoresist layer etch for the upper surface 20a of mask to described Semiconductor substrate 20, form described opening 20c; Remove described graphical after photoresist layer.
It should be noted that, described opening 20c does not penetrate described Semiconductor substrate 20, its width equals to expect the width wearing the link nail in through-silicon via structure formed, the degree of depth of described opening 20c is determined by follow-up materials and process of filling the first connected nail formed, that is the depth-to-width ratio of described opening 20c needs the filling effect ensureing follow-up the first connected nail adopting the conventional technique such as CVD, plating to be formed, and prevents from wherein occurring cavity blemish.
Composition graphs 6 and Figure 10, perform step S23, in said opening filled conductive material 23, form the first connected nail.Described electric conducting material 23 is selected from the polysilicon of copper, tungsten, aluminium or doping.In the present embodiment, described electric conducting material 23 is copper, and described first connected nail comprises the barrier layer 21 and copper seed layer 22 that are formed at described opening sidewalls and bottom successively.The forming process of described first connected nail is illustrated below with reference to Fig. 9 and Figure 10.
First with reference to figure 9, form barrier layer 21 and copper seed layer 22 successively in the bottom of described opening and sidewall, barrier layer 21 described in the present embodiment and copper seed layer 22 also cover the upper surface 20a of described Semiconductor substrate 20.The material on described barrier layer 21 can be Ta, TaN etc., and the formation method of described barrier layer 21 and copper seed layer 22 can be PVD.
Afterwards with reference to Figure 10, filled conductive material 23, is specially metallic copper in said opening, and described metallic copper covers described copper seed layer 22; After filling planarization is carried out to the surface of described metallic copper, as chemico-mechanical polishing (CMP), to the upper surface 20a exposing described Semiconductor substrate 20.
In other specific embodiments, described electric conducting material 23 also can be tungsten or aluminium, and its fill method is PVD or CVD; Described electric conducting material 23 can also be the polysilicon of doping, and its fill method is CVD, and the method that original position (in-situ) can be used to adulterate introduces Doped ions in polysilicon.
Composition graphs 6 and Figure 14, perform step S24, etch the lower surface 20b of described Semiconductor substrate 20, and form groove 25, described groove 25 bottom-exposed goes out described first connected nail.Describe in detail below with reference to Figure 11 to Figure 14.
First with reference to Figure 11, photoetching alignment mark 24 is formed at the upper surface 20a of described Semiconductor substrate 20, the degree of depth of described photoetching alignment mark 24 is greater than the degree of depth of described first connected nail, namely the degree of depth of described opening is greater than, more specifically, the degree of depth of described photoetching alignment mark 24 is more than or equal to the degree of depth of wearing the connected nail in through-silicon via structure that expection is formed.Described photoetching alignment mark 24 can be formed in a groove of described upper surface 20a, also can be the medium or metal material of filling wherein after forming groove.
Afterwards with reference to Figure 12, the upper surface 20a of described Semiconductor substrate 20 is fixed on bearing substrate 30.Described bearing substrate 30 can be silicon substrate, glass substrate etc.Fixing method can be bonding, bonding etc.
Afterwards with reference to Figure 13, carry out thinning to the lower surface 20b of described Semiconductor substrate 20, the thickness being thinned to remaining Semiconductor substrate 20 can meet the requirement to mechanical strength in practical application.After thinning, the lower surface 20b of described Semiconductor substrate 20 exposes described photoetching alignment mark 24.
Afterwards with reference to Figure 14, described Semiconductor substrate 20 and described bearing substrate 30 are overturn, the lower surface 20b of described Semiconductor substrate 20 is etched, form groove 25.The bottom-exposed of described groove 25 goes out described first connected nail, is specially and exposes described barrier layer 21 in the present embodiment.The width of described groove 25 needs enough wide, to ensure the filling effect of the follow-up electric conducting material etched.In the present embodiment, before the width range covering of described groove 25, be formed in the scope of whole first connected nails of upper surface 20a.The forming process of described groove 25 can comprise photoetching, etching etc.
Composition graphs 6, Figure 15 and Figure 16, perform step S25, in described groove, fill the electric conducting material 26 that can etch, and the described electric conducting material 26 etched is etched, form the second connected nail 26a, described second connected nail 26a connects up and down with described first connected nail.Concrete, in the present embodiment, described second connected nail 26a connects with described barrier layer 21.
The described electric conducting material 26 etched is selected from aluminium, the polysilicon of doping or the polycrystalline silicon germanium of doping.In the present embodiment, the described electric conducting material 26 etched is preferably aluminium, and its fill method is PVD or CVD.
Can be carried out graphically the described electric conducting material 26 etched by the technique such as photoetching, etching, thus the first connected nail forming the second connected nail 26a, each second connected nail 26a corresponding with position respectively connects up and down.Can be aimed at by described photoetching alignment mark 24 in described patterned process, the position of the second connected nail 26a formed to make etching can be corresponding with the position of the first connected nail being formed at upper surface 20a.
It should be noted that, when etching the described electric conducting material 26 etched, need the described electric conducting material 26 etched to wear quarter, the bottom-exposed in the space namely formed after etching goes out described Semiconductor substrate 20, insulated from each other to ensure between each second connected nail 26a that etching is formed.
Composition graphs 6 and Figure 17, perform step S26, the space between described second connected nail 26a and described Semiconductor substrate 20 and the fill gaps dielectric layer 27 between the second adjacent connected nail 26a.The material of described dielectric layer 27 is selected from silica, silicon oxynitride or low k dielectric materials, and its formation method can be CVD.Filling in the process forming described dielectric layer 27, the dielectric layer 27 of formation can cover the surface of described second connected nail 26a, can also carry out planarization, to exposing described second connected nail 26a therefore to the surface of described dielectric layer 27.Can be chemico-mechanical polishing or selective etch etc. to the flattening method of described dielectric layer 27.
So far, the through-silicon via structure of wearing that the present embodiment is formed with reference to Figure 17, can comprise: Semiconductor substrate 20, described Semiconductor substrate 20 is formed with groove, is filled with dielectric layer 27 in described groove; Run through the connected nail of described Semiconductor substrate 20 and described dielectric layer 27, described connected nail comprises the first connected nail (specifically comprising barrier layer 21, copper seed layer 22 and metallic copper 23 in the present embodiment) and the second connected nail 26a that connect up and down, wherein, first connected nail is embedded in described Semiconductor substrate 20, described second connected nail is embedded in described dielectric layer 27, and the material of described second connected nail is the electric conducting material that can etch.
Through-silicon via structure of wearing in the present embodiment is made up of with the second connected nail being formed in lower surface the first connected nail being respectively formed at upper surface.Because the depth-to-width ratio of the opening of the first connected nail filling is moderate, thus ensure that the filling effect of the first connected nail, avoid cavity blemish wherein; In addition, described second connected nail is formed by etching after filling the electric conducting material that can etch, and because the width of described groove is comparatively large, ensure that the filling effect of the electric conducting material that can etch, therefore it also avoid the cavity blemish in the second connected nail.
Afterwards, with reference to Figure 18, by described connected nail, described Semiconductor substrate 20 and substrate 40 are docked.In one embodiment, the upper surface 20a of described Semiconductor substrate 20 is formed with transducer, described substrate 40 is formed with control circuit, described control circuit comprises multiple subelement 41, and each subelement after docking in transducer is connected by the subelement 41 that connected nail is corresponding with control circuit.
Continue, with reference to Figure 19, described bearing substrate to be peeled off, exposes the upper surface 20a of described Semiconductor substrate 20.After stripping, can also clean described upper surface 20a.After this, scribing can also be carried out to described Semiconductor substrate 20 and described substrate 40, be cut and split into multiple independently nude film (die).
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (16)
1. wear a through-silicon via structure, it is characterized in that, comprising:
Semiconductor substrate, described Semiconductor substrate is formed with groove, is filled with dielectric layer in described groove;
Run through the connected nail of described Semiconductor substrate and described dielectric layer, described connected nail comprises the first connected nail and the second connected nail that connect up and down, described first connected nail is embedded in described Semiconductor substrate, described second connected nail is embedded in described dielectric layer, and the material of described second connected nail is the electric conducting material that can etch; Described first connected nail and described second connected nail are aimed at up and down, and the width of the second connected nail is equal with the width of the first connected nail.
2. according to claim 1ly wear through-silicon via structure, it is characterized in that, the described electric conducting material etched is selected from aluminium, the polysilicon of doping or the polycrystalline silicon germanium of doping.
3. according to claim 1ly wear through-silicon via structure, it is characterized in that, the material of described dielectric layer is selected from silica, silicon oxynitride or low k dielectric materials.
4. according to claim 1ly wear through-silicon via structure, it is characterized in that, the material of described first connected nail is selected from the polysilicon of copper, tungsten, aluminium or doping.
5. wear a formation method for through-silicon via structure, it is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises relative upper surface and lower surface;
The upper surface of described Semiconductor substrate is etched, forms opening;
Filled conductive material in said opening, forms the first connected nail;
Etch the lower surface of described Semiconductor substrate, form groove, described bottom portion of groove exposes described first connected nail;
In described groove, fill the electric conducting material that can etch, and etch the described electric conducting material etched, form the second connected nail, described second connected nail connects up and down with described first connected nail; Described first connected nail and described second connected nail are aimed at up and down, and the width of the second connected nail is equal with the width of the first connected nail;
Filled media layer in space between described second connected nail and described Semiconductor substrate and the space between the second adjacent connected nail.
6. formation method of wearing through-silicon via structure according to claim 5, is characterized in that, the described electric conducting material etched is selected from aluminium, the polysilicon of doping or the polycrystalline silicon germanium of doping.
7. formation method of wearing through-silicon via structure according to claim 5, is characterized in that, the described electric conducting material etched is aluminium, uses physical vapour deposition (PVD) or chemical vapour deposition (CVD) in described groove, fill the electric conducting material that can etch.
8. formation method of wearing through-silicon via structure according to claim 5, is characterized in that, the material of described dielectric layer is selected from silica, silicon oxynitride or low k dielectric materials.
9. formation method of wearing through-silicon via structure according to claim 5, is characterized in that, after described first connected nail of formation, before forming described groove, also comprises:
The upper surface of described Semiconductor substrate is fixed on bearing substrate;
Carry out thinning to the lower surface of described Semiconductor substrate.
10. formation method of wearing through-silicon via structure according to claim 9, it is characterized in that, before the upper surface of described Semiconductor substrate is fixed on bearing substrate, also comprise: form photoetching alignment mark at the upper surface of described Semiconductor substrate, the degree of depth of described photoetching alignment mark is greater than the degree of depth of described first connected nail.
11. formation methods of wearing through-silicon via structure according to claim 10, is characterized in that, the described lower surface to described Semiconductor substrate carry out thinning after, expose described photoetching alignment mark.
12. formation methods of wearing through-silicon via structure according to claim 9, it is characterized in that, described bearing substrate is silicon substrate or glass substrate.
13. formation methods of wearing through-silicon via structure according to claim 5, it is characterized in that, described electric conducting material is copper, and the described material of filled conductive in said opening, forms the first connected nail and comprise:
Barrier layer and copper seed layer is formed successively in the bottom of described opening and sidewall;
Fill metallic copper in said opening, described metallic copper covers described copper seed layer;
Planarization is carried out, to the upper surface exposing described Semiconductor substrate to the surface of described metallic copper.
14. formation methods of wearing through-silicon via structure according to claim 5, it is characterized in that, described electric conducting material is tungsten or aluminium, uses physical vapour deposition (PVD) or chemical vapour deposition (CVD) filled conductive material in said opening.
15. formation methods of wearing through-silicon via structure according to claim 5, is characterized in that, described electric conducting material is the polysilicon of doping, uses chemical vapour deposition (CVD) filled conductive material in said opening.
16. formation methods of wearing through-silicon via structure according to claim 5, is characterized in that, after the described dielectric layer of formation, also comprise: carry out planarization to the surface of described dielectric layer, to exposing described second connected nail.
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| CN104347492A (en) * | 2013-08-09 | 2015-02-11 | 上海微电子装备有限公司 | Manufacturing methods for through hole structure with high depth-to-width ratio and multi-chip interconnection |
| CN103681390B (en) * | 2013-12-20 | 2016-09-14 | 中国电子科技集团公司第五十八研究所 | A kind of wafer scale silicon substrate preparation method based on TSV technique |
| CN105261590B (en) * | 2015-10-09 | 2017-11-24 | 张家港市东大工业技术研究院 | A kind of method for filling high-aspect-ratio three-dimensional glass through hole |
| CN105870054B (en) * | 2016-06-06 | 2019-05-10 | 上海华虹宏力半导体制造有限公司 | Through-silicon via structure and forming method thereof |
| CN113410175B (en) * | 2021-06-15 | 2023-06-02 | 西安微电子技术研究所 | TSV conductive through hole structure preparation method |
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| CN1909208A (en) * | 2005-08-02 | 2007-02-07 | 奇梦达股份公司 | Method of manufacturing a semiconductor structure and a corresponding semiconductor structure |
| CN101553903A (en) * | 2006-10-17 | 2009-10-07 | 丘费尔资产股份有限公司 | Wafer via formation |
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| CN102683308A (en) | 2012-09-19 |
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