CN102683308A - Through-silicon-vias structure and formation method thereof - Google Patents
Through-silicon-vias structure and formation method thereof Download PDFInfo
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Abstract
The invention relates to a through-silicon-vias structure and a formation method thereof. The formation method includes that a semiconductor substrate is provided, the semiconductor substrate includes an upper surface and a lower surface which are opposite to each other, the upper surface of the semiconductor substrate is subjected to an etching to form an opening, a conducting material is filled in the opening to form first connecting pegs, the lower surface of the semiconductor substrate is subjected to the etching to form a groove, the first connecting pegs are exposed at the bottom of the groove, a conducting material which is capable of being etched is filled in the groove, the conducting material which is capable of being etched is subjected to the etching to form second connecting pegs, each of the second connecting pegs is vertically connected with each of the first connecting pegs, and dielectric layers are filled gaps between the second connecting pegs and the semiconductor substrate and gaps between adjacent second connecting pegs. The through-silicon-vias structure and the formation method thereof have the advantages that the reliability of the through-silicon-vias structure is improved, and the cavity defect is prevented.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of through-silicon via structure and forming method thereof of wearing.
Background technology
3D encapsulation is encapsulated in two or more integrated circuit vertical stacking in the same chip, thereby can reduce occupation space, in the 3D encapsulation substrate of bearing integrated commonly used often have the through-silicon via structure of wearing (TSV, Through-Silicon-Vias).Wear through-silicon via structure through employing and replace traditional edge line and carry out 3D encapsulation, can be in a little device package (footprint) integrated more logic function.In addition, employing is worn through-silicon via structure and can effectively be shortened critical path (critical path), reduces to postpone, and improves device speed.
Wearing through-silicon via structure mainly is on Semiconductor substrate, to form the through hole that runs through; And filling forms connected nail (nail) therein; Link to each other with interconnection structure on another wafer or another chip through connected nail afterwards and realize the 3D encapsulation; Its formation method has multiple, comprising: wear the through-silicon via structure precedence method, before forming circuit, at first form and wear through-silicon via structure; Mid-term, the through-silicon via structure method was worn in formation, after the preceding road of completion technology (form device after), carry out postchannel process before (forming before the interconnection structure) form and wear through-silicon via structure; The back forms the through-silicon via structure method of wearing, and after forming circuit, promptly forms the formation afterwards of device and interconnection structure and wears through-silicon via structure; Form the through-silicon via structure method of wearing behind the bonding, forming the through-silicon via structure method of wearing with two wafers or after a wafer and chip piece bonding.
The through-silicon via structure of wearing of prior art is based on mainly that copper wiring technique forms, the profile of the intermediate structure of a kind of formation method of wearing through-silicon via structure that Fig. 1 to Fig. 5 shows prior art.
With reference to figure 1, Semiconductor substrate 10 is provided, can be formed with semiconductor device on the said Semiconductor substrate 10, like MOS transistor, also can be formed with semiconductor device and interconnection structure, perhaps also can not comprise semiconductor device and interconnection structure.
With reference to figure 2, the upper surface of said Semiconductor substrate 10 is carried out etching, form opening 11.
With reference to figure 3; Form barrier layer 12; Cover the upper surface of bottom, sidewall and the said Semiconductor substrate 10 of said opening; On said barrier layer 12, form metallic copper 13 afterwards, fill said opening, on the surface that also is included in said barrier layer 12 before the formation metallic copper 13, form inculating crystal layer (seedlayer) through galvanoplastic.
With reference to figure 4, planarization is carried out on the metallic copper and the barrier layer 12 that cover on the Semiconductor substrate 10, to the upper surface that exposes said Semiconductor substrate 10, form connected nail 13a.
With reference to figure 5, from the lower surface of said Semiconductor substrate 10 it is carried out attenuate, to exposing said connected nail 13a, make said opening become the through hole that runs through whole Semiconductor substrate 10, accomplish the forming process of wearing through-silicon via structure.
No matter be to adopt to wear that through-silicon via structure precedence method, mid-term form the through-silicon via structure method of wearing, the back forms the through-silicon via structure method of wearing after forming and wearing through-silicon via structure method or bonding, based on the filling problem that is metallic copper of a bigger challenge in the forming process of wearing through-silicon via structure of copper wiring technique.For example; In such as application such as MEMSs (MEMS, Micro-electromechanical System), transducer need link to each other with control circuit; Can said transducer be produced in different Semiconductor substrate respectively with control circuit; And adopt and to wear through-silicon via structure with each subelement in the transducer and corresponding linking to each other of each subelement in the control unit, thereby simplified design and production process, the raising yield.
But this type application often need form the highdensity through-silicon via structure of wearing on Semiconductor substrate, promptly in unit are, forms the through-silicon via structure of wearing of greater number.In order to satisfy the demand of density; The diameter of wearing through-silicon via structure must become very little; But in order to guarantee the mechanical strength of Semiconductor substrate itself, the thickness of Semiconductor substrate needs enough big simultaneously, and this just causes the depth-to-width ratio (aspect ratio) of wearing the silicon through hole to become very big.Continuous increase along with the depth-to-width ratio of wearing through hole in the through-silicon via structure; Particularly depth-to-width ratio was greater than 10: 1 o'clock; Form continuous barrier layer and inculating crystal layer and become very difficult; The discontinuous meeting of barrier layer and inculating crystal layer causes electroplating filling in the connected nail that the back forms and cavity blemish (void) occurs, makes reliability decrease, even might cause the problem that opens circuit.
Describe in detail about wearing the more of through-silicon via structure, please refer to the patent No. is 7,683,459 and 7,633,165 United States Patent (USP) more.
Summary of the invention
The problem that the present invention solves is along with depth-to-width ratio increases, based on the problem of wearing the through-silicon via structure reliability decrease of copper wiring technique in the prior art.
For addressing the above problem, the invention provides a kind of through-silicon via structure of wearing, comprising:
Semiconductor substrate is formed with groove on the said Semiconductor substrate, is filled with dielectric layer in the said groove;
The connected nail that runs through said Semiconductor substrate and said dielectric layer; Said connected nail comprises first connected nail and second connected nail that joins up and down; Said first connected nail is embedded in the said Semiconductor substrate; Said second connected nail is embedded in the said dielectric layer, but the material of said second connected nail is the electric conducting material of etching.
Alternatively, but the electric conducting material of said etching is selected from the polysilicon of aluminium, doping or the polycrystalline silicon germanium of doping.
Alternatively, the material of said dielectric layer is selected from silica, silicon oxynitride or low k dielectric material.
Alternatively, the material of said first connected nail is selected from the polysilicon of copper, tungsten, aluminium or doping.
The present invention also provides a kind of formation method of wearing through-silicon via structure, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises relative upper surface and lower surface;
Upper surface to said Semiconductor substrate carries out etching, forms opening;
Filled conductive material in said opening forms first connected nail;
Lower surface to said Semiconductor substrate carries out etching, forms groove, and said bottom portion of groove exposes said first connected nail;
But in said groove, fill the electric conducting material of etching, but and the electric conducting material of said etching carried out etching, form second connected nail, said second connected nail and said first connected nail join up and down;
Fill dielectric layer in the space between space between said second connected nail and said Semiconductor substrate and the second adjacent connected nail.
Alternatively, but the electric conducting material of said etching is selected from the polysilicon of aluminium, doping or the polycrystalline silicon germanium of doping.
Alternatively, but the electric conducting material of said etching is an aluminium, but uses physical vapour deposition (PVD) or chemical vapour deposition (CVD) in said groove, to fill the electric conducting material of etching.
Alternatively, the material of said dielectric layer is selected from silica, silicon oxynitride or low k dielectric material.
Alternatively, after forming said first connected nail, form before the said groove, said formation method also comprises:
The upper surface of said Semiconductor substrate is fixed on the bearing substrate;
Lower surface to said Semiconductor substrate carries out attenuate.
Alternatively; Before the upper surface with said Semiconductor substrate is fixed on the bearing substrate; Said formation method also comprises: the upper surface in said Semiconductor substrate forms photoetching alignment mark (lithographyalignment mark), and the degree of depth of said photoetching alignment mark is greater than the degree of depth of said first connected nail.
Alternatively, said lower surface to said Semiconductor substrate carries out exposing said photoetching alignment mark after the attenuate.
Alternatively, said bearing substrate is silicon substrate or glass substrate.
Alternatively, said electric conducting material is a copper, said in said opening the filled conductive material, form first connected nail and comprise:
Bottom and sidewall at said opening form barrier layer and copper seed layer successively;
In said opening, fill metallic copper, said metallic copper covers said copper seed layer;
Planarization is carried out on surface to said metallic copper, to the upper surface that exposes said Semiconductor substrate.
Alternatively, said electric conducting material is tungsten or aluminium, uses physical vapor deposition (PVD) or chemical vapor deposition (CVD) filled conductive material in said opening.
Alternatively, the polysilicon of said electric conducting material for mixing uses chemical vapour deposition (CVD) filled conductive material in said opening.
Alternatively, after forming said dielectric layer, said formation method also comprises: planarization is carried out on the surface to said dielectric layer, to exposing said second connected nail.
Compared with prior art, embodiments of the invention have following advantage:
In the formation method of wearing through-silicon via structure of the embodiment of the invention; At first form the opening of depth-to-width ratio appropriateness at the upper surface of Semiconductor substrate; And fill formation first connected nail therein, usually, the depth-to-width ratio of said opening is selected comparatively moderate numerical value; To improve the filling effect of said first connected nail, avoid wherein occurring problems such as cavity blemish; Lower surface in said Semiconductor substrate forms groove afterwards; But in said groove, fill the electric conducting material of etching and it is carried out forming second connected nail after the etching; Usually, can form the bigger groove of width, promptly said groove has less depth-to-width ratio; But with the filling effect of the electric conducting material that improves said etching, thereby the cavity blemish problem in second connected nail of avoiding forming through etching.Therefore, present embodiment forms wears through-silicon via structure and can when having big depth-to-width ratio, also have higher reliability.
Description of drawings
Fig. 1 to Fig. 5 is a kind of cross-sectional view of wearing the formation method of through-silicon via structure of prior art;
Fig. 6 is the schematic flow sheet of the embodiment of the present invention's formation method of wearing through-silicon via structure;
Fig. 7 to Figure 19 is the cross-sectional view of the embodiment of the present invention's formation method of wearing through-silicon via structure.
Embodiment
The method that through-silicon via structure is worn in formation in the prior art is mainly based on copper wiring technique; Along with the increase of wearing through-silicon via structure density; Its depth-to-width ratio also increases accordingly, causes copper diffusion barrier layer and copper seed layer possibly can't cover the inner surface of through hole fully, thereby produces cavity blemish in the connected nail that makes plating filling back form; Cause wearing the reliability decrease of through-silicon via structure, even the problem that opens circuit occurs.
In the formation method of wearing through-silicon via structure of the embodiment of the invention; At first form the opening of depth-to-width ratio appropriateness at the upper surface of Semiconductor substrate; And fill formation first connected nail therein, usually, the depth-to-width ratio of said opening is selected comparatively moderate numerical value; To improve the filling effect of said first connected nail, avoid wherein occurring problems such as cavity blemish; Lower surface in said Semiconductor substrate forms groove afterwards; But in said groove, fill the electric conducting material of etching and it is carried out forming second connected nail after the etching; Usually, can form the bigger groove of width, promptly said groove has less depth-to-width ratio; But with the filling effect of the electric conducting material that improves said etching, thereby the cavity blemish problem in second connected nail of avoiding forming through etching.Therefore, present embodiment forms wears through-silicon via structure and can when having big depth-to-width ratio, also have higher reliability.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed embodiment.
Fig. 6 shows the schematic flow sheet of the embodiment of formation method of wearing through-silicon via structure of the present invention, comprising:
Step S21 provides Semiconductor substrate, and said Semiconductor substrate comprises relative upper surface and lower surface;
Step S22 carries out etching to the upper surface of said Semiconductor substrate, forms opening;
Step S23, filled conductive material in said opening forms first connected nail;
Step S24 carries out etching to the lower surface of said Semiconductor substrate, forms groove, and said bottom portion of groove exposes said first connected nail;
Step S25, but in said groove, fill the electric conducting material of etching, but and the electric conducting material of said etching carried out etching, form second connected nail, said second connected nail and said first connected nail join up and down;
Step S26 fills dielectric layer in the space between space between said second connected nail and said Semiconductor substrate and the second adjacent connected nail.
Fig. 7 to Figure 19 shows the generalized section of the embodiment of formation method of wearing through-silicon via structure of the present invention, below in conjunction with Fig. 6 and Fig. 7 to Figure 19 first embodiment is elaborated.
In conjunction with Fig. 6 and Fig. 7, execution in step S21 provides Semiconductor substrate 20, and said Semiconductor substrate 20 comprises relative upper surface 20a and lower surface 20b.Particularly, said Semiconductor substrate 20 can be silicon substrate, germanium silicon substrate, III-V group element compound substrate, silicon carbide substrates or its laminated construction, or silicon on insulated substrate, or well known to a person skilled in the art other semiconductive material substrate.In the present embodiment, said Semiconductor substrate 20 is a silicon substrate, wherein can be formed with transducer or control circuit etc., also can be blank silicon substrate.
In conjunction with Fig. 6 and Fig. 8, execution in step S22 carries out etching to the upper surface 20a of said Semiconductor substrate 20, forms opening 20c.As an example, the number of the opening 20c that forms among Fig. 8 is 3.The forming process of said opening 20c can comprise: on the upper surface 20a of said Semiconductor substrate 20, form photoresist layer and graphical, define the figure of said opening 20c; Being mask with said photoresist layer after graphical carries out etching to the upper surface 20a of said Semiconductor substrate 20, forms said opening 20c; Remove said photoresist layer after graphical.
Need to prove; Said opening 20c does not penetrate said Semiconductor substrate 20; Its width equals to expect the width of wearing the link nail in the through-silicon via structure that forms; The material of first connected nail that the degree of depth of said opening 20c is formed by follow-up filling and technology decision, the depth-to-width ratio that is to say said opening 20c need guarantee the filling effect of first connected nail that technologies such as the conventional CVD of following adopted, plating form, and prevents wherein to occur cavity blemish.
In conjunction with Fig. 6 and Figure 10, execution in step S23, filled conductive material 23 in said opening forms first connected nail.Said electric conducting material 23 is selected from the polysilicon of copper, tungsten, aluminium or doping.In the present embodiment, said electric conducting material 23 is a copper, and said first connected nail comprises the barrier layer 21 and copper seed layer 22 that is formed at said opening sidewalls and bottom successively.Specify the forming process of said first connected nail below with reference to figure 9 and Figure 10.
At first with reference to figure 9, form barrier layer 21 and copper seed layer 22 successively at the bottom and the sidewall of said opening, barrier layer described in the present embodiment 21 and copper seed layer 22 also cover the upper surface 20a of said Semiconductor substrate 20.The material on said barrier layer 21 can be Ta, TaN etc., and the formation method of said barrier layer 21 and copper seed layer 22 can be PVD.
With reference to Figure 10, filled conductive material 23 is specially metallic copper in said opening afterwards, and said metallic copper covers said copper seed layer 22; Planarization is carried out on surface to said metallic copper after filling, like chemico-mechanical polishing (CMP), to the upper surface 20a that exposes said Semiconductor substrate 20.
In other specific embodiments, said electric conducting material 23 also can be tungsten or aluminium, and its fill method is PVD or CVD; Said electric conducting material 23 can also be the polysilicon that mixes, and its fill method is CVD, and the method that can use original position (in-situ) to mix is introduced dopant ion in polysilicon.
In conjunction with Fig. 6 and Figure 14, execution in step S24 carries out etching to the lower surface 20b of said Semiconductor substrate 20, forms groove 25, and said groove 25 bottom-exposed go out said first connected nail.Specify with reference to figures 11 to Figure 14 below.
At first with reference to Figure 11; Upper surface 20a in said Semiconductor substrate 20 forms photoetching alignment mark 24; The degree of depth of said photoetching alignment mark 24 is greater than the degree of depth of said first connected nail; Promptly greater than the degree of depth of said opening, more specifically, the degree of depth of said photoetching alignment mark 24 is more than or equal to the degree of depth of wearing the connected nail in the through-silicon via structure of expection formation.Said photoetching alignment mark 24 can be formed in the groove of said upper surface 20a, also can be to form the medium or the metal material of filling therein behind the groove.
Afterwards with reference to Figure 12, the upper surface 20a of said Semiconductor substrate 20 is fixed on the bearing substrate 30.Said bearing substrate 30 can be silicon substrate, glass substrate etc.Fixed method can be bonding, bonding etc.
Afterwards with reference to Figure 13, the lower surface 20b of said Semiconductor substrate 20 is carried out attenuate, the thickness that is thinned to remaining Semiconductor substrate 20 can satisfy in the practical application requirement to mechanical strength.Behind the attenuate, the lower surface 20b of said Semiconductor substrate 20 exposes said photoetching alignment mark 24.
Afterwards with reference to Figure 14, with said Semiconductor substrate 20 and said bearing substrate 30 upsets, the lower surface 20b of said Semiconductor substrate 20 is carried out etching, form groove 25.The bottom-exposed of said groove 25 goes out said first connected nail, is specially in the present embodiment to expose said barrier layer 21.The width of said groove 25 needs enough wide, but with the filling effect of the electric conducting material that guarantees follow-up etching.In the present embodiment, before covering, the width range of said groove 25 is formed on the scope of whole first connected nails of upper surface 20a.The forming process of said groove 25 can comprise photoetching, etching etc.
In conjunction with Fig. 6, Figure 15 and Figure 16; Execution in step S25, but in said groove, fill the electric conducting material 26 of etching, but and the electric conducting material 26 of said etching carried out etching; Form the second connected nail 26a, said second connected nail 26a and said first connected nail join up and down.Concrete, in the present embodiment, said second connected nail 26a and said barrier layer 21 join.
But the electric conducting material 26 of said etching is selected from the polysilicon of aluminium, doping or the polycrystalline silicon germanium of doping.In the present embodiment, but the electric conducting material 26 of said etching is preferably aluminium, and its fill method is PVD or CVD.
But can carry out graphically through the electric conducting material 26 of technologies such as photoetching, etching to said etching, thereby form the second connected nail 26a, each second connected nail 26a joins up and down with corresponding first connected nail in position respectively.Can aim at through said photoetching alignment mark 24 in the said patterned process, so that the position of the second connected nail 26a that etching forms can be corresponding with the position of first connected nail that is formed at upper surface 20a.
Need to prove; When but the electric conducting material 26 to said etching carries out etching; Need but the electric conducting material of said etching is worn for 26 quarters, the bottom-exposed in the space that promptly forms after the etching goes out said Semiconductor substrate 20, and is respectively insulated from each other between second connected nail 26a to guarantee that etching forms.
In conjunction with Fig. 6 and Figure 17, execution in step S26, dielectric layer 27 is filled in the space between the space between said second connected nail 26a and the said Semiconductor substrate 20 and the adjacent second connected nail 26a.The material of said dielectric layer 27 is selected from silica, silicon oxynitride or low k dielectric material, and its formation method can be CVD.Form in the process of said dielectric layer 27 in filling, the dielectric layer 27 of formation can cover the surface of the said second connected nail 26a, therefore afterwards can also carry out planarization to the surface of said dielectric layer 27, to exposing the said second connected nail 26a.Flattening method to said dielectric layer 27 can be chemico-mechanical polishing or selective etch etc.
So far, the through-silicon via structure of wearing that present embodiment forms can comprise with reference to Figure 17: Semiconductor substrate 20, be formed with groove on the said Semiconductor substrate 20, and be filled with dielectric layer 27 in the said groove; The connected nail that runs through said Semiconductor substrate 20 and said dielectric layer 27; Said connected nail comprises first connected nail (specifically comprising barrier layer 21, copper seed layer 22 and metallic copper 23 in the present embodiment) and the second connected nail 26a that joins up and down; Wherein, First connected nail is embedded in the said Semiconductor substrate 20, and said second connected nail is embedded in the said dielectric layer 27, but the material of said second connected nail is the electric conducting material of etching.
The through-silicon via structure of wearing in the present embodiment is made up of first connected nail that is respectively formed at upper surface and second connected nail that is formed on lower surface.Because the depth-to-width ratio of the opening that first connected nail is filled is moderate, thereby has guaranteed the filling effect of first connected nail, avoided cavity blemish wherein; In addition, but said second connected nail is to form through etching behind the electric conducting material of filling etching, because the width of said groove is bigger, but has guaranteed the filling effect of the electric conducting material of etching, has therefore also avoided the cavity blemish in second connected nail.
Afterwards, with reference to Figure 18, through said connected nail, with said Semiconductor substrate 20 and substrate 40 butt joints.In one embodiment; Be formed with transducer on the upper surface 20a of said Semiconductor substrate 20; Be formed with control circuit on the said substrate 40; Said control circuit comprises a plurality of subelements 41, and each subelement in the transducer of butt joint back is connected through corresponding subelement 41 in connected nail and the control circuit.
Continuation is peeled off said bearing substrate with reference to Figure 19, exposes the upper surface 20a of said Semiconductor substrate 20.After peeling off, can also clean said upper surface 20a.After this, can also carry out scribing with said substrate 40, its cutting is split into a plurality of independently nude films (die) said Semiconductor substrate 20.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (16)
1. wear through-silicon via structure for one kind, it is characterized in that, comprising:
Semiconductor substrate is formed with groove on the said Semiconductor substrate, is filled with dielectric layer in the said groove;
The connected nail that runs through said Semiconductor substrate and said dielectric layer; Said connected nail comprises first connected nail and second connected nail that joins up and down; Said first connected nail is embedded in the said Semiconductor substrate; Said second connected nail is embedded in the said dielectric layer, but the material of said second connected nail is the electric conducting material of etching.
2. the through-silicon via structure of wearing according to claim 1 is characterized in that, but the electric conducting material of said etching is selected from the polysilicon of aluminium, doping or the polycrystalline silicon germanium of doping.
3. the through-silicon via structure of wearing according to claim 1 is characterized in that the material of said dielectric layer is selected from silica, silicon oxynitride or low k dielectric material.
4. the through-silicon via structure of wearing according to claim 1 is characterized in that the material of said first connected nail is selected from the polysilicon of copper, tungsten, aluminium or doping.
5. a formation method of wearing through-silicon via structure is characterized in that, comprising:
Semiconductor substrate is provided, and said Semiconductor substrate comprises relative upper surface and lower surface;
Upper surface to said Semiconductor substrate carries out etching, forms opening;
Filled conductive material in said opening forms first connected nail;
Lower surface to said Semiconductor substrate carries out etching, forms groove, and said bottom portion of groove exposes said first connected nail;
But in said groove, fill the electric conducting material of etching, but and the electric conducting material of said etching carried out etching, form second connected nail, said second connected nail and said first connected nail join up and down;
Fill dielectric layer in the space between space between said second connected nail and said Semiconductor substrate and the second adjacent connected nail.
6. formation method of wearing through-silicon via structure according to claim 5 is characterized in that, but the electric conducting material of said etching is selected from the polysilicon of aluminium, doping or the polycrystalline silicon germanium of doping.
7. formation method of wearing through-silicon via structure according to claim 5 is characterized in that, but the electric conducting material of said etching is an aluminium, but uses physical vapour deposition (PVD) or chemical vapour deposition (CVD) in said groove, to fill the electric conducting material of etching.
8. formation method of wearing through-silicon via structure according to claim 5 is characterized in that the material of said dielectric layer is selected from silica, silicon oxynitride or low k dielectric material.
9. formation method of wearing through-silicon via structure according to claim 5 is characterized in that, after forming said first connected nail, forms before the said groove, also comprises:
The upper surface of said Semiconductor substrate is fixed on the bearing substrate;
Lower surface to said Semiconductor substrate carries out attenuate.
10. formation method of wearing through-silicon via structure according to claim 9; It is characterized in that; Before the upper surface with said Semiconductor substrate is fixed on the bearing substrate; Also comprise: the upper surface in said Semiconductor substrate forms photoetching alignment mark, and the degree of depth of said photoetching alignment mark is greater than the degree of depth of said first connected nail.
11. formation method of wearing through-silicon via structure according to claim 10 is characterized in that, said lower surface to said Semiconductor substrate carries out exposing said photoetching alignment mark after the attenuate.
12. formation method of wearing through-silicon via structure according to claim 9 is characterized in that said bearing substrate is silicon substrate or glass substrate.
13. formation method of wearing through-silicon via structure according to claim 5 is characterized in that said electric conducting material is a copper, said in said opening the filled conductive material, form first connected nail and comprise:
Bottom and sidewall at said opening form barrier layer and copper seed layer successively;
In said opening, fill metallic copper, said metallic copper covers said copper seed layer;
Planarization is carried out on surface to said metallic copper, to the upper surface that exposes said Semiconductor substrate.
14. formation method of wearing through-silicon via structure according to claim 5 is characterized in that said electric conducting material is tungsten or aluminium, uses physical vapour deposition (PVD) or chemical vapour deposition (CVD) filled conductive material in said opening.
15. formation method of wearing through-silicon via structure according to claim 5 is characterized in that, the polysilicon of said electric conducting material for mixing uses chemical vapour deposition (CVD) filled conductive material in said opening.
16. formation method of wearing through-silicon via structure according to claim 5 is characterized in that, after forming said dielectric layer, also comprise: planarization is carried out on the surface to said dielectric layer, to exposing said second connected nail.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258788A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Through hole interconnection structure manufacturing method based on bidirectional filling and through hole interconnection structure product |
| CN103681390A (en) * | 2013-12-20 | 2014-03-26 | 中国电子科技集团公司第五十八研究所 | TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate |
| CN104347492A (en) * | 2013-08-09 | 2015-02-11 | 上海微电子装备有限公司 | Manufacturing methods for through hole structure with high depth-to-width ratio and multi-chip interconnection |
| CN105261590A (en) * | 2015-10-09 | 2016-01-20 | 张家港市东大工业技术研究院 | Method for filling three-dimensional glass through hole with high aspect ratio |
| CN105870054A (en) * | 2016-06-06 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Through-silicon-hole structure and formation method thereof |
| CN113410175A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Preparation method of TSV (through silicon Via) conductive through hole structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1909208A (en) * | 2005-08-02 | 2007-02-07 | 奇梦达股份公司 | Method of manufacturing a semiconductor structure and a corresponding semiconductor structure |
| CN101553903A (en) * | 2006-10-17 | 2009-10-07 | 丘费尔资产股份有限公司 | Wafer via formation |
| US20100264548A1 (en) * | 2009-04-16 | 2010-10-21 | Freescale Semiconductor, Inc. | Through substrate vias |
-
2011
- 2011-03-11 CN CN201110059582.7A patent/CN102683308B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1909208A (en) * | 2005-08-02 | 2007-02-07 | 奇梦达股份公司 | Method of manufacturing a semiconductor structure and a corresponding semiconductor structure |
| CN101553903A (en) * | 2006-10-17 | 2009-10-07 | 丘费尔资产股份有限公司 | Wafer via formation |
| US20100264548A1 (en) * | 2009-04-16 | 2010-10-21 | Freescale Semiconductor, Inc. | Through substrate vias |
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| CN103258788A (en) * | 2013-04-17 | 2013-08-21 | 华中科技大学 | Through hole interconnection structure manufacturing method based on bidirectional filling and through hole interconnection structure product |
| CN103258788B (en) * | 2013-04-17 | 2015-09-23 | 华中科技大学 | Based on the through hole interconnect architecture manufacture method and products thereof of two-way filling |
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| CN103681390A (en) * | 2013-12-20 | 2014-03-26 | 中国电子科技集团公司第五十八研究所 | TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate |
| CN103681390B (en) * | 2013-12-20 | 2016-09-14 | 中国电子科技集团公司第五十八研究所 | A kind of wafer scale silicon substrate preparation method based on TSV technique |
| CN105261590A (en) * | 2015-10-09 | 2016-01-20 | 张家港市东大工业技术研究院 | Method for filling three-dimensional glass through hole with high aspect ratio |
| CN105261590B (en) * | 2015-10-09 | 2017-11-24 | 张家港市东大工业技术研究院 | A kind of method for filling high-aspect-ratio three-dimensional glass through hole |
| CN105870054A (en) * | 2016-06-06 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Through-silicon-hole structure and formation method thereof |
| CN113410175A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Preparation method of TSV (through silicon Via) conductive through hole structure |
| CN113410175B (en) * | 2021-06-15 | 2023-06-02 | 西安微电子技术研究所 | TSV conductive through hole structure preparation method |
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