CN107527802A - Groove type double-layer grid MOS film build methods - Google Patents
Groove type double-layer grid MOS film build methods Download PDFInfo
- Publication number
- CN107527802A CN107527802A CN201710695128.8A CN201710695128A CN107527802A CN 107527802 A CN107527802 A CN 107527802A CN 201710695128 A CN201710695128 A CN 201710695128A CN 107527802 A CN107527802 A CN 107527802A
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- China
- Prior art keywords
- layer
- polysilicon
- etching
- type double
- boron
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- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000011521 glass Substances 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000002347 injection Methods 0.000 claims abstract description 5
- 239000007924 injection Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000005368 silicate glass Substances 0.000 claims description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 32
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
The invention discloses a kind of groove type double-layer grid MOS film build methods, comprising：1st step, oxidation film layer and hard mask layer are formed on a silicon substrate, graphical to open etching groove window, etching forms groove；Sacrificial oxide layer is deposited after groove chamfering processing；2nd step, cushion oxide layer is deposited, then depositing polysilicon and time quarter, be then coated with photoresist, again polysilicon performed etching to form polysilicon source after patterning definition；3rd step, carry out thermal oxide and form dielectric oxide, then dielectric oxide carve, depositing polysilicon simultaneously time forms polysilicon gate at quarter；Deposited oxide layer, depositing polysilicon simultaneously carry out back forming Electro-static Driven Comb structure quarter under the definition of photoresist to polysilicon；4th step, the injection of body area and source region is carried out, deposited oxide layer, deposits boron-phosphorosilicate glass, carrying out wet method to boron-phosphorosilicate glass and oxide layer returns quarter；Contact hole photoetching and etching, deposit metal.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of groove type double-layer grid MOS film build methods.
Background technology
In groove type double-layer gate MOSFET, layer connects film and put down by reflow rather than CMP (cmp) completions surface
Smoothization.
In the product with ESD structures, the situation of grid/source short circuit occurs in wafer peripheral, aobvious by being analyzed under microscope
Show that connecing film edge in layer has metal residual.
Further it is analyzed to identify, because ESD interfaces are more straight, tungsten residual is formed after layer connects film.The tungsten of residual result in
State problem.
Above mentioned problem is based on current technique：After groove is formed, deposit cushion oxide layer, then depositing polysilicon and return
Carve, be then coated with photoresist, again polysilicon performed etching to form polysilicon source after patterning definition；Thermal oxide is carried out to be formed
Thermal oxide layer, then to thermal oxide layer carry out back carve, depositing polysilicon and return form polysilicon gate at quarter；Form glassy silicate
Glass, depositing polysilicon simultaneously carry out back forming Electro-static Driven Comb structure quarter under the definition of photoresist to polysilicon；Carry out body area and source
The injection in area, silicate glass is formed again, deposit boron-phosphorosilicate glass, silicate glass and boron-phosphorosilicate glass and oxide layer are entered
Go back quarter；The subsequent technique such as contact hole photoetching and etching, deposit metal is completed.The technique mainly in later stage silicate glass and
B/P parameter optimization obtains not good enough in the thickness and boron-phosphorosilicate glass of the interlayer film (inter-level dielectric) that boron-phosphorosilicate glass is formed,
Cause the surface flatness in later stage inadequate, interlayer film caliper uniformity is not good enough, easily forms the tungsten metal derby of residual.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of groove type double-layer grid MOS film build methods.
To solve the above problems, groove type double-layer grid MOS film build methods of the present invention：Comprising：
1st step, oxidation film layer and hard mask layer are formed on a silicon substrate, it is graphical to open etching groove window, etch shape
Into groove；Groove chamfering processing；
2nd step, cushion oxide layer is deposited, then depositing polysilicon and time quarter, photoresist is then coated with, after patterning definition
Again polysilicon is performed etching to form polysilicon source；
3rd step, carry out thermal oxide and form thermal oxide layer, then thermal oxide layer carve；
4th step, depositing polysilicon and return form polysilicon gate at quarter；Form silicate glass, depositing polysilicon and in light
Polysilicon is carried out back under the definition of photoresist to form Electro-static Driven Comb structure quarter；
Carry out the injection of body area and source region, form silicate glass again, deposit boron-phosphorosilicate glass, to silicate glass and
Boron-phosphorosilicate glass and oxide layer carve；Contact hole photoetching and etching, deposit metal.
Further, in the 2nd step, cushion oxide layer is ONO composite beds, i.e., comprising oxide-film, nitride film, oxide-film
Three layers of sandwich structure.
Further, in the 3rd step, thermal oxide layer returns carving technology and uses wet etching.
Further, in the 4th step, the thickness of the silicate glass formed again is Boron phosphorus silicon
The thickness of glass is
Further, in the boron-phosphorosilicate glass, boron, the molar ratio of phosphorus are:(9.8±0.3)/(5.4±0.3).
Further, in the 4th step, silicate glass and boron-phosphorosilicate glass form inter-level dielectric, return carving technology and use
Wet etching, finally inter-level dielectric thickness is after etching
Further, in the 4th step, the formation of boron-phosphorosilicate glass is the time 30 under 950~1000 DEG C of oxygen atmosphere
Minute.
In 4th step, contact hole etching depth is 0.3~0.4 μm.
Groove type double-layer grid MOS film build methods of the present invention, in the thickness and boron-phosphorosilicate glass by optimizing interlayer film
The molar ratio of boron and phosphorus, improve surface flatness, avoid the problem of tungsten remains.
Brief description of the drawings
Fig. 1~4 are present invention process block diagrams.
Fig. 5 is present invention process flow chart.
Description of reference numerals
1 is hard mask, and 2 be oxide-film, and 3 be ONO layer, and 4 be polysilicon, and 5 be thermal oxide layer, and 6 be contact hole, and 7 be boron phosphorus
Silica glass.
Embodiment
Groove type double-layer grid MOS film build methods of the present invention：Include following processing step：
1st step, oxidation film layer and hard mask layer are formed on a silicon substrate, it is graphical to open etching groove window, etch shape
Into groove；Groove chamfering processing.
2nd step, cushion oxide layer is deposited, cushion oxide layer is ONO composite beds, i.e., comprising oxide-film, nitride film, oxide-film
Three layers of sandwich structure.Then depositing polysilicon and time quarter, photoresist is then coated with, polysilicon is entered again after patterning definition
Row etching forms polysilicon source.
3rd step, carry out thermal oxide and form thermal oxide layer, then carrying out wet method to thermal oxide layer returns quarter.
4th step, depositing polysilicon and return form polysilicon gate at quarter；Form silicate glass, depositing polysilicon and in light
Polysilicon is carried out back under the definition of photoresist to form Electro-static Driven Comb structure quarter.
The injection of body area and source region is carried out, forms silicate glass again, thickness isSuch as950~1000 DEG C of oxygen atmosphere, under conditions of 30 minutes time deposit B/P molar ratio 9.8/5.4 boron
Phosphorosilicate glass, thickness areFor example the present embodiment selects medianTo silicate glass and boron phosphorus silicon
Glass carries out wet method and returns quarter；Contact hole photoetching and etching, contact hole etching depth are 0.3~.4 μm, such as 0.35 μm, deposit gold
Category.Technique is completed.
The preferred embodiments of the present invention are these are only, are not intended to limit the present invention.Come for those skilled in the art
Say, the present invention there can be various modifications and variations.Within the spirit and principles of the invention, it is any modification for being made, equivalent
Replace, improve etc., it should be included in the scope of the protection.
Claims (8)
- A kind of 1. groove type double-layer grid MOS film build methods, it is characterised in that：Comprising：1st step, oxidation film layer and hard mask layer are formed on a silicon substrate, graphical to open etching groove window, etching forms ditch Groove；Groove chamfering processing；2nd step, cushion oxide layer is deposited, then depositing polysilicon and time quarter, be then coated with photoresist, it is right again after patterning definition Polysilicon performs etching to form polysilicon source；3rd step, carry out thermal oxide and form thermal oxide layer, then thermal oxide layer carve；4th step, depositing polysilicon and return form polysilicon gate at quarter；Form silicate glass, depositing polysilicon and in photoresist Definition under polysilicon is carried out back to form Electro-static Driven Comb structure quarter；The injection of body area and source region is carried out, forms silicate glass again, boron-phosphorosilicate glass is deposited, to silicate glass and boron phosphorus Silica glass carve；Contact hole lithographic definition and etching, deposit metal.
- 2. groove type double-layer grid MOS film build methods as claimed in claim 1, it is characterised in that：In 2nd step, oxygen is padded Change layer is ONO composite beds, i.e., comprising oxide-film, nitride film, three layers of oxide-film sandwich structure.
- 3. groove type double-layer grid MOS film build methods as claimed in claim 1, it is characterised in that：In 3rd step, thermal oxide Layer returns carving technology and uses wet etching.
- 4. groove type double-layer grid MOS film build methods as claimed in claim 1, it is characterised in that：In 4th step, shape again Into the thickness of silicate glass be 1200~2000, the thickness of boron-phosphorosilicate glass is 8000~10000.
- 5. groove type double-layer grid MOS film build methods as claimed in claim 4, it is characterised in that：In the boron-phosphorosilicate glass, Boron, the molar ratio of phosphorus are（9.8±0.3）/（5.4±0.3）.
- 6. groove type double-layer grid MOS film build methods as claimed in claim 1, it is characterised in that：In 4th step, silicate Glass and boron-phosphorosilicate glass form inter-level dielectric, return carving technology and use wet etching, and inter-level dielectric thickness is after final etching 5000~6000.
- 7. groove type double-layer grid MOS film build methods as claimed in claim 1, it is characterised in that：In 4th step, boron phosphorus silicon The formation of glass is the 30 minutes time under 950~1000 DEG C of oxygen atmosphere.
- 8. groove type double-layer grid MOS film build methods as claimed in claim 1, it is characterised in that：In 4th step, contact hole Etching depth is 0.3~0.4 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710695128.8A CN107527802A (en) | 2017-08-15 | 2017-08-15 | Groove type double-layer grid MOS film build methods |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710695128.8A CN107527802A (en) | 2017-08-15 | 2017-08-15 | Groove type double-layer grid MOS film build methods |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107527802A true CN107527802A (en) | 2017-12-29 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710695128.8A Pending CN107527802A (en) | 2017-08-15 | 2017-08-15 | Groove type double-layer grid MOS film build methods |
Country Status (1)
| Country | Link |
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| CN (1) | CN107527802A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491782A (en) * | 2019-08-13 | 2019-11-22 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of groove type double-layer gate MOSFET |
| CN114023652A (en) * | 2021-10-26 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing shielded gate trench type semiconductor device |
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|---|---|---|---|---|
| US20030132480A1 (en) * | 2002-01-16 | 2003-07-17 | Duc Chau | Self-aligned trench mosfets and methods for making the same |
| US20100055857A1 (en) * | 2008-09-04 | 2010-03-04 | Wei-Chieh Lin | Method of forming a power device |
| CN101752295A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method for preparing contact hole isolating layer in power MOS transistor |
| CN102593125A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Groove type MOS (metal oxide semiconductor) electrostatic discharge structure and integrated circuit |
| CN104465781A (en) * | 2014-12-31 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Groove type double-gate MOS and technological method |
-
2017
- 2017-08-15 CN CN201710695128.8A patent/CN107527802A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030132480A1 (en) * | 2002-01-16 | 2003-07-17 | Duc Chau | Self-aligned trench mosfets and methods for making the same |
| US20100055857A1 (en) * | 2008-09-04 | 2010-03-04 | Wei-Chieh Lin | Method of forming a power device |
| CN101752295A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method for preparing contact hole isolating layer in power MOS transistor |
| CN102593125A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Groove type MOS (metal oxide semiconductor) electrostatic discharge structure and integrated circuit |
| CN104465781A (en) * | 2014-12-31 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Groove type double-gate MOS and technological method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110491782A (en) * | 2019-08-13 | 2019-11-22 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of groove type double-layer gate MOSFET |
| CN110491782B (en) * | 2019-08-13 | 2021-11-09 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench type double-layer gate MOSFET |
| CN114023652A (en) * | 2021-10-26 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing shielded gate trench type semiconductor device |
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Application publication date: 20171229 |