CN101394678B - Serialization/de-serialization interface module generally used in GEPON/GPON - Google Patents
Serialization/de-serialization interface module generally used in GEPON/GPON Download PDFInfo
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Abstract
The invention relates to a serialized/deserialized interface module suitable for use in GEPON/GPON modes, which comprises serial signal input port, a serial signal output port, a parallel signal input port, a parallel signal input port, a mode selection port, a sending rate selection port, a receiving rate selection port, a sending data width selection port, a receiving data width selection port, a reference clock input port, a clock selection port, a receiving clock output port, a sending clock input port, a sending end circuit and a receiving end circuit, wherein the receiving end circuit comprises a clock recovery unit CDR and a deserializing unit DEMUX, and the sending end circuit comprises a clock synthesizing and multiplexing unit. The interface module supports the GEPON mode and the GPON mode, and can select line side sending and receiving rates according to different systems and equipment in use.
Description
Technical field
The present invention relates to a kind of general-purpose interface that is common to the SERDES (Serializer-Deserializer, serialization/de-serializer) of gigabit ethernet passive optical network (GEPON) and gigabit passive optical network (GPON) system.
Background technology
Gigabit ethernet passive optical network (GEPON) is to utilize the topological structure of EPON (PON, Passive Optical Network) to realize a kind of latticed form that the ethernet signal of carrying multiple business transmits.Adopt point to multipoint configuration, the passive fiber transmission means provides multiple business on Ethernet.At present, IP/Ethernet uses and to account for more than 90% of whole local area network communication, and EPON is structure efficiently owing to use above-mentioned economy, thereby becomes a kind of effective communication means that connects the Access Network end user.
Similarly, gigabit passive optical network (GPON) also is to adopt point to transmit multi-service data to the passive fiber transmission means of multiple spot, the difference of itself and EPON is, GPON has adopted GFP interchangeable frame agreement, the business (Ethernet, TDM, ATM etc.) of any kind and any speed can be carried out original form encapsulation after, be a kind of brand-new effective solution of Optical Access Network by the PON transmission.
As shown in Figure 1, the typical GEPON/GPON of one cover system is by the optical line terminal (OLT that is positioned at local side, OpticalLine Terminal) and several be positioned at the optical network unit (ONU of far-end, Optical Network Unit) forms, between OLT and the ONU by passive light distribution network (ODN, Optical Distribution Network) connects, adopt the topological structure of point to multiple spot (P2MP, Point to Multi Point).In OLT and ONU equipment, PON MAC chip is used to realize the PON mac-layer protocol, and physical medium relevant layers (PMD, Physical Medium Dependent) function is realized by the optical transceiver module at two ends.
Fig. 2 shows the interface of SERDES and optical module and PON MAC chip, SERDES is as the interface between MAC layer and the pmd layer, be used to connect PON MAC layer acp chip and optical transceiver module, mainly realize the function of PMA layer, as functions such as string and conversion, clock recovery, Comma Detect.。
For the OLT or the ONU of GEPON and GPON system, the interface of SERDES and optical module one side all is the HSSI High-Speed Serial Interface of 1.25G or 2.5G, and much the operation principle of circuit is same or analogous, so there is the possibility of exploitation unified interface.But the interface of SERDES and PON MAC chip is a parallel interface, is discrepant between the different systems.For typical GEPON equipment, usually usefulness is TBI (Ten-Bit-interface) interface that meets the IEEE802.3 standard, also have some producers to develop the EPON system of 2.5G, under this condition, this interface may be the non-standard interface of 20bit bit wide.For GPON equipment, the bit wide of this interface may be 8Bit or 16Bit, and also can there be certain difference in other interface signal definition, depends on the design of each producer.In addition, for OLT and ONU, also there is certain difference in the definition of both interface signals.In order to realize the compatibility of SERDES in 2 kinds of different systems, 2 kinds of distinct devices, need a kind of general series connection with low cost of exploitation/separate serializer module.
Summary of the invention
The present invention proposes serialization/anti-serialization interface module of a kind of GEPON/GPON of being common to, comprising:
Serial signal input port, serial signal output port, parallel signal input port, parallel signal output port, model selection port, transmission rate select port, receiving velocity to select port, transmission data width to select port, reception data width to select port, reference clock input port, clock selecting port, receive clock output port, tranmitting data register input port, transmitting terminal circuit and receiving terminal circuit, wherein
Receiving terminal circuit comprises clock recovery unit CDR, string and converting unit DEMUX, detecting signal unit SDT;
Wherein clock recovery unit selects port, reference clock input port, clock selecting port to be connected with serial signal input port, model selection port, reception data, described clock recovery unit is based on the reference clock of reference clock input port input, from serial data, extract serial clock from the serial signal input port, and make described serial clock and receive data sync, based on the serial clock that extracts serial data is carried out sending to string and converting unit after the 8b/10b decoding; When the GEPON pattern was selected in the indication of model selection port, described clock recovery unit was ignored the signal from the clock selecting port, receives the 125MHz reference clock from the input of reference clock input port; When the GPON pattern was selected in the indication of model selection port, described clock recovery unit selected the clock of 78MHz or 155MHz as the reference clock according to the indication of clock selecting port; Described clock recovery unit selects the indication of port to utilize phase-locked loop circuit to generate the serial clock of 1.25G or 2.5G based on reference clock according to receiving velocity;
String and converting unit are connected with the output port that receives data width selection port, model selection port, parallel signal output port, receive clock output port and clock recovery unit, described string and converting unit are used for being converted to parallel data with having carried out the serial data after the clock recovery, wherein, when the GEPON pattern was selected in the indication of model selection port, described string and converting unit selected the indication of port that serial data is converted to 10bit or 20bit parallel data according to described reception data width; When the GPON pattern was selected in the indication of model selection port, described string and converting unit were converted to the 16bit parallel data with the serial data unification; Parallel data after the conversion is by the output of parallel signal output port, and described string and converting unit are also by output of receive clock output port and the synchronous receive clock of parallel signal;
The transmitting terminal circuit comprises that clock synthesizes and Multiplexing Unit, and the synthetic Multiplexing Unit that reaches of described clock selects port, transmission data width to select port to be connected with parallel data input port, serial data output port, model selection port, tranmitting data register input port, transmission rate; Described clock is synthetic and Multiplexing Unit is imported based on the indication and the tranmitting data register input port of transmission rate selection port synthetic 1.25Gbps of tranmitting data register or 2.5Gbps serial clock; When the GEPON pattern is selected in the indication of model selection port, select the indication of port according to sending data width, based on the synthetic serial clock that obtains, carry out parallel serial conversion by 10bit parallel data or 20bit parallel data and obtain the serial data corresponding with the serial clock frequency; When the GPON pattern was selected in model selection port indication, the synthetic and Multiplexing Unit of described clock was based on the synthetic serial clock that obtains, and carried out parallel serial conversion by the 16bit parallel data and obtained serial data with serial clock frequency correspondence; Resulting serial data is exported via the serial data output interface.
Wherein, described interface module comprises that also COMMA detects the indication port, COMMA detects enable port and described string and converting unit and also comprises the COMMA testing circuit, described COMMA testing circuit detects the indication port with COMMA, COMMA detects the enable port and the model selection port is connected, described COMMA detects the COMMA character in the detection trigger ethernet frame of enable port based on COMMA, and detects the output of indication port by COMMA and detect indication.
Wherein, described interface module also comprises parallel data border indication port, described parallel data border indication port is connected with described string and converting unit, when the model selection port was selected the GPON pattern, described string and converting unit were by the border of the 16bit parallel data of described parallel data border indication interface indication output.
Wherein, the alternative circuit is being set with the loopback test circuit that constitutes the parallel port side respectively and the loopback test circuit of serial port side between parallel data input port and the parallel data output port and between serial data input port and the serial data output port respectively, described loopback test circuit is used for the docking port module and carries out loopback test.
Wherein, the output of the loopback test circuit of surveying at parallel port connects an alternative circuit, and another input of alternative circuit connects a PRBS generator, and the selecting side connects test pattern enable port, Error detection circuit BERT; The PRBS generator is used to produce the required random data input of self-test, be designated as under the test pattern in the test pattern enable port, the dateout of PRBS generator is imported as parallel data, after serial port side internal loopback, from string and converting unit output; The error code testing circuit will detect the completeness of PRBS data behind the chip internal loopback, if mistake do not occur, output test result by test result indication port.
Description of drawings
Fig. 1 is the PON system construction drawing;
Fig. 2 is SERDES and optical module and PON MAC chip interface figure;
Fig. 3 is general SERDES module interface functional definition figure of the present invention;
Fig. 4 is the modular structure figure of general SERDES module of the present invention;
Fig. 5 is the interface function option table of general SERDES module of the present invention;
Fig. 6 is the loopback test schematic diagram of general SERDES module of the present invention.
Embodiment
Describe the specific embodiment of the present invention in detail below in conjunction with accompanying drawing.
In order to solve the compatibility in different system and equipment, following demand is proposed described general module:
1, arbitrary moment can only be defined as GEPON pattern or GPON pattern, and both can only get one.
When 2, working in different mode, can be according to system for use in carrying and device therefor different, the selection wire trackside sends, receiving velocity.
3, can make that the circuit interface characteristic after the conversion can adapt to the demand of different system and equipment, thereby guarantee the stability of interface work according to the bit wide of the different transmissions in line side, receiving velocity selection string and the transmission of conversion back, reception data.
4, should carry out multiplexingly for signal, interface definition is simplified as far as possible with identical electric attribute.
5, the proprietary interface definition of different system should independently be drawn, and is independent of each other.
6, interface should have measurability preferably, can adapt to the test request of different system and equipment.
If be provided with the function of fast synchronous auxiliary circuit in 7 SERDES, interface should have the quick synchronous indicating signal at the GEPON/GPON system, can be on the border of synchronous back designation data.
In order to satisfy the demand, done design for the setting of interface:
1) defining mode selects signal Mode_sel to select GEPON pattern or GPON pattern, after the mode select signal definition, and the interface related sets of signals of activation and GEPON or GPON.
2) for the GPON system, exploitation is the asymmetric system of 2.5G/1.25Gbps usually, but considers the versatility of SERDES, also needs to consider the symmetrical system of 2.5G/2.5Gbps and 1.25G/1.25Gbps.
For the GEPON system, what IEEE802.3-2005 defined is the system of the 1.25Gbps of up-downgoing symmetry, but in actual applications, there is producer to develop the asymmetric system of 2.5G/1.25Gbps (for OLT, it is the transmission rate of 2.5Gbps, 1.25Gbps receiving velocity, otherwise ONU), in order to satisfy above listed all demands, respectively to sending and receiving velocity selection definition XMT_FSEL and RCV_FSEL signal, regulation sends and receiving velocity, is operated under all speed grade guaranteeing.
3) as mentioned above, for the GPON system, it sends receiving velocity can be the symmetrical system of 2.5G/2.5Gbps and 1.25G/1.25Gbps, or the asymmetric system of 2.5G/1.25Gbps.For the robustness of intensifier circuit, after having selected setting GPON pattern, the parallel data bit wide is defaulted as 16Bit, and the parallel interface frequency after the conversion is operated in 78Mhz or 155Mhz like this, can work reliablely.
For the GEPON system, as above chat, according to different application scenarios, it may be the symmetrical system of 1.25G/1.25Gbps, it also may be the asymmetric system of 2.5G/1.25Gbps, can set according to demand and send and receive bit wide selection signal XMT_W_SEL and RCV_W_SEL, make the width that sends receiving interface be operated in 10Bit or 20Bit, thereby the interface operating frequency be operated in 125MHz or 250MHz.This definition can also the compatible 2.5G/2.5Gbps symmetrical system that may occur later.
4) from above analysis as can be seen, being used for the data-interface of 2 kinds of different system SERDES can be multiplexing.High-speed-differential line at serial port needs only the level unanimity, just can be multiplexing; Breadth Maximum in parallel port is 20Bit, when working in the GPON pattern, only uses 16Bit wherein; When working in the 10Bit pattern of GEPON, only need to use low 10Bit.
5) interface signal that will be exclusively used in GEPON and GPON is independently drawn, and after having set mode of operation, will be independent of each other, and have only one group of signal effective.
6) the control pin that is used to test can be shared, as function signals such as loopback test and test patterns.
Loop-back test signal can be provided with the loopback of serial port and parallel port, is convenient to fault location.Fig. 6 is seen in the function signal.
Test pattern indication is set, when batch testing, can starts inner test function, test by the time will provide test and finish signal.
For the GEPON system, if enable the function of Comma Detect, after the requirement according to IEEE802.3Clause36.3 detected Comma, interface will provide and detect indication; For the GPON system, if external chip can provide the border of data, the output of the parallel port of SERDES will be according to this boundary alignment.
Interface function definition figure as Fig. 3, can see that most of signals can be used for the GEPON/GPON system multiplexing, are respectively:
1) with the serial line interface signal of optical module: SIN and SOUT.
Can transmit the high-speed differential signal of 1.25Gbps or 2.5Gbps.
2) control signal.Have 9:
MODE_SEL: be used for the GEPON/GPON model selection.
XMT_FSEL: be used for transmission rate and select.
RCV_FSEL: be used for receiving velocity and select.
XMT_W_SEL: be used to send data width and select.
RCV_W_SEL: be used to receive data width and select.
LOOPEN_S: the serial port loopback enables control.
LOOPEN_P: the parallel port loopback enables control.
RESET: control resets.
TEST_MODE: chip operation is set under test pattern.
According to setting to control signal, the various working methods of interface can be set, specifically can be referring to Fig. 5.
3) reference clock: REFCLK.
Under the GEPON pattern, be 125Mbps, under the GPON pattern, be 78M/155Mbps.
4) pll lock indication: LF_IND.
Can be used to judge the operating state of phase-locked loop.Phase-locked loop circuit GEPON/GPON system can be shared.
5) test is by indication: TEST_OK.
Be used for automatic detection of chip and finish indication.Chip internal has PRBS generator and BERT, after entering test pattern, carries out detecting by providing this indication from detecting.
6) parallel interface data and clock signal:
And line output DOUT, parallel DIN, receive clock RXCLK, the tranmitting data register TXCLK of importing.According to the difference of control signal, the data bit width is different with frequency, can satisfy the various requirement of different system and distinct device, specifically referring to seeing Fig. 5.
The proprietary signal that is used for the GEPON interface has:
1) RBC0/RBC1: the 62.5Mhz clock that is used for TBI interface regulation.
2) SIG_DET: input, the differential signal of detection serial port.
3) BYT_SYNC:COMMA detects indication.Its testing process satisfies the requirement of IEEE802.3Clause36.3.
4) EN_B_SYNC:COMMA detects and enables.
The proprietary signal that is used for the GPON interface has:
1) REF_SEL: reference clock is selected, and can select 78Mhz or 155Mhz reference clock.
2) RCV_SYNC: the border of indication parallel data.
The structure of SERDES can be divided into receiver side circuit, transmitter side circuit and test circuit as shown in Figure 4.
At receiver side, mainly form by clock recovery circuitry (CDR unit), serial-parallel conversion circuit (DEMUX unit), signal deteching circuit (SDT).After selected GEPON pattern of mode select signal MODE_SEL signal or GPON pattern, corresponding sets of signals works.
Be used for locking phase in the CDR unit, receiver carries out the data bit alignment according to clock recovered then, then carries out the word alignment with reference clock.At last, data are carried out the extracting data serial clock of 8b/10b decoding from receiving, and make this clock and receive data sync.For GEPON and GPON pattern, the circuit of this part is consistent substantially, and difference is under different patterns the REFCLK difference.For different speed, the phase-locked loop circuit in the CDR unit will be indicated according to rate selection, select corresponding Clock Multiplier Factor, to obtain the serial clock of 1.25G or 2.5G.If phase-locked loop circuit can not lock, then will provide the LF_IND indication.
The major function of DEMUX unit is that serial data is converted to parallel data, also has the COMMA testing circuit to be used for detecting the COMMA character of ethernet frame.Under the GPON pattern, parallel data is 16Bit, if the indication of RCV_SYNC signal is worked, can be used to refer to the border of byte; For the GEPON pattern, deciding the DEMUX unit by the RCV_W_SEL indication is to adopt 10Bit or the output of 20Bit, and under the GEPON pattern, when the EN_B_SYN signal is designated as " 1 ", inner COMMA testing circuit will work, and the COMMA character has been found in output BYT_SYNC indication.The selection of above-mentioned functions can realize by some simple logical circuits.
The SDT circuit is mainly used in the signal testing function under the GEPON pattern, and serial signal reaches certain threshold value will provide the SIG_DET signal, can be used for the state transitions input of some Fault Diagnosis and subsequent conditioning circuit.
The circuit of transmitter side mainly is the synthetic and Multiplexing Unit (SYNTHESIZER﹠amp of clock; MUX).For GEPON and GPON pattern, the circuit that serial clock produces part is consistent substantially, all needs Synthesizer PLL to generate the serial tranmitting data register, and difference just is 2 kinds of tranmitting data register signal TXCLK differences under the pattern.For different transmission rates, clock circuit will be selected indication according to transmission rate, select corresponding Clock Multiplier Factor, to obtain the serial clock of 1.25G or 2.5G.The MUX partial circuit is finished the conversion of parallel data to serial data, and under the GPON pattern, the 16Bit parallel data is effective; Under the GEPON pattern, indicate the valid data of 10Bit or 20Bit by XMT_W_SEL.The selection of these functions can realize by some simple logical circuits.
The circuit that is used for loopback test is made of the alternative circuit.As shown in Figure 4, an alternative circuit is arranged respectively, control by LOOPEN_S and LOOPEN_P and select which signal output in serial side and parallel side.
Convenient for the interface module batch testing, in interface module, be provided with test circuit, comprise PRBS generator (PRBS GRT) and Error detection circuit (BERT), this part circuit is only effective when TEST_MODE is " 1 ".The PRBS generator is used to produce the required random data input of self-test, under test pattern, as the parallel data input, after internal loopback, exports from DEMUX.The bert circuitry design with detecting the completeness of PRBS data behind the chip internal loopback, if mistake do not occur, will provide the TEST_OK indication in the DEMUX unit.
The present invention has realized a kind of general SERDES interface module, the application scenario of special-purpose SERDES is expanded greatly, inherited can be shared in the SERDES design part, made things convenient for the SERDES designer to adjust designing requirement according to different demands, common interface module can satisfy the requirement of various interface modes such as GEPON/GPON OLT/ONU equipment, and has accomplished signal and multiplexing functions to greatest extent.
The above is preferred embodiment of the present invention only, is not limited to the present invention, all any modifications of being made within the present invention spirit and principle, is equal to replacement and improvement etc., all is contained within protection scope of the present invention.
Claims (5)
1. serialization/anti-serialization interface module that is common to GEPON/GPON comprises:
Serial data input port, serial data output port, parallel data input port, parallel data output port, model selection port, transmission rate select port, receiving velocity to select port, transmission data width to select port, reception data width to select port, reference clock input port, clock selecting port, receive clock output port, tranmitting data register input port, transmitting terminal circuit and receiving terminal circuit, wherein
Receiving terminal circuit comprises clock recovery unit CDR, string and converting unit DEMUX;
Wherein clock recovery unit selects port, reference clock input port, clock selecting port to be connected with serial data input port, model selection port, reception digit rate, described clock recovery unit is based on the reference clock of reference clock input port input, from serial data, extract serial clock from the serial data input port, and make described serial clock and receive data sync, based on the serial clock that extracts serial data is carried out sending to string and converting unit after the 8b/10b decoding; When the GEPON pattern was selected in the indication of model selection port, described clock recovery unit was ignored the signal from the clock selecting port, receives the 125MHz reference clock from the input of reference clock input port; When the GPON pattern was selected in the indication of model selection port, described clock recovery unit selected the clock of 78MHz or 155MHz as the reference clock according to the indication of clock selecting port; Described clock recovery unit selects the indication of port to utilize phase-locked loop circuit to generate the serial clock of 1.25G or 2.5G based on reference clock according to receiving velocity;
String and converting unit are connected with the output port that receives data width selection port, model selection port, parallel data output port, receive clock output port and clock recovery unit, described string and converting unit are used for being converted to parallel data with having carried out the serial data after the clock recovery, wherein, when the GEPON pattern was selected in the indication of model selection port, described string and converting unit selected the indication of port that serial data is converted to 10bit or 20bit parallel data according to described reception data width; When the GPON pattern was selected in the indication of model selection port, described string and converting unit were converted to the 16bit parallel data with the serial data unification; Parallel data after the conversion is by the output of parallel data output port, and described string and converting unit are also by output of receive clock output port and the synchronous receive clock of parallel signal;
The transmitting terminal circuit comprises that clock synthesizes and Multiplexing Unit, and the synthetic Multiplexing Unit that reaches of described clock selects port, transmission data width to select port to be connected with parallel data input port, serial data output port, model selection port, tranmitting data register input port, transmission rate; Described clock is synthetic and Multiplexing Unit is imported based on the indication and the tranmitting data register input port of transmission rate selection port synthetic 1.25Gbps of tranmitting data register or 2.5Gbps serial clock; When the GEPON pattern is selected in the indication of model selection port, carry out parallel serial conversion based on the synthetic serial clock that obtains by 10bit parallel data or 20bit parallel data according to the indication that sends data width selection port and obtain the serial data corresponding with the serial clock frequency; When the GPON pattern was selected in model selection port indication, the synthetic and Multiplexing Unit of described clock carried out parallel serial conversion based on the synthetic serial clock that obtains by the 16bit parallel data and obtains serial data with serial clock frequency correspondence; Resulting serial data is exported via the serial data output port.
2. interface module as claimed in claim 1, it is characterized in that: described interface module comprises that also COMMA detects the indication port, COMMA detects enable port and described string and converting unit and also comprises the COMMA testing circuit, described COMMA testing circuit detects the indication port with COMMA, COMMA detects the enable port and the model selection port is connected, described COMMA testing circuit detects the COMMA character in the detection trigger ethernet frame of enable port based on COMMA, and detects the output of indication port by COMMA and detect indication.
3. interface module as claimed in claim 1, it is characterized in that: described interface module also comprises parallel data border indication port, described parallel data border indication port is connected with described string and converting unit, when the model selection port was selected the GPON pattern, described string and converting unit were by the border of the 16bit parallel data of described parallel data border indication interface indication output.
4. interface module as claimed in claim 1, it is characterized in that: the alternative circuit is being set with the loopback test circuit that constitutes the parallel port side respectively and the loopback test circuit of serial port side between parallel data input port and the parallel data output port and between serial data input port and the serial data output port respectively, described loopback test circuit is used for the docking port module and carries out loopback test.
5. interface module as claimed in claim 4, it is characterized in that: the output of the loopback test circuit of surveying at parallel port connects an alternative circuit, another input of alternative circuit connects a PRBS generator, and the selecting side connects test pattern enable port, Error detection circuit BERT; The PRBS generator is used to produce the required random data input of self-test, be designated as under the test pattern in the test pattern enable port, the dateout of PRBS generator is imported as parallel data, after serial port side internal loopback, from string and converting unit output; The error code testing circuit will detect the completeness of PRBS data behind the chip internal loopback, if mistake do not occur, output test result by test result indication port.
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| CN109947681B (en) * | 2019-03-20 | 2020-12-01 | 天津芯海创科技有限公司 | Serializer/deserializer and high-speed interface protocol exchange chip |
| CN110781112A (en) * | 2019-10-23 | 2020-02-11 | 中国人民解放军国防科技大学 | Dual-channel serial RapidIO interface supporting multiple transmission modes |
| CN111342835A (en) * | 2020-02-27 | 2020-06-26 | 成都泰格微电子研究所有限责任公司 | SERDES module for JESD204B interface |
| CN114553350B (en) * | 2020-11-24 | 2023-09-05 | 中国科学院沈阳自动化研究所 | Deterministic low-delay message processing method |
| CN113626364B (en) * | 2021-06-30 | 2024-05-31 | 海光信息技术股份有限公司 | High-speed serial interface and conversion circuit for same |
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| US7134796B2 (en) * | 2004-08-25 | 2006-11-14 | Opnext, Inc. | XFP adapter module |
| CN101009488A (en) * | 2006-01-10 | 2007-08-01 | 恩益禧电子股份有限公司 | Clock and data recovery circuit, and SERDES circuit |
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2008
- 2008-11-07 CN CN2008102259373A patent/CN101394678B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7134796B2 (en) * | 2004-08-25 | 2006-11-14 | Opnext, Inc. | XFP adapter module |
| CN101009488A (en) * | 2006-01-10 | 2007-08-01 | 恩益禧电子股份有限公司 | Clock and data recovery circuit, and SERDES circuit |
Non-Patent Citations (1)
| Title |
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| JP特开2007-288702A 2007.11.01 |
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| CN101394678A (en) | 2009-03-25 |
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