CN102593098A - Metal interconnection structure of integrated circuit and preparation method for metal interconnection structure - Google Patents
Metal interconnection structure of integrated circuit and preparation method for metal interconnection structure Download PDFInfo
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- CN102593098A CN102593098A CN2012100484778A CN201210048477A CN102593098A CN 102593098 A CN102593098 A CN 102593098A CN 2012100484778 A CN2012100484778 A CN 2012100484778A CN 201210048477 A CN201210048477 A CN 201210048477A CN 102593098 A CN102593098 A CN 102593098A
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Abstract
The invention discloses a metal interconnection structure of an integrated circuit and a preparation method for the metal interconnection structure. A graphene covering layer is coated on the upper surfaces of upper layer metal interconnection lines of the metal interconnection structure of the integrated circuit by utilizing the proper unique molecular structure and the electrology characteristic of graphene. As the electromigration-resistance current density of the graphene can reach 109A/cm<2>, once when small cavities appear in metal conductors due to electromigration, current can be possibly conducted through the graphene coated on the surfaces of the metal conductors, and thereby, the growth rate of the cavities in the metal interconnection lines is effectively lowered, the electromigration resistance of the metal interconnection lines is increased, and the service lives of the metal interconnection lines are prolonged. Meanwhile, the graphene coated on the surfaces of the metal interconnection lines is also capable of effectively stopping the growth of crystal whiskers, and thereby, the short circuit risk caused by the growth of the crystal whiskers is lowered. Moreover, the graphene covering layer is capable of effectively isolating the metal conductors from contacting with the air so as to retard or eliminate the oxidation of the surfaces of the metal interconnection lines, and thereby, the reliability of the interconnection lines of the integrated circuit is improved.
Description
Technical field
The present invention relates to nanofabrication technique, specifically is a kind of integrated circuit metal interconnect structure and preparation method thereof.
Background technology
Constantly scaled along with the IC-components size, circuit level improves constantly, and the performance of metal interconnecting wires becomes one of key factor that influences IC reliability in the integrated circuit.And electromigration is the main cause that causes the metal interconnecting wires performance degradation.So-called electromigration, exactly after current density reaches a certain value, in the metallic conductor the mass transportation phenomenon; Promptly when current density is very high; Electron density through metal interconnecting wires is very high, this strand " electron wind " can to the metal ion near near the positively charged the negative electrode apply one very big with former electric field force power in the opposite direction, when this power enough greatly the time; Just can make metal ion have enough big momentum to move to contiguous room, thereby make the electromigration of metallic atom anode.Electromigration can make the interconnecting line in the integrated circuit produce in the course of the work to open circuit or short circuit, thereby causes ic failure, and it shows as: 1. in interconnecting line, form the cavity, increased resistance; 2. grow up in the cavity, finally runs through interconnecting line, and formation is opened circuit; 3. in interconnecting line, form whisker, even overlap, cause layer short circuit with the interconnection line that closes on; 4. whisker is grown up, and penetrates passivation layer, produces source of corrosion.Electromigration is a kind of major reason that causes ic failure.The interconnecting metal of integrated circuit mainly contains the alloy of copper, aluminium or aluminium at present.Wherein the deelectric transferred critical current density of aluminum steel is 2 * 10
5A/cm
2, surpass this value and the circuit malfunction that electromigration causes will occur.Though the deelectric transferred current density of copper conductor is bigger than aluminium, when current density surpasses 10
6A/cm
2The time also tangible electromigration can appear.Research shows that electromigration mainly occurs in the plain conductor top surface.Possible solution is through the surface deposition one deck cover layer at copper interconnecting line copper atom migration is restricted, and can prevent that copper connecting lines from following the oxygen contact, can effectively improve the deelectric transferred ability of copper interconnecting line.These covering layer materials comprise SiN
x, CoWB, CuSiN, CoWP etc.Though these cover layers can effectively improve the reliability of metal interconnecting wires, can increase the resistance of interconnection line.In addition; People such as Chai are through coming Alloy instead of Copper with the Cu/CNT composite material; Can effectively reduce the growth rate of hole, empty growth rate is about 1/4th of pure copper material in the Cu/CNT composite material, but same problem is exactly that resistivity has increased 15% than fine copper resistivity.
Summary of the invention
The objective of the invention is to propose a kind of method of utilizing Graphene to prepare metal interconnected line structure.
Basic principle of the present invention has been utilized distinctive molecular structure of Graphene own and electrology characteristic exactly; Comprise atomic scale; High conductivity; High deelectric transferred current density, good thermal stability and chemical stability etc., coated graphite alkene cover layer on metal connecting line surface, the upper strata of integrated circuit metal interconnect structure.Because the deelectric transferred current density of Graphene can reach 10
9A/cm
2In plain conductor, in a single day occur in the little cavity owing to electromigration; Electric current just might conduct through the Graphene that is coated on the plain conductor surface, thereby effectively reduces the growth rate in cavity in the metal interconnecting wires, the deelectric transferred ability and the life-span thereof of improving metal interconnecting wires; The Graphene that is coated on the metal interconnecting wires surface simultaneously also can effectively stop the growth of whisker, thereby reduction causes short risk because of whisker growth; In addition, this Graphene cover layer can effectively completely cut off plain conductor and contact with air, slows down or eliminate the oxidation on metal interconnecting wires surface, thereby improves the reliability of integrated circuit interconnection line.
Technical scheme provided by the invention is following:
A kind of integrated circuit metal interconnect structure comprises upper and lower layer metal connecting line and the through hole that connects the upper/lower layer metallic line, it is characterized in that the surface coverage single or multiple lift Graphene of metal connecting line on the upper strata.
A kind of preparation method of metal interconnected line structure, concrete steps comprise:
(1) preparation lower metal line, and on its structure metallization medium layer.
The lower metal line can be a tungsten, also can be that the surface coats like tectal copper, nickel, the alloy of copper or the alloys of nickel such as NiWP, CuSiN, CoWP.Metallization medium layer on the lower metal connecting line construction, dielectric layer can be low-K dielectric materials such as silicon dioxide, doping silicon dioxide, organic polymer and porous material.
(2) preparation connects the through hole of lower metal line and the groove of upper strata metal interconnecting wires.Connecting the through hole of lower metal line and the groove of upper strata metal interconnecting wires can be (the single mosaic technology) that forms in two steps, also can be (dual-damascene technics) that forms simultaneously, and so-called mosaic technology just is meant that first etching groove recharges the technology of metal.
(3) in bottom and the side wall deposition one deck diffusion impervious layer and the metal seed layer of through hole and groove.Elder generation is at bottom and side wall deposition one deck diffusion impervious layer of through hole and groove, then in barrier layer surface plated metal seed layer.Diffusion impervious layer can be TaN/Ta, WN, and Ru etc., deposition process can be the methods of physical vapor deposition (PVD), also can be the methods of ald (ALD).
(4) plated metal in through hole and groove, and with the method for chemico-mechanical polishing to upper strata metal connecting line and dielectric layer flattening surface.The upper strata metal adopts copper, nickel, the alloy of copper or the alloy of nickel.The method of plated metal can be methods such as physical vapour deposition (PVD) or chemical vapour deposition (CVD), plating, chemical plating.
(5) metal connecting line surface in situ growth Graphene optionally: with the method for chemical vapor deposition (CVD), at copper connecting lines surface in situ covering graphene layer on the upper strata.The carbon source of Graphene of being used to grow can be a carbonaceous gas, like CH
2, CH
4Deng, also can be carbonaceous liquid, like ethanol, can also be carbonaceous solids, like PMMA.The Graphene cover layer of preparation can be an individual layer, and bilayer or multi-layer graphene also can be amalgams.
(6) preparation multilayer interconnect structure: repeat above-mentioned (1)～(5) process, then can prepare the tectal multilevel metal interconnection structure of coated graphite alkene.
Advantage of the present invention is following:
The thickness of single-layer graphene has only 0.34nm, and every increase one deck, thickness only are to have increased 0.34nm, can well satisfy the requirement that overburden cover will approach as far as possible; The high conductivity of Graphene has satisfied the requirement of low sheet resistance; The maximum current density that Graphene can bear is 10
9A/cm
2Magnitude has effectively guaranteed the deelectric transferred ability that it is powerful; Thermal stability that Graphene is good and chemical stability have guaranteed that also the Graphene cover layer is used to improve the validity and the reliability of metal interconnecting wires reliability.
Description of drawings
Fig. 1-Fig. 6 is at the tectal sketch map of copper connecting lines superficial growth Graphene;
Wherein, 1-lower floor copper interconnecting line; The 2-NiWP cover layer; 3-silica dioxide medium layer; The 4-diffusion impervious layer; 5-upper copper interconnection line; 6-Graphene cover layer.
Embodiment
Specific embodiment is following:
(1) preparation lower floor copper interconnecting line 1: lower floor's copper interconnecting line 1 is through the mosaic technology preparation, and its surface is through chemico-mechanical polishing and be coated with the NiWP layer, and is as shown in Figure 1.
(2) use method deposit thickness on lower floor's copper interconnecting line structure of PECVD to be the silica dioxide medium layer 3 of 1 μ m, as shown in Figure 2.
(3) method with reactive ion etching (RIE) etches the through hole of connection lower floor copper interconnecting line 1 and the groove (dual-damascene technics) of upper copper interconnection line 5 in silica dioxide medium layer 3, like Fig. 3, shown in 4.
(4) with the method for ald at the thick TaN of the bottom of through hole and groove and side wall deposition one deck 5nm as diffusion impervious layer 4, and then use CuCl above that
2Do reactant, H
2Do the method deposition 5nm thick copper seed layer of reducing agent with ald.
The method of (5) electricity consumption chemical plating (ECP) deposited copper metal in through hole and groove, and make copper coating 5 and dielectric layer 3 flattening surfaces with the method for chemico-mechanical polishing, thus form through hole and the upper copper interconnection line 5 that connects lower floor's copper interconnecting line 1, as shown in Figure 5.
(6) with the method for chemical vapour deposition (CVD), the wire list long Graphene cover layer 6 of looking unfamiliar on the upper strata.
Optionally on the surface of upper copper interconnection line 5 with the method growth Graphene cover layer 6 of chemical vapour deposition (CVD), its growth technique is following:
(i) temperature-rise period: at H
2Under Ar atmosphere, in 60 minutes, furnace temperature is risen to 850 ℃ of growth temperatures.H
2Flow control is at 15sccm, and the flow control of Ar is at 450sccm;
(ii) insulating process: after furnace temperature rises to growth temperature, continue at H
2With kept 20 minutes under the atmosphere of Ar;
(iii) Graphene growth course: after the thermostatic process, methane is introduced in the stove, flow control is at 15sccm, and it is constant that temperature continues to keep, and growth time is 10 minutes.
(iv) temperature-fall period: after growth course is accomplished, close CH
4Gas continues to keep H
2Lower the temperature with beginning under the Ar flow rate condition, cooling rate is 20 ℃/min.
The structure that forms at last is as shown in Figure 6.
Above-described embodiment is used to limit the present invention, and any those skilled in the art is not breaking away from the spirit and scope of the present invention, can make various conversion and modification, so protection scope of the present invention is looked the claim scope and defined.
Claims (7)
1. an integrated circuit metal interconnect structure comprises upper and lower layer metal interconnecting wires and the through hole that connects the upper/lower layer metallic interconnection line, it is characterized in that the surface coverage single or multiple lift Graphene of metal interconnecting wires on the upper strata.
2. integrated circuit metal interconnect structure as claimed in claim 1 is characterized in that, said lower metal interconnection line is a tungsten, or the surface coats tectal copper, nickel, the alloy of copper or the alloys of nickel such as NiWP, CuSiN, CoWP.
3. integrated circuit metal interconnect structure as claimed in claim 1 is characterized in that, the upper strata metal adopts copper, nickel, the alloy of copper or the alloy of nickel.
4. the preparation method of a metal interconnected line structure, concrete steps comprise:
1) preparation lower metal connecting line construction, and on this metal connection structure metallization medium layer;
2) form metal interconnecting wires; Method with chemico-mechanical polishing makes the body structure surface leveling and metal interconnecting wires surface, upper strata is exposed;
3) the metal connecting line surface coverage single or multiple lift Graphene on the upper strata.
5. method as claimed in claim 4 is characterized in that, step 1) medium layer is a silicon dioxide, or doping silicon dioxide, organic polymer, or low-K dielectric material such as porous material.
6. method as claimed in claim 4 is characterized in that step 2) in form metal interconnecting wires and specifically comprise:
I) etching forms the through hole of connection lower metal line and the groove of upper strata metal connecting line;
Ii) in bottom and the side wall deposition one deck diffusion impervious layer and the metal seed layer of above-mentioned through hole and groove, and deposition upper strata metal connecting line.
7. method as claimed in claim 4 is characterized in that step 3) specifically comprises: with chemical gaseous phase depositing process on the upper strata metal connecting line surface in situ growth graphene layer.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9171801B2 (en) | 2013-05-09 | 2015-10-27 | Globalfoundries U.S. 2 Llc | E-fuse with hybrid metallization |
| US9202743B2 (en) | 2012-12-17 | 2015-12-01 | International Business Machines Corporation | Graphene and metal interconnects |
| CN105274595A (en) * | 2014-05-30 | 2016-01-27 | 应用材料公司 | Method for electrochemically depositing metal on a reactive metal film |
| US9257391B2 (en) | 2013-04-30 | 2016-02-09 | GlobalFoundries, Inc. | Hybrid graphene-metal interconnect structures |
| US9293412B2 (en) | 2012-12-17 | 2016-03-22 | International Business Machines Corporation | Graphene and metal interconnects with reduced contact resistance |
| US9305879B2 (en) | 2013-05-09 | 2016-04-05 | Globalfoundries Inc. | E-fuse with hybrid metallization |
| US9431346B2 (en) | 2013-04-30 | 2016-08-30 | GlobalFoundries, Inc. | Graphene-metal E-fuse |
| US9536830B2 (en) | 2013-05-09 | 2017-01-03 | Globalfoundries Inc. | High performance refractory metal / copper interconnects to eliminate electromigration |
| CN106505031A (en) * | 2015-09-07 | 2017-03-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of copper interconnection structure, copper interconnection structure and electronic installation |
| CN114898915A (en) * | 2022-05-31 | 2022-08-12 | 四川华丰科技股份有限公司 | Circuit wire, manufacturing method of circuit wire and connector |
| EP4109508A3 (en) * | 2021-06-25 | 2023-01-25 | Intel Corporation | Integrated circuit interconnect structures with graphene cap |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9293412B2 (en) | 2012-12-17 | 2016-03-22 | International Business Machines Corporation | Graphene and metal interconnects with reduced contact resistance |
| US9202743B2 (en) | 2012-12-17 | 2015-12-01 | International Business Machines Corporation | Graphene and metal interconnects |
| US9431346B2 (en) | 2013-04-30 | 2016-08-30 | GlobalFoundries, Inc. | Graphene-metal E-fuse |
| US9257391B2 (en) | 2013-04-30 | 2016-02-09 | GlobalFoundries, Inc. | Hybrid graphene-metal interconnect structures |
| US9305879B2 (en) | 2013-05-09 | 2016-04-05 | Globalfoundries Inc. | E-fuse with hybrid metallization |
| US9171801B2 (en) | 2013-05-09 | 2015-10-27 | Globalfoundries U.S. 2 Llc | E-fuse with hybrid metallization |
| US9536830B2 (en) | 2013-05-09 | 2017-01-03 | Globalfoundries Inc. | High performance refractory metal / copper interconnects to eliminate electromigration |
| CN105274595A (en) * | 2014-05-30 | 2016-01-27 | 应用材料公司 | Method for electrochemically depositing metal on a reactive metal film |
| CN105274595B (en) * | 2014-05-30 | 2020-01-03 | 应用材料公司 | Method for electrochemically depositing a metal on a reactive metal film |
| CN106505031A (en) * | 2015-09-07 | 2017-03-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of copper interconnection structure, copper interconnection structure and electronic installation |
| CN106505031B (en) * | 2015-09-07 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of copper interconnection structure, copper interconnection structure and electronic device |
| EP4109508A3 (en) * | 2021-06-25 | 2023-01-25 | Intel Corporation | Integrated circuit interconnect structures with graphene cap |
| CN114898915A (en) * | 2022-05-31 | 2022-08-12 | 四川华丰科技股份有限公司 | Circuit wire, manufacturing method of circuit wire and connector |
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Application publication date: 20120718 |