CN201576463U

CN201576463U - Device for producing and displaying bitmap information during embedded flash memory testing process

Info

Publication number: CN201576463U
Application number: CN2009200747546U
Authority: CN
Inventors: 辛吉升; 桑浚之
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-12-03
Filing date: 2009-12-03
Publication date: 2010-09-08
Anticipated expiration: 2019-12-03

Abstract

The utility model discloses a device for producing and displaying bitmap information during the embedded flash memory testing process. The device comprises a fault bitmap conversion module; one end of the fault bitmap conversion module is connected with a fault information acquisition module, and the other end of the fault bitmap conversion module is connected with a fault bitmap display module; and the fault bitmap conversion module is connected with a mode control module and controlled by the mode control module. The quantity of information contained in the fault bitmap produced by the utility model is large, so that the produced reasons of the fault information during the memory testing process can be rapidly determined, which estimates that the half of time can be shortened compared with the using method in the prior art.

Description

The device of generation and display bitmap information in the embedded flash memory test process

Technical field

The utility model relates to a kind of semiconductor test apparatus, is specifically related to the device of the display message in a kind of semiconductor test.

Background technology

After the wafer manufacturing was finished, test was unusual important step.Test is the school report of wafer production process.In test process, the electrical ability and the circuit function of each chip all are detected.Wafer sort chip testing just or wafer electrical measurement.

When test, wafer is fixed on the chuck of pull of vacuum, and aims at very thin proving installation electroprobe, and proving installation contacts with each welded gasket of chip simultaneously.Electroprobe test circuit and note the result under the driving of power supply.Quantity, order and the type of test are controlled by computer program.Test machine is robotization, so aim at auxiliary that the test job of back (manual-alignment or use automatic vision system) need not the operator with first wafer at the proving installation electroprobe.

Test is for following three targets.The first, before wafer is delivered to encapsulation factory, identify qualified chip.The second, the electrical parameter of devices/circuits carries out characteristic evaluation.Engineers needs the distribution of monitoring parameter to keep the quality level of technology.The 3rd, the certified products of chip and the accounting of defective products provide the feedback of comprehensive achievement can for the wafer production personnel.Qualified chip and the defective products position on wafer is noted with the form of wafer figure on computers.

Wafer sort is one of main chip yields statistic device.Along with improving, area of chip increase and density makes that the expense of wafer sort is increasing.So, chip needs longer test duration and accurate more complicated power supply, mechanical hook-up and computer system to carry out test job and test results monitored.Vision inspection system also is accurate and expensive more along with chip size expansion.The designer of chip is required test pattern is introduced storage array.How the designer of test simplifies testing process more and effectively, for example uses the test procedure of simplifying in the qualified back of chip parameter assessment exploring, and the chip in addition also can the interlacing test wafer perhaps carries out the test of a plurality of chips simultaneously.

There is following problems in error message technology for automatically treating in the existing large scale integrated chip test:

1, mainly depend on Memory class testing instrument dedicated tester, if test with logic tester, the failure message that the back that then finishes obtains is not comprehensive, can only obtain the failure message of logical address, does not have the failure message of physical address.

2, do not have the fault bitmap (FBM, Fail Bit Map) of physics, thereby can't characterize the failure mode of fault bit intuitively.

3, can't produce fault bitmap FBM file with device-independent bitmap (DIB, Device Independent Bitmap) form

The utility model content

Technical problem to be solved in the utility model provides a kind of the generation and the device of display bitmap information in the embedded flash memory test process, the fault bitmap that it can produce, what wherein comprise contains much information, and can position the failure message reason that produces in the memory test process more quickly.

In order to solve above technical matters, the utility model provides a kind of and has produced in the embedded flash memory test process and the device of display bitmap information, comprising: a fault bitmap-converted module; Described fault bitmap-converted module one end connects the fault information acquisition module; The described fault bitmap-converted module other end connects a fault bitmap display module; Described fault bitmap-converted module connects a mode control module, and is controlled by mode control module.

The beneficial effects of the utility model are: what comprise in the fault bitmap of generation contains much information, can position the failure message reason that produces in the memory test process more quickly, expectation can be shortened the time of half than the method for using in the prior art.

Description of drawings

Below in conjunction with the drawings and specific embodiments the utility model is described in further detail.

Fig. 1 is a fault information acquisition module synoptic diagram;

Fig. 2 is the described device synoptic diagram of the utility model embodiment;

Fig. 3 is the synoptic diagram of the text of the record trouble information that forms of the utility model embodiment.

Embodiment

As shown in Figure 1, a kind of logic tester of the present utility model produces in the embedded flash memory test process and the device of display bitmap information, comprise a fault bitmap FBM modular converter, this fault bitmap FBM modular converter one end connects the fault information acquisition module, the other end connects a fault bitmap FBM display module, and by a mode control module control.

(1) fault information acquisition module

Described fault information acquisition module can store all failure messages of producing in test process logical address according to storer get off

The test of flash memory generally comprises scanning 00, scanning 11, and gridiron pattern test events such as (check board), same flash memory was because the mechanism difference of fault may lose efficacy on different test events.

As shown in Figure 2, when each test event is tested, at first by programmed control, algorithm pattern generator (ALPG) and sequential vector maker (SQPG) by ATE (automatic test equipment) ATE produce synchronous signal, be carried on all tested flash chips, the output terminal of channel C hannel by ATE (automatic test equipment) ATE carries out by Pass and failure Fail relatively the information of Pass/Fail directly being outputed to address failure storer AFM (Address Fail Memory) module.

(2) failure message module

After each project testing finishes, from address failure storer AFM module, read information, directly output in the txt text, as shown in Figure 3, essential informations such as place test event (is example with Scan 00), lot/slot/address/ have been comprised in the text, the pass/fail information that has also comprised simultaneously all logical addresses, the pass record is 0, the fail record is 1

(3) fault bitmap FBM modular converter

The information of failure message module is input in the special fault crossover tool of developing and goes, this instrument is according to the concrete physical location of each the bit position in each address of SRAM, the fail information of Cheng Chengyi the physics of logic fail information translation in the information module, and embody with the BMP graphics mode of DIB form.By the information of fault bitmap FBM display module according to the display file of BMP graphical format, and in shown graphical information:

The failure message situation of A, all bits all can obtain showing, comprise each bit 0 fault, 1 fault, trouble-free information.Fault bit is red, and non-fault bit is colourless.

B, can be with the different failure message of different color representative.Color as 0/1 equal fault is the synthetic of 0 fault and two kinds of colors of 1 fault.

C, can be in fault bitmap FBM display module show the only bit on certain fault (such as 0 fault) selectively.

D, the fault bitmap FBM of each memory chip is lined up according to coordinate, can obtain the fault bitmap FBM of whole piece of wafer, in this fault bitmap FBM figure, on the position of click, can demonstrate the information of physical location.

In the process that the engineering print of embedded flash memory and static RAM class like product is estimated, can adopt method of the present utility model.

The utility model is not limited to embodiment discussed above.More than the description of embodiment is intended in order to describe and illustrate the technical scheme that the utility model relates to.Based on the conspicuous conversion of the utility model enlightenment or substitute and also should be considered to fall into protection domain of the present utility model.Above embodiment is used for disclosing best implementation method of the present utility model, so that those of ordinary skill in the art can use numerous embodiments of the present utility model and multiple alternative reaches the purpose of this utility model.

Claims

1. one kind produces in the embedded flash memory test process and the device of display bitmap information, it is characterized in that, comprising:

A fault bitmap-converted module;

Described fault bitmap-converted module one end connects the fault information acquisition module;

The described fault bitmap-converted module other end connects a fault bitmap display module;

Described fault bitmap-converted module connects a mode control module, and is controlled by mode control module.

2. as claimed in claim 1 the generation in the embedded flash memory test process and the device of display bitmap information is characterized in that in the graphical format fileinfo of described fault bitmap display module demonstration, the failure message situation of all bits all shows.

3. as claimed in claim 2 the generation in the embedded flash memory test process and the device of display bitmap information is characterized in that the failure message of described bit comprises each bit 0 fault, 1 fault, 0/1 equal fault and trouble-free information.

4. as claimed in claim 1 in the embedded flash memory test process, the generation and the device of display bitmap information, it is characterized in that, in the graphical format fileinfo that described fault bitmap display module shows, in fault bitmap display module, show the only bit on certain fault selectively.

5. as claimed in claim 1 in the embedded flash memory test process, the generation and the device of display bitmap information, it is characterized in that, in the graphical format fileinfo that described fault bitmap display module shows, the fault bitmap of each memory chip is lined up according to coordinate, obtain the fault bitmap of whole piece of wafer; In this fault bitmap graphics, on selected position, demonstrate the information of physical location.