CN102567168A - BIST (Built-in Self-test) automatic test circuit and test method aiming at PHY (Physical Layer) high-speed interface circuit - Google Patents
BIST (Built-in Self-test) automatic test circuit and test method aiming at PHY (Physical Layer) high-speed interface circuit Download PDFInfo
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Abstract
The invention discloses a BIST (Built-in Self-test) automatic test circuit and a test method aiming at a PHY (Physical Layer) high-speed interface circuit. The test circuit comprises a BIST control circuit, an analog circuit parameter control scan chain, two selectors and a test result output circuit, wherein the BIST control circuit has the functions of automatically generating control signals and data and comparing results. The test method comprises the following steps of: (1) entering into an ATPG (Automatic Test Pattern Generation) scan mode; (2) configuring the parameter of the PHY high-speed interface circuit and the parameter of a PLL (Phase Locked Loop) circuit through the scan chain; (3) entering into a PHYBIST test mode; (4) starting to automatically generate a test vector, and inputting a measurement vector to the PHY high-speed interface circuit; (5) returning the data in a built-in loopback way, and comparing the correctness of the returned data; and (6) outputting a test result. According to the test circuit disclosed by the invention, the PHY high-speed interface circuit can be effectively tested under an actual speed mode, the cost of hardware is low, the control is simple, and the complex degree and the test time of the test vector used by ATE (Automatic Test Equipment) are reduced.
Description
Technical field
The present invention relates to field of automatic testing; Especially relate to and be used for ATE (Automatic Test Equipment; Be automated test device) the test methodology field of tester table; More specifically relate to a kind of BIST (Built-in Self-Test, i.e. built-in self-test) test circuit and method of testing to PHY (Physical Layer, i.e. Physical layer) high-speed interface circuit.
Background technology
Integrated circuit testing is significant to development of integrated circuits, the important evidence that it is not only guide product design, produces and use, and be to improve the quality of products and reliability, the effective measures of carrying out TQC.
Along with the development of integrated circuit fields, some interface circuits are because travelling speed is very high, so its Design of Digital Circuit is replaced by the high speed analog circuit of full customization (PHY) gradually.At present, the test to these PHY high-speed interface circuits has unprecedented huge challenge.Why like this, be because the high speed characteristics that these interface circuits itself are had makes that the output signal capture to this interface has very big difficulty on the ATE tester table on the one hand, and the existing testing apparatus of upgrading or replacing mean huge economic cost; Be because the interface module of these full customizations has independence and uncontrollability on the other hand; Thereby cause dependence test to become a kind of Black-box Testing; Can't improve its controlled and ornamental through inserting measurable type designing techniques commonly used such as scan chain; And then make conventional test methods only be left can use in the means that the circuit peripheral interface is directly observed its output, and this mode also has great complexity and high testing cost.
Consider the state of development of top said prior art; In order to adapt to the testing requirement of various PHY high-speed interface circuits; And obtain stable output and cheap relatively testing cost, need find a kind of effective method of testing to come the PHY high-speed interface circuit is tested specially.This method of testing should be accomplished: (1) test data has higher complexity, simulates various practical working situation as far as possible; (2) circuit-under-test is carried out the test of reality speed, cover the real work frequency of tested PHY high-speed interface circuit; (3) in circuit-under-test inside the input and output of PHY high-speed interface circuit are compared and judge; Outside the direct output chip of judged result; To avoid the lower and test limits that causes of interface pin or the parameter configuration of ATE tester table own; Control testing cost, and the stability of raising test result.
Summary of the invention
The object of the invention is to overcome existing existing above-mentioned one or more deficiencies of PHY high-speed interface circuit method of testing, thereby a kind of comprehensive, compatible all kinds PHY high-speed interface circuit is provided, circuit output pin and ATE testing apparatus are required low and/or be easy to the test circuit and the method for testing that realize and measure.
According to an aspect of the present invention, a kind of BIST automatic testing circuit to the PHY high-speed interface circuit is provided, has it is characterized in that said BIST automatic testing circuit comprises:
The BIST control circuit, it is used to generate output terminal test control signal, data signal under test and input end test control signal;
First selector, it is used for sending between the data-signal and selecting in output terminal working control signal, actual data to be sent and the output terminal test control signal that is generated by said BIST control circuit, test;
Second selector, it is used between input end working control signal and the input end test control signal by said BIST control circuit generation, selecting;
The output terminal of said first selector and said second selector is coupled to said PHY high-speed interface circuit,
Wherein, the output signal of said PHY high-speed interface circuit is by the input end of loopback to this high-speed interface circuit.
Preferably, when in normal mode of operation following time, said first selector is selected to export said output terminal working control signal and actual data to be sent to said PHY high-speed interface circuit; When in test pattern following time, the said output terminal test control signal that is used for test-purpose that said first selector selects to come from said BIST control circuit sends data-signal with test and exports said PHY high-speed interface circuit to.
Preferably, when in normal mode of operation following time, said second selector is selected to export said input end working control signal to said PHY high-speed interface circuit; When in test pattern following time, the input end test control signal that second selector is selected to come from the BIST control circuit exports said PHY high-speed interface circuit to.
Preferably; When in test pattern following time; After said PHY high-speed interface circuit receives output terminal test control signal, test transmission data-signal and the input end test control signal that comes from said first selector and said second selector; If said output terminal test control signal and said input end test control signal are shaken hands successfully; The output signal of then said PHY high-speed interface circuit is connected the input end that directly feeds back to this PHY high-speed interface circuit by outside inner at said high-speed interface circuit or through said high-speed interface circuit, as input end data-signal behind the loopback.
Preferably; The input end data-signal is transferred into said BIST control circuit behind the said loopback; Said BIST control circuit with its said loopback that receives after the expected data signal of input end data-signal and pre-stored compare, to judge the correctness of input end data-signal behind the loopback.
According to another aspect of the present invention, a kind of method of testing to the PHY high-speed interface circuit is provided, its step is following:
The BIST control circuit is set, makes it generate output terminal test control signal, data signal under test and input end test control signal;
Adopt first selector that output terminal working control signal, actual data to be sent and the output terminal test control signal that is generated by said BIST control circuit, test are sent data-signal and selected;
Adopt second selector to select to input end working control signal with by the input end test control signal that said BIST control circuit generates;
Export the selection result signal of said first selector and said second selector to said PHY high-speed interface circuit,
Wherein, the output signal of said PHY high-speed interface circuit is by the input end of loopback to this high-speed interface circuit.
Preferably, when in normal mode of operation following time, said first selector selects said output terminal working control signal and actual data to be sent to export said PHY high-speed interface circuit to as its selection result signal; When in test pattern following time, the said output terminal test control signal that is used for test-purpose that said first selector selects to come from said BIST control circuit sends data-signal with test and exports said PHY high-speed interface circuit to as its selection result signal.
Preferably, when in normal mode of operation following time, said second selector exports said input end working control signal to said PHY high-speed interface circuit as its selection result signal; When in test pattern following time, the input end test control signal that second selector will come from the BIST control circuit exports said PHY high-speed interface circuit to as its selection result signal.
Preferably; When in test pattern following time; After said PHY high-speed interface circuit receives the selection result signal that comes from said first selector and said second selector; If said output terminal test control signal and said input end test control signal are shaken hands successfully; The output signal of then said PHY high-speed interface circuit is connected the input end that directly feeds back to this PHY high-speed interface circuit by outside inner at said high-speed interface circuit or through said high-speed interface circuit, as input end data-signal behind the loopback.
Preferably; The input end data-signal is transferred into said BIST control circuit behind the said loopback; Said BIST control circuit with its said loopback that receives after the expected data signal of input end data-signal and pre-stored compare, to judge the correctness of input end data-signal behind the loopback.
Preferably, said BIST automatic testing circuit also comprises analog circuit parameters gated sweep chain, and it is used for before testing beginning, passing through the predetermined configurations parameter immigration scan register of the mode of scanning with tested PHY high-speed interface circuit and clock generating circuit.
Preferably, said BIST control circuit can generate the data-signal that is complementary with the output terminal control signal, and this data-signal is generation or self-defining at random.
Through adopting technical scheme of the present invention to make the present invention have following at least one advantage:
1. test data has higher complexity, can with at random or the mode of appointment simulate various practical working situation;
2. circuit-under-test is carried out the test of reality speed, cover the real work frequency of tested PHY high-speed interface circuit;
3. in circuit-under-test inside the input and output of PHY high-speed interface circuit are compared and judge; Outside the direct output chip of judged result; Avoiding the lower and test limits that causes of interface pin or the parameter configuration of ATE tester table own, the control testing cost, and improve the stability of test result;
4, test circuit of the present invention is organizational form with the module; Can under real fast mode, effectively test the PHY high-speed interface circuit; And judge and when EOT, directly output test result the correctness of its output that hardware spending is little; Control is simple, the complexity and the test duration of having reduced the employed test vector of ATE.
Description of drawings
Fig. 1 is the structured flowchart according to the test circuit that is directed against DDR (Double Data Rate, i.e. double data rate) PHY high-speed interface circuit of the first embodiment of the present invention.
Fig. 2 is the structured flowchart of the test circuit that is directed against HT (Hyper Transport, promptly ultra transmission) PHY high-speed interface circuit according to a second embodiment of the present invention.
Embodiment
Some term is used for indicating particular system component from start to finish in present specification.As person of skill in the art will appreciate that, can indicate identical parts with different titles usually, thereby present specification is unexpectedly schemed to distinguish, and those are just different rather than in the function aspects various parts nominally.In present specification, use a technical term " comprising ", " comprising " and " having " with open form, and so should it be interpreted as mean " including but not limited to ... "
Below in conjunction with the preferred embodiments of the present invention the present invention is described in further detail.
As previously mentioned, the present invention aims to provide a kind of BIST automatic testing circuit and method of testing thereof to the PHY high-speed interface circuit.
BIST test automatically is when design circuit, in circuit, to implant built-in self-test circuit (being about to this built-in self-test circuit congenerous circuit is integrated on the same chip); So just make after accomplishing chip manufacture; Can utilize the built-in self-test circuit that is added that chip itself is tested; So that the selftest function to be provided, reduce the degree of dependence of device detection to ATE ATE with this.This built-in self-test circuit has two kinds of mode of operations: a kind of is self-testing mode, and another kind is a normal mode of operation, and when normal mode of operation, self testing circuit is inoperative.BIST is a kind of DFT (Design for Testability, i.e. design for Measurability) technology, and it can be applied to nearly all circuit.
Adopt the BIST technology can realize following advantage:
1, can simplify external test facility.External test facility is only accomplished initialization built-in self-test logic and synchronous clock is provided under this test pattern, and the output of inspection comparison logic is to judge whether logic to be tested is normal.If the built-in self-test logical design has the clock of oneself, then external test facility only need be accomplished initialization and observation has error-free information to see off to get final product;
2, can improve testing efficiency.Because built-in testing logical and logic to be tested is work under identical environment, so can under the operate as normal speed of circuit to be tested, detect it, so both can improve test speed, has also checked the dynamic perfromance of circuit simultaneously;
3, be convenient to the maintenance and the debugging of electronic system.External circuit is the working method of control circuit easily, confirms whether the built-in self-test circuit fault has taken place.Therefore such integrated circuit has good self-test function and fault location function;
4, can reduce testing cost, improve wrong coverage rate, shorten the test required time and make things convenient for customer service.
The present invention has utilized the above-mentioned feature and advantage of BIST technology to realize just, describes each preferred implementation of the present invention below with reference to accompanying drawings in detail.
Fig. 1 shows the structured flowchart according to the test circuit that is directed against DDR PHY high-speed interface circuit of first embodiment of the invention.
As shown in Figure 1, DRAM (Dynamic Random Access Memory, dynamic RAM) controller 10 is for being used to generate the control signal of DDR bus and the signal generating circuit of data-signal under normal mode.
Two input ends of first selector 12 respectively with an output terminal coupling of the output terminal and the BIST control circuit 11 of dram controller 10; Two input ends of second selector 13 are coupled with another output terminal of dram controller 10 and another output terminal of BIST control circuit 11 respectively; The output terminal of first, second selector switch 12,13 all is coupled to DDR PHY 14; These two selector switchs are used to select the signal of dram controller 10 outputs and the signal of BIST control circuit 11 outputs.
DDR PHY 14 is tested PHY high-speed interface circuit, loopback (loopback) pattern that this circuit is built in having according to bus protocol, and opened.
PLL (Phase Lock Loop is phaselocked loop) circuit 15 is clock signal generating circuit, is used to BIST control circuit 11 and with DDR PHY 14 grades the clock signal under normal mode and the test pattern is provided.According to a preferred embodiment of the invention; The predetermined configurations parameter of PLL circuit 15 and DDR PHY 14 is imported through scan mode by the scan register shown in Fig. 1 16 and is offered PLL circuit 15 and DDR PHY 14 respectively, so that said PLL circuit 15 and DDR PHY 14 are carried out initial configuration.
When the test beginning; At first through ATPG (Automatic Test Pattern Genaration; Being that automatic resolution chart vector generates) scan pattern sequentially moves into aforementioned predetermined configurations parameter in the scan register 16 by analog circuit parameters gated sweep chain, then the predetermined configurations parameter that is moved into is input among PLL circuit 15 and the DDR PHY 14 respectively it is configured; After treating that configuration finishes, withdraw from scan pattern, get into the PHYBIST pattern.
In like manner, when being in normal mode of operation, second selector 13 selects output to come from the DDR bus input end working control signal of dram controller 10; And when being in the PHYBIST test pattern, second selector 13 selects output to come from the DDR bus input end test control signal of BIST control circuit 11.
When in PHYBIST test pattern following time, first selector 12 exports its selection result signal (the DDR output end of main test control signal and the data signal under test that are used for test-purpose that promptly come from BIST control circuit 11) to DDR PHY 14.Meanwhile, second selector 13 also exports its selection result signal (the DDR bus input end test control signal that promptly comes from BIST control circuit 11) among the DDR PHY 14 to.
When in PHYBIST test pattern following time; DDR PHY 14 comes from that first selector 12 transmits respectively with second selector 13 and after the DDR output end of main test control signal that is positioned at DDR bus both sides, data signal under test and the DDR bus input end test control signal that come receiving; If said DDR output end of main test control signal and DDR bus input end test control signal as handshake are successfully shaken hands, then said data signal under test just can successfully be transmitted by said DDR PHY 14.
When under the PHYBIST test pattern and above-mentioned shaking hands during success; Because the said DDR PHY 14 in the present embodiment is operated under the loopback mode; So the output signal of this DDR PHY 14 (being said data signal under test) is directly fed back to the input end of this DDR PHY 14 again; As input end data-signal behind the loopback; The input end data-signal passes DDR PHY 14 (shown in Reference numeral among Fig. 1 17) behind this loopback, is sent to simultaneously in BIST control circuit 11 and the dram controller 10 afterwards.
Need to prove at this; When in PHYBIST test pattern following time; Though dram controller 10 has received input end data-signal 17 behind the said loopback, because this dram controller 10 is in off position at present, so it does not carry out any response or processing to this signal 17.
After BIST control circuit 11 under the PHYBIST test pattern receives the loopback that said DDR PHY14 passes back after the input end data-signal; The expected data signal (being desirable right value) that the inner comparer (not shown in figure 1) of BIST control circuit 11 is stored in the storehouse of input end data-signal and BIST control circuit 11 after with received loopback compares (for example comparing one by one according to sequence order); With the correctness of the data-signal after the judgement loopback, thereby whether the IO port of test DDR Physical layer can produce error of transmission under fast mode.Afterwards, comparative result is recorded in the internal memory (not shown in figure 1) and finally as test results as a result the output circuit (not shown in figure 1) output to outside the entire chip.
Fig. 2 shows the second embodiment of the present invention.Wherein, HT (ultra transmission) bus controller 20 is for being used to generate HyperTransport (ultra transmission) control signal of bus and the signal generating circuit of data-signal under normal mode.
Two input ends of first selector 22 respectively with an output terminal coupling of the output terminal and the BIST control circuit 21 of HT bus controller 20; Two input ends of second selector 23 are coupled with another output terminal of HT bus controller 20 and another output terminal of BIST control circuit 21 respectively; The output terminal of first selector 22 is coupled to TX (transmission) PHY 241; The output terminal of second selector 23 is coupled to RX (reception) PHY 242; These two selector switchs are used to select the signal of HT bus controller 20 outputs and the signal of BIST control circuit 21 outputs.
PLL (Phase Lock Loop is phaselocked loop) circuit 25 is clock signal generating circuit, is used to BIST control circuit 21 and with RX PHY 242 grades the clock signal under normal mode and the test pattern is provided.According to a preferred embodiment of the invention; The predetermined configurations parameter of PLL circuit 25 and TX PHY 241/RX PHY 242 is imported through scan mode by the scan register shown in Fig. 2 26 and is offered PLL circuit 25 and TX PHY 241/RX PHY 242 respectively, so that said PLL circuit 25 and TX PHY 241/RX PHY 242 are carried out initial configuration.
When the test beginning; At first through ATPG (Automatic Test Pattern Genaration; Being that automatic resolution chart vector generates) scan pattern sequentially moves into aforementioned predetermined configurations parameter in the scan register 26 by analog circuit parameters gated sweep chain, then the predetermined configurations parameter that is moved into is input among PLL circuit 25 and the TX PHY 241/RX PHY 242 respectively it is configured; After treating that configuration finishes, withdraw from scan pattern, get into the PHYBIST pattern.
Under the PHYBIST pattern; HT bus controller 20 generates normal HT output end of main working control signal and normal data-signal to be sent, exports HT output end of main working control signal that is generated and normal data-signal to be sent to first selector 22 afterwards.Meanwhile, HT bus controller 20 also generates HT bus input end working control signal, and exports the HT bus input end working control signal that is generated to second selector 23.
In like manner, when being in normal mode of operation, second selector 23 is selected the HT bus input end working control signal of output from HT bus controller 20; And when being in the PHYBIST test pattern, second selector 23 selects output to come from the HT bus input end test control signal of BIST control circuit 21.
When in test pattern following time, (the HT output end of main test control signal that is used for test-purpose and the data signal under test that promptly come from BIST control circuit 21 export TX PHY 241 to first selector 22 with its selection result signal.Meanwhile, second selector 23 exports its selection result signal (the HT bus input end test control signal that is used for test-purpose that promptly comes from BIST control circuit 21) to RX PHY 242.
When in PHYBIST test pattern following time; TX PHY 241 and RX PHY 242 come from that first selector 22 transmits with second selector 23 and after the HT output end of main test control signal, data signal under test and the HT bus input end test control signal that come receiving respectively; If said HT output end of main test control signal and HT bus input end test control signal as handshake are successfully shaken hands, then said data signal under test just can successfully be transmitted with RX PHY 242 by said TX PHY 241.
When under the PHYBIST test pattern and after the above-mentioned success of shaking hands; Because the said TX PHY 241 in the present embodiment has externally carried out loopback with RX PHY 242 and has been connected,, the output signal of TX PHY 241 (being said data signal under test) becomes input end data-signal behind the loopback so directly being received the input port of RX PHY 242 again.The input end data-signal passes RX PHY 242 behind this loopback, is sent to simultaneously in BIST control circuit 21 and the HT bus controller 20 afterwards.
With first embodiment in like manner; When in PHYBIST test pattern following time; Though HT bus controller 20 has received input end data-signal behind the said loopback, because this HT bus controller 20 is in off position at present, so it does not carry out any response or processing to this signal.
When under the PHYBIST test pattern; BIST control circuit 21 receives behind the loopback that said RX PHY 242 passes back after the input end data-signal; The expected data signal of being stored in the storehouse of comparer (not shown among Fig. 2) with input end data-signal behind the received loopback and BIST control circuit 21 of BIST control circuit 21 inside (being desirable right value) compares (for example comparing one by one according to sequence order); With the correctness of the data-signal after the judgement loopback, thereby whether the IO port of test Physical layer can produce error of transmission under fast mode.Afterwards, comparative result is recorded in the internal memory (not shown among Fig. 2) and finally as test results as a result output circuit output to outside the entire chip.
Through the description of above-mentioned two embodiment, advantage of the present invention is tangible.The present invention has overcome the deficiency of traditional P HY high-speed interface circuit method of testing, and feasibility is good, the test result true and accurate.
What more than describe only is the preferred embodiments of the present invention, so that those skilled in the art can realize or use content disclosed by the invention.But above these embodiment are not exhaustive; To those skilled in the art; Various modifications to these disclosures all are conspicuous, and the technical scheme of the resulting within the spirit and scope of the present invention any modification of those skilled in the art, conversion, replacement all falls within protection scope of the present invention.In addition; Each step that comprises in the previous embodiment, the sequencing between each parts are just preferred; And the present invention is not limited to this; Those skilled in the art can adjust said sequence under the situation that does not deviate from spirit of the present invention, and resulting technical scheme still falls within protection scope of the present invention after the adjustment.
Claims (10)
1. BIST automatic testing circuit to the PHY high-speed interface circuit is characterized in that said BIST automatic testing circuit comprises:
The BIST control circuit, it is used to generate output terminal test control signal, data signal under test and input end test control signal;
First selector, it is used for sending between the data-signal and selecting in output terminal working control signal, actual data to be sent and the output terminal test control signal that is generated by said BIST control circuit, test;
Second selector, it is used between input end working control signal and the input end test control signal by said BIST control circuit generation, selecting;
The output terminal of said first selector and said second selector is coupled to said PHY high-speed interface circuit,
Wherein, the output signal of said PHY high-speed interface circuit is by the input end of loopback to this high-speed interface circuit.
2. BIST automatic testing circuit as claimed in claim 1 is characterized in that,
When in normal mode of operation following time, said first selector is selected to export said output terminal working control signal and actual data to be sent to said PHY high-speed interface circuit;
When in test pattern following time, the said output terminal test control signal that is used for test-purpose that said first selector selects to come from said BIST control circuit sends data-signal with test and exports said PHY high-speed interface circuit to.
3. BIST automatic testing circuit as claimed in claim 1 is characterized in that,
When in normal mode of operation following time, said second selector is selected to export said input end working control signal to said PHY high-speed interface circuit;
When in test pattern following time, the input end test control signal that second selector is selected to come from the BIST control circuit exports said PHY high-speed interface circuit to.
4. like claim 2 or 3 described BIST automatic testing circuits, it is characterized in that,
When in test pattern following time; After said PHY high-speed interface circuit receives output terminal test control signal, test transmission data-signal and the input end test control signal that comes from said first selector and said second selector; If said output terminal test control signal and said input end test control signal are shaken hands successfully; The output signal of then said PHY high-speed interface circuit is connected the input end that directly feeds back to this PHY high-speed interface circuit by outside inner at said high-speed interface circuit or through said high-speed interface circuit, as input end data-signal behind the loopback.
5. BIST automatic testing circuit as claimed in claim 4; It is characterized in that; The input end data-signal is transferred into said BIST control circuit behind the said loopback; Said BIST control circuit with its said loopback that receives after the expected data signal of input end data-signal and pre-stored compare, to judge the correctness of input end data-signal behind the loopback.
6. method of testing to the PHY high-speed interface circuit, its step is following:
The BIST control circuit is set, makes it generate output terminal test control signal, data signal under test and input end test control signal;
Adopt first selector that output terminal working control signal, actual data to be sent and the output terminal test control signal that is generated by said BIST control circuit, test are sent data-signal and selected;
Adopt second selector to select to input end working control signal with by the input end test control signal that said BIST control circuit generates;
Export the selection result signal of said first selector and said second selector to said PHY high-speed interface circuit,
Wherein, the output signal of said PHY high-speed interface circuit is by the input end of loopback to this high-speed interface circuit.
7. method of testing as claimed in claim 6 is characterized in that,
When in normal mode of operation following time, said first selector selects said output terminal working control signal and actual data to be sent to export said PHY high-speed interface circuit to as its selection result signal;
When in test pattern following time, the said output terminal test control signal that is used for test-purpose that said first selector selects to come from said BIST control circuit sends data-signal with test and exports said PHY high-speed interface circuit to as its selection result signal.
8. method of testing as claimed in claim 6 is characterized in that,
When in normal mode of operation following time, said second selector exports said input end working control signal to said PHY high-speed interface circuit as its selection result signal;
When in test pattern following time, the input end test control signal that second selector will come from the BIST control circuit exports said PHY high-speed interface circuit to as its selection result signal.
9. like claim 7 or 8 described method of testings, it is characterized in that,
When in test pattern following time; After said PHY high-speed interface circuit receives the selection result signal that comes from said first selector and said second selector; If said output terminal test control signal and said input end test control signal are shaken hands successfully; The output signal of then said PHY high-speed interface circuit is connected the input end that directly feeds back to this PHY high-speed interface circuit by outside inner at said high-speed interface circuit or through said high-speed interface circuit, as input end data-signal behind the loopback.
10. method of testing as claimed in claim 9; It is characterized in that; The input end data-signal is transferred into said BIST control circuit behind the said loopback; Said BIST control circuit with its said loopback that receives after the expected data signal of input end data-signal and pre-stored compare, to judge the correctness of input end data-signal behind the loopback.
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| CN104504209A (en) * | 2014-12-29 | 2015-04-08 | 浪潮(北京)电子信息产业有限公司 | PHY (Physical layer) characteristic simulation method and PHY characteristic simulation system |
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| CN112612264A (en) * | 2020-12-22 | 2021-04-06 | 北京时代民芯科技有限公司 | Serial port self-testing method in CAN bus controller |
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| CN104504209A (en) * | 2014-12-29 | 2015-04-08 | 浪潮(北京)电子信息产业有限公司 | PHY (Physical layer) characteristic simulation method and PHY characteristic simulation system |
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| CN105824351A (en) * | 2016-03-11 | 2016-08-03 | 福州瑞芯微电子股份有限公司 | Testable clock circuit of CPU and testing method for testable clock circuit |
| CN105823978A (en) * | 2016-03-11 | 2016-08-03 | 福州瑞芯微电子股份有限公司 | Universal chip testing clock circuit and testing method thereof |
| CN105823978B (en) * | 2016-03-11 | 2018-09-14 | 福州瑞芯微电子股份有限公司 | A kind of general chip testing clock circuit and its test method |
| CN105824351B (en) * | 2016-03-11 | 2018-12-18 | 福州瑞芯微电子股份有限公司 | The testability clock circuit and its test method of CPU |
| CN107800584A (en) * | 2016-09-07 | 2018-03-13 | 扬智科技股份有限公司 | The selftest method of second too networked physics layer circuit and selftest system |
| CN108226741A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of DMA self testing circuits |
| CN107329073A (en) * | 2017-07-31 | 2017-11-07 | 上海华力微电子有限公司 | A kind of pair of time domain dynamic frequency-conversion method of testing |
| CN107329073B (en) * | 2017-07-31 | 2019-11-26 | 上海华力微电子有限公司 | A kind of double time domain dynamic frequency-conversion test methods |
| CN112612264A (en) * | 2020-12-22 | 2021-04-06 | 北京时代民芯科技有限公司 | Serial port self-testing method in CAN bus controller |
| CN115866341A (en) * | 2022-12-05 | 2023-03-28 | 武汉凌久微电子有限公司 | HDMIPHY loopback test method and device based on FPGA |
| CN115866341B (en) * | 2022-12-05 | 2024-05-28 | 武汉凌久微电子有限公司 | Method and device for HDMIPHY loop-back test based on FPGA |
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