CN108226741A - A kind of DMA self testing circuits - Google Patents
A kind of DMA self testing circuits Download PDFInfo
- Publication number
- CN108226741A CN108226741A CN201611153107.5A CN201611153107A CN108226741A CN 108226741 A CN108226741 A CN 108226741A CN 201611153107 A CN201611153107 A CN 201611153107A CN 108226741 A CN108226741 A CN 108226741A
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- China
- Prior art keywords
- dma
- host
- information exchange
- exchange area
- self testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The present invention provides a kind of DMA self testing circuits that isolation test is carried out to FC AE ASM protocol processing chips host interface functionalities and FC protocol processes function.DMA self testing circuits include the control of self-test register, host dma interface readwrite tests and transmit and receive DMA tests and information exchange area.Wherein host dma interface readwrite tests circuit is connect with host dma interface, is transmitted and received DMA tests and is connect with transmission interface channel circuit.The present invention can carry out the transmission-receiving function and host interface DMA functions of FC AE ASM chip FC frames relatively independent isolation test.
Description
Technical field
The present invention relates to a kind of detection circuit, more particularly to a kind of DMA self testing circuits.
Background technology
Self testing circuit largely applies in chip design, can not needed to outside chip by self testing circuit function
In the case of enclosing circuit, the test to some basic functions of chip is completed.Chip basic function may determine that by self-test
It is whether normal.Fail for the chip of some functions complexity if there is self-test, failure of chip generally can not be positioned.
Invention content
The purpose of the present invention：A kind of DMA self testing circuits that can realize fault location are provided.
Technical scheme of the present invention：A kind of DMA self testing circuits, test circuit detection DMA channel function are special
It levies and is：Self testing circuit verifies whether every DMA channel function is normal by way of trying transmission data.
Preferably, the self testing circuit includes information exchange area and host reads BIST control modules, and host reads BIST
Control module sends DMA interface to PCIe and initiates DMA read request, and after host interface response, information exchange area receives next autonomous
The data of machine interface and storage, host judge that the DMA channel function is according to whether information exchange area is stored with DMA test datas
It is no normal.
Preferably, the self testing circuit includes information exchange area and host writes BIST control modules, and host writes BIST
Control module receives DMA interface to PCIe and initiates DMA write request, and after host interface response, host main memory, which receives, carrys out self-information
The test data of exchange area, host judge the DMA channel work(according to whether there being DMA test datas in corresponding core address space
Can whether normal.
Preferably, the self testing circuit includes information exchange area and sends BIST control modules, sends BIST controls
Module sends the test data in information exchange area by FC sendaisles, and test data is recorded by FC analyzers, according to
Whether FC analyzers, which receive test data, judges whether the DMA channel function is normal.
Preferably, the self testing circuit includes information exchange area and receives BIST control modules, receives BIST controls
Module stores the data of FC receiving channels to information exchange area, judges to be somebody's turn to do according to whether information exchange area receives test data
Whether DMA channel function is normal.
Preferably, the information exchange divides into two address spaces, and the data obtained from host are led to being sent to FC
The same address space of data sharing in road；The data that are obtained from FC channels and be sent to host the same address of data sharing it is empty
Between.
Beneficial effects of the present invention：Transmission data is tried to test to every DMA channel according to the pattern self testing circuit of configuration
Whether normal demonstrate,prove the channel function.The technical solution can complete host readwrite tests and transmit and receive test isolation test,
It can on earth be appeared in come positioning failure by these types of test pattern when chip breaks down bad positioning failure simultaneously
In sendaisle, receiving channel or host interface.
Description of the drawings
Fig. 1 is DMA self testing circuit structures.
Specific embodiment
Referring to Fig. 1, the mode register in BIST register control modules is configured by register interface for processor, it can
It is write with being configured to normal mode, sending BIST (self-test) pattern, reception BIST patterns, host reading BIST patterns and host
BIST patterns, while can enable and post with configuration testing length (being less than 4K) register and test address register and self-test
Storage, wherein testing length register are used to remove other all BIST patterns for receiving BIST patterns, test address register
It refers to the address in main memory, reads and writes BIST patterns for host, self-test enable signal is pulse signal, for removing reception
Other all BIST patterns of BIST patterns.
Under normal mode, self testing circuit does not work.Host (PCIe) transmission DMA interface is direct and sends DMA channel phase
Connection, host (PCIe) receive DMA interface and are directly connected with reception DMA channel.
Host reads BIST patterns：Machine-readable BIST patterns, configuration address register, Yi Jichang based on processing configuration test mode
Register is spent, while host prepares the test data of corresponding length in corresponding address space, configuration testing enables register.It surveys
It tries circuit to start to work, sending DMA interface to PCIe according to the information of configuration initiates DMA request, waits for host interface response, together
When receive the data from host interface write since 0 address in information exchange area successively until this DMA transfer complete.This mould
Formula can be completed to send host interface the test of DMA channel function.
Host writes BIST patterns：Processing configuration test mode writes BIST patterns, configuration address register, Yi Jichang for host
Spend register, for simultaneous processor in the high 4K address spaces setup test data in information exchange area, configuration testing enables register.
Test circuit is started to work, and test circuit receives DMA interface to PCIe according to the information of configuration and initiates DMA reception requests, waits for
Host interface responds, and when detecting that the DMA of host interface reads enable signal, the signal is controlled to be opened from the high 4K addresses in information exchange area
Beginning is successively read data and gives PCIeDMA receiving interfaces.This pattern can be completed to receive host interface the survey of DMA channel function
Examination.
Send BIST patterns：First processor by the data since 0 address in information exchange area of the test of needs successively
Information exchange area is write, according to the length configuration testing length register of test, configuration test mode is sends BIST patterns, together
When configuration testing enable register, send BIST circuit and start to work.It sends DMA channel circuit and receives to send BIST and send and belong to
Property, start according to DMA request is initiated, wherein request length is the self-test length of configuration, test circuit is received from transmission
The DMA request of DMA channel, while according to request length information, request length is successively read since 0 address in information exchange area
Data give send DMA channel drive corresponding data enable signal simultaneously.DMA channel is sent to pass through the data being connected to
FC-ASM modules are sent.This pattern can complete the test of sendaisle function.
Receive BIST patterns：Configuration test mode is handled to receive BIST patterns, receives the DMA of the reception DMA channel come
Request, drives according to the length information of request and reads enable signal, and the data of reading are once stored in information exchange by test circuit
The high 4K address spaces in area, the marking signal of one frame of driving reception gives BIST register control modules after being transmitted.This mould
Formula can complete the test of receiving channel function.
Claims (6)
1. a kind of DMA self testing circuits, test circuit detection DMA channel function, it is characterized in that：Self testing circuit passes through
The mode of examination transmission data verifies whether every DMA channel function is normal.
2. a kind of DMA self testing circuits according to claim 1, it is characterized in that：The self testing circuit includes information
Exchange area and host read BIST control modules, and host reads BIST control modules and sends DMA interface initiation DMA read request to PCIe,
After host interface response, information exchange area receives the data from host interface and storage, host is according to information exchange area
The no DMA test datas that are stored with judge whether the DMA channel function is normal.
3. a kind of DMA self testing circuits according to claim 1, it is characterized in that：The self testing circuit includes information
Exchange area and host write BIST control modules, and host writes BIST control modules and receives DMA interface initiation DMA write request to PCIe,
After host interface response, host main memory receives the test data from information exchange area, and host is according to corresponding core address sky
Between in whether have DMA test datas and judge whether the DMA channel function normal.
4. a kind of DMA self testing circuits according to claim 1, it is characterized in that：The self testing circuit includes information
Exchange area and transmission BIST control modules send BIST control modules and send the test data in information exchange area by FC and lead to
Road is sent, and is recorded test data by FC analyzers, is judged the DMA channel work(according to whether FC analyzers receive test data
Can whether normal.
5. a kind of DMA self testing circuits according to claim 1, it is characterized in that：The self testing circuit includes information
Exchange area and reception BIST control modules receive BIST control modules and store the data of FC receiving channels to information exchange area,
Judge whether the DMA channel function is normal according to whether information exchange area receives test data.
6. according to DMA self testing circuits described in claim 2 to 5 any claim, it is characterized in that：The information exchange area
It is divided into two address spaces, the data obtained from host and the same address space of data sharing for being sent to FC channels；Lead to from FC
The data that road obtains and the same address space of data sharing for being sent to host.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611153107.5A CN108226741B (en) | 2016-12-14 | 2016-12-14 | DMA self-test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611153107.5A CN108226741B (en) | 2016-12-14 | 2016-12-14 | DMA self-test circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108226741A true CN108226741A (en) | 2018-06-29 |
| CN108226741B CN108226741B (en) | 2020-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611153107.5A Active CN108226741B (en) | 2016-12-14 | 2016-12-14 | DMA self-test circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112162890A (en) * | 2020-09-24 | 2021-01-01 | 深圳市航顺芯片技术研发有限公司 | DMA pressure test method and device of MCU and storage medium |
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| US5668815A (en) * | 1996-08-14 | 1997-09-16 | Advanced Micro Devices, Inc. | Method for testing integrated memory using an integrated DMA controller |
| CN1797378A (en) * | 2004-12-24 | 2006-07-05 | 华为技术有限公司 | Method of data interchange by using mode of direct memory access |
| CN201465098U (en) * | 2009-07-14 | 2010-05-12 | 浪潮电子信息产业股份有限公司 | Multi-channel crossed DMA |
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102037453A (en) * | 2008-04-01 | 2011-04-27 | 苹果公司 | Central DMA with arbitrary processing functions |
| CN102567168A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | BIST (Built-in Self-test) automatic test circuit and test method aiming at PHY (Physical Layer) high-speed interface circuit |
| CN102928009A (en) * | 2012-09-05 | 2013-02-13 | 成都华太航空科技有限公司 | Test board for system of DMA-37A distance measuring equipment |
| CN103198001A (en) * | 2013-04-25 | 2013-07-10 | 加弘科技咨询(上海)有限公司 | Storage system capable of self-testing peripheral component interface express (PCIE) interface and test method |
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2016
- 2016-12-14 CN CN201611153107.5A patent/CN108226741B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5465332A (en) * | 1992-09-21 | 1995-11-07 | International Business Machines Corporation | Selectable 8/16 bit DMA channels for "ISA" bus |
| US5668815A (en) * | 1996-08-14 | 1997-09-16 | Advanced Micro Devices, Inc. | Method for testing integrated memory using an integrated DMA controller |
| CN1797378A (en) * | 2004-12-24 | 2006-07-05 | 华为技术有限公司 | Method of data interchange by using mode of direct memory access |
| CN102037453A (en) * | 2008-04-01 | 2011-04-27 | 苹果公司 | Central DMA with arbitrary processing functions |
| CN201465098U (en) * | 2009-07-14 | 2010-05-12 | 浪潮电子信息产业股份有限公司 | Multi-channel crossed DMA |
| CN101996265A (en) * | 2009-08-25 | 2011-03-30 | 安凯(广州)微电子技术有限公司 | Verification system and method for memory controller |
| CN102567168A (en) * | 2010-12-27 | 2012-07-11 | 北京国睿中数科技股份有限公司 | BIST (Built-in Self-test) automatic test circuit and test method aiming at PHY (Physical Layer) high-speed interface circuit |
| CN102928009A (en) * | 2012-09-05 | 2013-02-13 | 成都华太航空科技有限公司 | Test board for system of DMA-37A distance measuring equipment |
| CN103198001A (en) * | 2013-04-25 | 2013-07-10 | 加弘科技咨询(上海)有限公司 | Storage system capable of self-testing peripheral component interface express (PCIE) interface and test method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112162890A (en) * | 2020-09-24 | 2021-01-01 | 深圳市航顺芯片技术研发有限公司 | DMA pressure test method and device of MCU and storage medium |
| CN112162890B (en) * | 2020-09-24 | 2021-09-21 | 深圳市航顺芯片技术研发有限公司 | DMA pressure test method and device of MCU and storage medium |
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| Publication number | Publication date |
|---|---|
| CN108226741B (en) | 2020-06-09 |
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Effective date of registration: 20221010 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710000 Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |
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