CN102541772B - Signal acquisition device of memory bus - Google Patents
Signal acquisition device of memory bus Download PDFInfo
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- CN102541772B CN102541772B CN201110451208.1A CN201110451208A CN102541772B CN 102541772 B CN102541772 B CN 102541772B CN 201110451208 A CN201110451208 A CN 201110451208A CN 102541772 B CN102541772 B CN 102541772B
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Abstract
The invention provides a signal acquisition device of a memory bus, which comprises a detecting buffer unit and an acquisition unit, wherein the detecting buffer unit is suitable for acquiring signals of commands/an address bus and/or a data bus between a memory controller and memory chip and buffering and outputting the signals, and the acquisition unit is suitable or converting the buffered and output signals into data. By means of selection of input impedance of the detecting buffer unit, the signals of the memory bus are unaffected when signal acquisition is performed for the memory bus. The detecting buffer unit is a memory buffer or a DDRx register, and the acquisition unit is an FPGA (field programmable gate array), a high-speed oscilloscope or a logical analyzer. By the aid of the signal acquisition device, the problem of signal integrity when the FPGA performs signal acquisition for the memory bus is solved, so that a method for effectively acquiring memory signals can be carried out without interfering normal operation of an original memory system. Besides, the problem that caches of the high-speed oscilloscope and the logical analyzer can be only used for storing data at short time intervals is solved, so that the signals can be continuously acquired and outputted.
Description
Technical field
The present invention relates to high-performance computing sector and signals collecting field, relate in particular to a kind of signal pickup assembly of rambus.
Background technology
Gathering rambus signal is that hardware is caught the stored basis of visit in real time.Visit stored obtaining: can helper applications deviser improve memory access behavior, improve application software usefulness; Can help architecture Design person to find the defect of existing memory system, thereby improve perfect; Can also help hardware design personnel to analyze protocol memory, debug hardware.
Rambus comprises command line, address bus and data bus, connects Memory Controller Hub and memory grain, and overall width is about 100.Existing rambus acquisition mode, is all the mode that bypass is intercepted, and selects the somewhere of rambus as collection point, gathers with distinct device.Can be divided into two classes according to the difference of the equipment of use: the first kind is for being used high-speed oscilloscope or logic analyser; Equations of The Second Kind is for using high speed FPGA (Field-Programmable Gate Array, field programmable gate array).
High-speed oscilloscope or logic analyser can not only provide very high measuring accuracy, and its high resistant probe can will drop to minimum to the interference of memory system.But, its shortcoming also clearly: 1) the limited port number of oscillograph has determined that it can only intercept a few position in 100 rambus simultaneously.Although logic analyser can be intercepted the signal of bit wides up to a hundred simultaneously, be difficult in actual use find the position of fixing its probe in the mainboard of high integration, except the non-customized hardware with its particular measurement interface (as mid-bus).2) these two kinds of equipment bias toward collection signal, but cannot carry out effectively processing in real time to the information getting, and its buffer memory can only be stored the data in short period interval, the memory access information of catching that can not continue.3) high-speed oscilloscope and logic analyser are too expensive, and versatility is not strong.
Application number is that 200510008612.6 Chinese patent application has proposed the scheme that uses FPGA directly internal memory bus message to be caught.High speed FPGA is with its good customizability, can realize signals collecting, process and continue in real time a whole set of function of storage, and cost is relatively cheap, as shown in Figure 1.Its inferior position is, signals collecting ability is not so good as specialized equipment (oscillograph and logic analyser): direct FPGA connecting system is carried out to signals collecting, its input pin tends to long apart from the distance of measurement point, be equivalent to introduce Liao Yigechang branch in memory system, can cause serious problems of Signal Integrity in high frequency Xia Gai branch, not only correctly settling signal collection, also can disturb the normal operation of former memory system.
In order to address the above problem, application number is to have designed a set of system of utilizing bus monitor (bus monitor) to carry out program debug in the patented claim of EP19910102866, this bus monitor can controlling bus the information such as address, data, but its highest bus frequency being suitable for is 20MHz, does not provide concrete solution for the bus of higher frequency.Application number be US20060461567 Patent Application Publication a kind of system of monitoring rambus, but can only utilize counter to collect some statistical informations.
Summary of the invention
The object of this invention is to provide a kind of signal pickup assembly of rambus, can, not disturbing under the prerequisite of the normal operation of original memory system, carry out effective internal memory signals collecting.
For achieving the above object, according to one aspect of the invention, the signal pickup assembly that a kind of rambus is provided, comprising: survey buffer cell, be suitable for gathering command/address bus between Memory Controller Hub and memory grain and/or signal the Buffer output of data bus; And collecting unit, be suitable for the signal of described Buffer output to be converted into data; Wherein, select the input impedance of described detection buffer cell, make in the time that rambus is carried out to signals collecting, the signal of described rambus is substantially unaffected.
Optionally, described detection buffer cell is input high impedance; For example,, higher than 1M ohm.
Optionally, described collecting unit is also suitable for signal or the described data that storage of collected arrives as required.
Optionally, described detection buffer cell is core buffer.
Optionally, described detection buffer cell is DDRx register.
Optionally, described detection buffer cell is special chip any and core buffer, the similar level compatibility of DDRx register, input high resistant, Buffer output.
Optionally, described collecting unit is FPGA, high-speed oscilloscope or logic analyser.
Optionally, described detection buffer cell comprises: a DDRx register, is suitable for the signal on acquisition bus and address bus; The 2nd DDRx register, is suitable for the DQ signal in image data bus; The 3rd DDRx register, is suitable for the DQS signal in image data bus; Described signal pickup assembly also comprises: clock generation unit, be suitable for receiving the clock signal of memory system, described clock signal is carried out to frequency multiplication and phase modulation processing, obtain having two kinds of frequency doubling clocks of out of phase, send into described the 2nd DDRx register and the 3rd DDRx register, be respectively used to DQ and the DQS signal of image data bus.
Optionally, described detection buffer cell is deployed in the position near sampled point, thereby alleviates the problems of Signal Integrity that branch brings.
Optionally, described detection buffer cell is that point-to-point is connected with described collecting unit, is easy to carry out suitable termination coupling, thereby improves acquisition quality.
Optionally, the signal that described detection buffer cell is also suitable for collecting carries out shaping amplification.
Compared with prior art, the invention has the advantages that:
(1) solve the problems of Signal Integrity of appearance when FPGA carries out signals collecting to rambus, can not disturb under the prerequisite of the normal operation of original memory system, carry out the method for effective internal memory signals collecting.
(2) solved its buffer memory of high-speed oscilloscope and logic analyser and can only store the problem of the data in short period interval, can continue to catch and export.
(3) (input impedance of Memory Buffer is high, can reduce the interference to former memory system for DDRx register (DDRx Register) and core buffer; Meanwhile, as the special active device of memory system, can carry out certain shaping amplification to signal, improve collection effect.
Brief description of the drawings
Fig. 1 utilizes FPGA directly rambus to be carried out the apparatus structure schematic diagram of signals collecting in prior art;
Fig. 2 is the structural representation of the signal pickup assembly of a kind of rambus of providing in one embodiment of the invention;
Fig. 3 is the structural drawing of the rambus signal pickup assembly that provides in one embodiment of the invention;
Fig. 4 is the structural drawing of the rambus signal pickup assembly that provides in another embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing, the present invention is described in more detail.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
DDRx register and core buffer are two kinds of special chips that use in current server memory bar, for reducing the electrical load of memory bar itself; Wherein: DDRx register is for the production of RDIMM (Registered Dual In-line Memory Module, with the dual-in-line memory bar of register), order, address signal that Memory Controller Hub is sent cushion and are transmitted to the memory grain on memory bar; Core buffer is for the production of LRDIMM (Load-Reduced Dual In-line Memory Module, low load dual-in-line memory bar), it can also cushion the bi-directional data signal between Memory Controller Hub and memory grain except having the function of DDRx register.
Inventor finds through research, utilizing above-mentioned memory bar special chip is the signals collecting that DDRx register and core buffer carry out rambus, can well solve the problem that direct use FPGA gathers produced signal integrity, improve the correctness of image data.DDRx register and core buffer coordinate high speed FPGA can realize internal memory signals collecting, process and continue in real time a whole set of function of storage, than the solution of high-speed oscilloscope and logic analyser, not only complete function, use flexibly, and cost is very low.
A kind of signal pickup assembly of rambus is provided in one embodiment of the present of invention.As described in Figure 2, the signal pickup assembly 100 of this rambus comprises substantially:
Survey buffer cell 101, be suitable for gathering command/address bus between Memory Controller Hub and memory bar (comprising memory grain) and the signal of data bus, and ensure that the signal of former memory system is interference-free; And
Collecting unit 102, is suitable for receiving the signal of surveying buffer cell 101, and the signal receiving is processed and is converted into data.
Wherein, signal pickup assembly 101 directly gathers internal memory signal, and Buffer output, and fundamental purpose is to ensure signal integrity; Collecting unit 102 is collected the signal of 101 Buffer outputs, and signal is converted into data, and data are carried out to suitable processing, and can store as required data.
Concrete, in the present embodiment, surveying buffer cell 101 is DDRx register.
In existing DDRx (x is for Double Data Rate) memory system, command line and address bus are the one-way transmission of Memory Controller Hub to memory grain, data bus is the two-way transmission between Memory Controller Hub and memory grain, and the frequency of data bus is the twice of command line and address bus frequency, more than can reaching 800MHz.Because data bus frequency is the twice of command/address bus frequency, therefore use two kinds of DDRx registers, have the frequency DDRx register of normal work for acquisition bus and an address bus, another kind has the DDRx register of twice frequency of operation for image data bus.
In addition, because DQ (data-signal) and DQS (data strobe signal) have different clock phase (rising edge that is both is asynchronous), therefore should use two frequency doubling clocks of out of phase to gather by different DDRx registers, finally coordinate the command line signal collecting, can identify and wherein effectively write data or read data according to DDRx agreement.
Based on above-mentioned analysis, as shown in Figure 3, survey buffer cell and comprise DDRx register 201a, the signal on acquisition bus and address bus; DDRx register 201b, the DQ signal in image data bus; DDRx register 201c, the DQS signal in image data bus.It is FPGA 202 that the output of DDRx register 201a, 201b, 201c (being referred to as DDRx register 201) accesses respectively collecting unit.
For the clock of appropriate frequency being provided to detection buffer cell, signal pickup assembly 200 also comprises clock generation unit 203.Draw the clock signal of former memory system, through DDRx register, 201a sends into clock generation unit 203, in clock generation unit 203, carry out frequency multiplication and the phase modulation processing of clock signal, obtain having two kinds of frequency doubling clocks of out of phase, send into DDRx register 201b, 201c, be respectively used to DQ and the DQS of image data bus, and finally go out valid data according to DDRx protocol identification.
Preferably, DDRx register 201 should be deployed in the position very near apart from sampled point, reduces branch length, because DDRx register 201 is for input high resistant, can alleviate like this problems of Signal Integrity that branch brings as far as possible.
In this embodiment, DDRx register 201 is equivalent to " probe " of FPGA collection internal memory signal.Because this scheme is that bypass is intercepted, ensureing, under the condition of signal integrity, can not disturb the normal operation of former memory system.DDRx register 201 has the level standard with rambus compatibility, can identify the signal on rambus, and deposits output.Between 201 outputs of DDRx register and FPGA input, for point-to-point is connected, be easy to carry out suitable termination coupling, improve acquisition quality.FPGA receives after DQ and DQS, can be according to the command line collecting, and from DQ, identify and effectively write data or read data.
Because above-mentioned employing DDRx register is as surveying when buffer cell, need multi-disc combination to carry out, more loaded down with trivial details.
In another embodiment of the present invention, also provide a kind of signal pickup assembly of rambus.As shown in Figure 4, compared with a upper embodiment, it is core buffer that difference is to survey buffer cell, is used for gathering full memory bus by core buffer, comprises command line, address bus and data bus.
Core buffer has whole inputs of rambus, use single-chip can gather whole rambus signals, and can carry out good termination coupling to internal memory bus signals, reduce signal reflex, and the signal collecting is played to the effect that shaping is amplified.
In this embodiment, core buffer is equivalent to " probe " of FPGA collection internal memory signal equally, because core buffer can carry out good termination coupling to rambus, can avoid the interference to memory system.Core buffer has the level standard with rambus compatibility, can identify the signal on rambus, and Buffer output.Between core buffer output and FPGA input, for point-to-point is connected, be easy to carry out suitable termination coupling, improve acquisition quality.
In the above-described embodiments, signal quality through DDRx register or core buffer shaping improves greatly, and the point-to-point that is connected between DDRx register or core buffer and FPGA is connected, and has greatly alleviated problems of Signal Integrity, improve the correctness of FPGA image data.
The output of DDRx register or core buffer is passed to FPGA and carry out Data Collection, and carry out subsequent treatment; Its output can give high-speed oscilloscope too or logic analyser is sampled, as shown in Figure 4.
It is data interception and the signals collecting in Double Data Rate (DDR) system more than 400MHz that the said apparatus that the present invention proposes can be realized bus frequency.
Should be noted that and understand, in the situation that not departing from the desired the spirit and scope of the present invention of accompanying claim, can make various amendments and improvement to the present invention of foregoing detailed description.Therefore, the scope of claimed technical scheme is not subject to the restriction of given any specific exemplary teachings.
Claims (7)
1. a signal pickup assembly for rambus, comprising:
Survey buffer cell, be suitable for gathering command/address bus between Memory Controller Hub and memory grain and/or signal the Buffer output of data bus; With
Collecting unit, is suitable for the signal of described Buffer output to be converted into data;
Wherein, select the input impedance of described detection buffer cell, make in the time that rambus is carried out to signals collecting, the signal of described rambus is substantially unaffected;
Described detection buffer cell adopts DDRx register or adopts core buffer;
Described detection buffer cell is that point-to-point is connected with described collecting unit.
2. signal pickup assembly according to claim 1, wherein, described detection buffer cell is input high impedance.
3. signal pickup assembly according to claim 1, wherein, described collecting unit is also suitable for signal or the described data that storage of collected arrives as required.
4. signal pickup assembly according to claim 1, wherein,
Described collecting unit is FPGA, high-speed oscilloscope or logic analyser.
5. signal pickup assembly according to claim 1, wherein, when described detection buffer cell adopts DDRx register, described detection buffer cell comprises:
The one DDRx register, is suitable for the signal on acquisition bus and address bus;
The 2nd DDRx register, is suitable for the DQ signal in image data bus;
The 3rd DDRx register, is suitable for the DQS signal in image data bus;
Described signal pickup assembly also comprises:
Clock generation unit, be suitable for receiving the clock signal of memory system, described clock signal is carried out to frequency multiplication and phase modulation processing, obtain having two kinds of frequency doubling clocks of out of phase, send into described the 2nd DDRx register and the 3rd DDRx register, be respectively used to DQ and the DQS signal of image data bus.
6. signal pickup assembly according to claim 1, wherein, described detection buffer cell is deployed in the position near sampled point, thereby alleviates the problems of Signal Integrity that branch brings.
7. signal pickup assembly according to claim 1, wherein, the signal that described detection buffer cell is also suitable for collecting carries out shaping amplification.
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| CN105702301B (en) * | 2015-12-31 | 2019-04-26 | 深圳市德名利电子有限公司 | A kind of method and system and logic analyser grabbing flash memory useful signal |
| CN114201422A (en) * | 2020-09-18 | 2022-03-18 | 华为技术有限公司 | Buffer, storage equipment and memory bus signal processing method |
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| CN1828550A (en) * | 2005-02-28 | 2006-09-06 | 中国科学院计算技术研究所 | RAM accessing information real-time capturing device and method |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| CN202058149U (en) * | 2011-05-31 | 2011-11-30 | 江汉大学 | Two-channel data acquisition instrument based on peripheral component interconnect (PCI) bus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1828550A (en) * | 2005-02-28 | 2006-09-06 | 中国科学院计算技术研究所 | RAM accessing information real-time capturing device and method |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| CN202058149U (en) * | 2011-05-31 | 2011-11-30 | 江汉大学 | Two-channel data acquisition instrument based on peripheral component interconnect (PCI) bus |
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