CN102478622A - Field effect transistor (FET) test device and method - Google Patents
Field effect transistor (FET) test device and method Download PDFInfo
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- CN102478622A CN102478622A CN2010105586285A CN201010558628A CN102478622A CN 102478622 A CN102478622 A CN 102478622A CN 2010105586285 A CN2010105586285 A CN 2010105586285A CN 201010558628 A CN201010558628 A CN 201010558628A CN 102478622 A CN102478622 A CN 102478622A
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Abstract
The invention provides a field effect transistor (FET) test device, which comprises a data collector. Drain D of a to-be-tested FET Q is connected with VQ-D terminal of the data collector and connected with an alarm device through a resistor R1; two ends of the resistor R1 are connected to VR1-1 and VR1-2 terminals, respectively; source S is connected with VQ-S terminal and grounded; gate G is connected with VQ-G terminal and grounded through capacitors C1 and CT1 respectively; the capacitors C1 and CT1 are connected with terminal 2 of a switch SW1; terminal 3 of the switch SW1 is connected with terminal 4 of AC-DC converter through adjustable voltage controller, electrically connected with terminal 6 of the AC-DC converter and then grounded; terminals 1 and 3 of the AC-DC converter are connected with AC power supply; one end of the power supply is connected to the source S of the FET Q and grounded, and the other end is connected with the alarm device and grounded through capacitors C2 and C3. The invention has high-precision test result.
Description
Technical field
The present invention relates to a kind of proving installation and method thereof, relate in particular to a kind of devices and methods therefor in order to FET is tested.
Background technology
Conventional needle can only test MOS FET monomer to the test of FET (being MOSFET); Can not measure VGS (TH) and the RDS (ON) of MOSFET at the state of MOSFETon board; And fail to consider the influence that the MOSFET actual welding causes factors such as welding, impedances to the mainboard; Again, conventional needle to the test mode of MOSFET can not be in real time at the RDS of the MOSFET on the mainboard (being the D utmost point of MOSFET and the resistance between the S utmost point), IDS (being the D utmost point of MOSFET and the current value between the S utmost point) and PMOS (PMOS is the power consumption of MOSFET) along with the trend that the variation of VGS changes is detected.
As the VGS of the MOSFET on the mainboard (TH) (being conduction threshold) and RDS (ON) (being the D utmost point of MOSFET and the resistance between the S utmost point) when problem is arranged; Usual method is will MOSFET continued to heat and remove with instruments such as heat guns, the MOSFET monomer that disassembles is measured again.But MOSFET can make these two parameters of VGS (TH) and RDS (ON) change through after the heat.MOSFET may make the VGS (TH) and the RDS (ON) that lost efficacy originally become normally after through heating, causes the basic reason of problem to be covered.
Traditional testing apparatus can not be on mainboard the waveform of direct modeling data acquisition unit make the trend that RDS, IDS and the PMOS of MOSFET change along with the variation of VGS unusually; If do test with actual problematic data acquisition unit; Data acquisition unit possibly further worsen in test, and causes finding the true cause of data acquisition unit inefficacy.
Summary of the invention
In view of the above problems, the invention provides a kind of FET proving installation and method thereof.
In order to achieve the above object, the present invention has adopted following technical scheme: a kind of FET proving installation, and wherein, this device mainly comprises:
Data acquisition unit;
FET Q to be tested, its drain D is connected with the VQ-D end of this data acquisition unit, and this drain D also is connected with warning device through resistance R 1; These resistance R 1 two ends also are connected to VR1-1 end, the VR1-2 end of this data acquisition unit respectively, and its source S is connected with the VQ-S end of this data acquisition unit, and this source S ground connection; Its grid G is connected with the VQ-G end of this data acquisition unit; Through capacitor C 1, CT1 ground connection, this capacitor C 1, the unearthed end of CT1 are connected with 2 ends of switch SW 1 this grid G respectively, and 3 ends of this switch SW 1 are connected with 4 ends of AC-DC converter through the adjustable voltage controller; And 3 ends of this switch SW 1 and 6 ends of this AC-DC converter electrically connect; And 6 end ground connection of 3 ends of this switch SW 1 and this AC-DC converter, again, 1 end and 3 ends of this AC-DC converter are connected with AC power; And
Power supply, one of which end are connected to source S and the ground connection of this FET Q to be tested respectively, and its other end is connected with this warning device respectively, and this other end is respectively through capacitor C 2, C3 ground connection.
Preferable, the invention provides a kind of FET proving installation, wherein; This warning device comprises LED lamp and loudspeaker, and 1 end of this switch SW 1 electrically connects through 4 ends of control signal simulator and this AC-DC converter, and said power supply is 3.3 volts to 5 volts; 0 to 24 volt of adjustable voltage controller output voltage; Capacitor C 1, CT1, C2 and C3 are set to 0.47 microfarad, 4.7 microfarads, 0.47 microfarad and 0.1 microfarad respectively, and switch SW 1 is a single-pole double-throw switch (SPDT), and resistance R 1 is 0.1 ohm.
With respect to prior art; The invention provides a kind of FET proving installation; Can VGS (TH) and the RDS (ON) of the FET Q on the mainboard be measured; The result of test can take factors such as the welding of the FET Q on the mainboard, impedance into account in the lump; Can change along with VGS and the trend that changes is carried out real time record RDS (ON), IDS and the PMOS of FET Q, make VGS (TH) and RDS (ON) parameter of the FET Q that records avoid the influence of being heated, just can the analog controller waveform on mainboard make the trend that RDS, IDS and the PMOS of FET Q change along with the variation of VGS unusually; Also can avoid simultaneously controller to worsen, the precision as a result of test is high.
Description of drawings
Fig. 1 is a circuit diagram of the present invention
Embodiment
Please, be circuit diagram of the present invention with reference to shown in Figure 1.Said FET proving installation mainly comprises data acquisition unit 101, FET Q to be tested, control signal simulator 102, adjustable voltage controller 103 and AC-DC converter 104.
Wherein, said FET Q to be tested, its drain D is connected with the VQ-D end of this data acquisition unit 101; This drain D also is connected with warning device through resistance R 1, and this warning device comprises the LED lamp and the loudspeaker of series connection, and these resistance R 1 two ends are connected to VR1-1 end, the VR1-2 end of this data acquisition unit 101 respectively; This resistance R 1 is 0.1 ohm; The source S of said FET Q to be tested is connected with the VQ-S end of this data acquisition unit 101, and this source S ground connection, again; The grid G of FET Q to be tested is connected with the VQ-G end of this data acquisition unit 101, and this grid G is respectively through capacitor C 1, CT1 ground connection.
In addition; This capacitor C 1, the unearthed end of CT1 are connected with 2 ends of switch SW 1, and this capacitor C 1, CT1 can be set to 0.47 microfarad (being μ F), 4.7 microfarads, and 3 ends of this switch SW 1 are connected with 4 ends of AC-DC converter 104 through adjustable voltage controller 103; 0 to 24 volt of this adjustable voltage controller output voltage; And 3 ends of this switch SW 1 and 6 ends of this AC-DC converter 104 electrically connect, and 6 end ground connection of 3 ends of this switch SW 1 and this AC-DC converter 104, again; 1 end of this switch SW 1 electrically connects through 4 ends of control signal simulator 102 with this AC-DC converter 104; 1 end of this AC-DC converter 104 and 3 ends are connected with the AC power (not shown), and in present embodiment, this switch SW 1 is a single-pole double-throw switch (SPDT).
Moreover; Said power supply 105 can be set to 3.3 volts to 5 volts; These power supply 105 1 ends are connected to source S and the ground connection of this FET Q to be tested respectively; Its other end electrically connects with the loudspeaker of this warning device respectively, and this other end is respectively through capacitor C 2, C3 ground connection, and said capacitor C 2 and C3 can be set to 0.47 microfarad and 0.1 microfarad.
After beginning test; Switch SW 1 is received 3 places; The variation from low to high that adjustable voltage controller 103 can let the VGS value (being the grid G of field effect pipe Q and the magnitude of voltage between the source S) of FET Q continued by 0V～24V; And the value that three passage VQ-G ends, VQ-D end and the VQ-S end of data acquisition unit 101 are measured is respectively the VGS of FET Q; VDS and VR1, with VGS (TH) and the RDS (on) of calculating acquisition FET Q, and the RDS of FET Q, IDS and PMOS are along with VGS changes and the trend of variation.
SW1 is received 1 place, and control signal simulator 102 can be simulated the signal waveform that controller (not shown) on mainboard exports the reality of FET Q to.Because the magnitude of voltage of power supply 105 is adjustable between 3.3V～5V; Utilize with the control signal simulator 102 in the FET proving installation and simulate the abnormal signal that the controller on the mainboard of FET Q place sends; Carry out long period of experiments, can not grasp the defective of useful signal with regard to burning FET Q thereby avoided in side circuit, powering on.
The invention provides a kind of FET proving installation; Can VGS (TH) and the RDS (ON) of the FET Q on the mainboard be measured; The result of test can take factors such as the welding of the FET Q on the mainboard, impedance into account in the lump; The trend that can change along with VGS RDS (ON), IDS and the PMOS of FET Q and change is carried out real time record; Make VGS (TH) and RDS (ON) parameter of the FET Q that records avoid the influence of being heated; On mainboard, just can make the trend that RDS, IDS and the PMOS of FET Q change along with the variation of VGS, while also can avoid the controller on the mainboard to worsen unusually by the analog controller waveform, the precision as a result of test be high.
Claims (8)
1. a FET proving installation is characterized in that, this device mainly comprises:
Data acquisition unit;
FET Q to be tested, its drain D is connected with the VQ-D end of this data acquisition unit, and this drain D also is connected with warning device through resistance R 1; These resistance R 1 two ends are connected to VR1-1 end, the VR1-2 end of this data acquisition unit respectively, and its source S is connected with the VQ-S end of this data acquisition unit, and this source S ground connection; Its grid G is connected with the VQ-G end of this data acquisition unit; Through capacitor C 1, CT1 ground connection, this capacitor C 1, the unearthed end of CT1 are connected with 2 ends of switch SW 1 this grid G respectively, and 3 ends of this switch SW 1 are connected with 4 ends of AC-DC converter through the adjustable voltage controller; And 3 ends of this switch SW 1 and 6 ends of this AC-DC converter electrically connect; And 6 end ground connection of 3 ends of this switch SW 1 and this AC-DC converter, again, 1 end and 3 ends of this AC-DC converter are connected with AC power; And
Power supply, one of which end are connected to source S and the ground connection of this FET Q to be tested respectively, and its other end is connected with this warning device respectively, and this other end is respectively through capacitor C 2, C3 ground connection.
2. FET proving installation according to claim 1 is characterized in that this warning device comprises LED lamp and loudspeaker.
3. FET proving installation according to claim 1 is characterized in that, 1 end of this switch SW 1 electrically connects through 4 ends of control signal simulator and this AC-DC converter.
4. FET proving installation according to claim 1 is characterized in that, said power supply is 3.3 volts to 5 volts.
5. FET proving installation according to claim 1 is characterized in that, 0 to 24 volt of adjustable voltage controller output voltage.
6. FET proving installation according to claim 1 is characterized in that, capacitor C 1, CT1, C2 and C3 are set to 0.47 microfarad, 4.7 microfarads, 0.47 microfarad and 0.1 microfarad respectively.
7. FET proving installation according to claim 1 is characterized in that, switch SW 1 is a single-pole double-throw switch (SPDT).
8. FET proving installation according to claim 1 is characterized in that, resistance R 1 is 0.1 ohm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105586285A CN102478622B (en) | 2010-11-25 | 2010-11-25 | Field effect transistor (FET) test device and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105586285A CN102478622B (en) | 2010-11-25 | 2010-11-25 | Field effect transistor (FET) test device and method |
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| Publication Number | Publication Date |
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| CN102478622A true CN102478622A (en) | 2012-05-30 |
| CN102478622B CN102478622B (en) | 2013-12-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010105586285A Expired - Fee Related CN102478622B (en) | 2010-11-25 | 2010-11-25 | Field effect transistor (FET) test device and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109375085A (en) * | 2018-09-03 | 2019-02-22 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Power device health monitoring and early warning system and method in contactless board-level circuit |
| CN109425816A (en) * | 2017-08-16 | 2019-03-05 | 英飞凌科技股份有限公司 | Test MOS power switch |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426375A (en) * | 1993-02-26 | 1995-06-20 | Hitachi Micro Systems, Inc. | Method and apparatus for optimizing high speed performance and hot carrier lifetime in a MOS integrated circuit |
| CN1635390A (en) * | 2003-12-30 | 2005-07-06 | 上海贝岭股份有限公司 | Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor |
| CN200976035Y (en) * | 2006-12-07 | 2007-11-14 | 比亚迪股份有限公司 | Device for testing power field-effect transistor static parameter |
| US20090033355A1 (en) * | 2007-08-02 | 2009-02-05 | International Business Machines Corporation | Method And Apparatus To Measure Threshold Shifting Of A MOSFET Device And Voltage Difference Between Nodes |
-
2010
- 2010-11-25 CN CN2010105586285A patent/CN102478622B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5426375A (en) * | 1993-02-26 | 1995-06-20 | Hitachi Micro Systems, Inc. | Method and apparatus for optimizing high speed performance and hot carrier lifetime in a MOS integrated circuit |
| CN1635390A (en) * | 2003-12-30 | 2005-07-06 | 上海贝岭股份有限公司 | Test circuit of double Rutherford horizontal dual diffusion field-effect transistor conducting resistor |
| CN200976035Y (en) * | 2006-12-07 | 2007-11-14 | 比亚迪股份有限公司 | Device for testing power field-effect transistor static parameter |
| US20090033355A1 (en) * | 2007-08-02 | 2009-02-05 | International Business Machines Corporation | Method And Apparatus To Measure Threshold Shifting Of A MOSFET Device And Voltage Difference Between Nodes |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109425816A (en) * | 2017-08-16 | 2019-03-05 | 英飞凌科技股份有限公司 | Test MOS power switch |
| CN109425816B (en) * | 2017-08-16 | 2022-12-23 | 英飞凌科技股份有限公司 | Testing MOS power switches |
| CN109375085A (en) * | 2018-09-03 | 2019-02-22 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Power device health monitoring and early warning system and method in contactless board-level circuit |
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| CN102478622B (en) | 2013-12-04 |
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