CN102468248B - 使用预置填角保护覆晶封装 - Google Patents
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Abstract
一种管芯具有第一表面,位于第一表面对面的第二表面,和包括第一部分和第二部分的侧壁,其中相比于第二部分,第一部分更接近于第一表面。填角接触管芯的侧壁的第一部分并且包围管芯。工件通过焊料凸块与管芯接合,其中第二表面面向工件。第一底部填充胶填充管芯和工件之间的间隙,其中第一底部填充胶接触填角,并且其中第一底部填充胶和填角由不同的材料形成。
Description
技术领域
本发明涉及一种使用预置填角保护覆晶封装的方法及利用该方法制造的器件。
背景技术
在集成电路封装工艺中,可能使用倒装芯片接合将管芯接合到封装基板上,其中使用焊料凸块连接管芯上的接合焊盘和封装基板上的接合焊盘。回流焊料凸块之后,底部填充胶分布在管芯和封装基板之间的间隙中。然后硬化底部填充胶,因此焊料凸块被底部填充胶保护。
在传统覆晶封装中,通过毛细管底部填充点胶将底部填充胶填充到管芯和封装基板的间隙中。结果,取决于底部填充胶的粘度,尽管一些底部填充胶可能攀升在管芯的侧壁上,但是一般底部填充胶被限制在管芯侧壁的下部上,如果其曾经攀升到管芯的侧壁上。底部填充胶攀升到管芯侧壁的上部上的可能性比较小。底部填充胶根本不爬到管芯侧壁的任何部分上的情况也可能发生。管芯的拐角缺少底部填充胶会导致管芯中不同层之间分层以及管芯和底部填充胶之间分层的风险增加。
发明内容
针对现有技术的问题,本发明提供了一种器件,包括:管芯,所述管芯包括第一表面,所述第一表面对面的第二表面,和侧壁,所述侧壁包括第一部分和第二部分,所述第一部分比所述第二部分更接近所述第一表面;填角,接触所述管芯的所述侧壁的所述第一部分;工件,所述工件通过焊料凸块与所述管芯接合,其中所述第二表面面向所述工件;和第一底部填充胶,所述第一底部填充胶填充所述管芯和所述工件之间的间隙,其中所述第一底部填充胶接触所述填角,并且其中所述第一底部填充胶和所述填角由不同的材料形成。
根据本发明所述的器件,其中所述第一底部填充胶包括第一填料,所述第一填料具有第一百分比,所述填角包括具有第二百分比的第二填料,而且其中所述第二百分出大于所述第一百分比。
根据本发明所述的器件,其中所述填角基本上接触所述管芯的整个所有侧壁。
根据本发明所述的器件,其中所述第一底部填充胶接触所述管芯的所述侧壁的所述第二部分,并且接触所述填角。
根据本发明所述的器件,其中所述填角和所述第一底部填充胶不直接延伸到所述管芯的所述第一表面上方并且接触所述管芯的所述第一表面。
根据本发明所述的器件,其中所述第一底部填充胶具有第一热膨胀系数(CTE),而且其中所述填角具有小于所述第一CTE的第二CTE。
根据本发明所述的器件,其中所述第一底部填充胶具有第一杨式模量,而且其中所述填角具有与所述第一杨式模量不同的第二杨式模量。
根据本发明所述的一种器件,包括:管芯,包括第一表面和在所述第一表面对面的第二表面;和第一填充胶,所述第一填充胶在所述管芯的侧壁上并且包围所述管芯,其中所述第一底部填充胶基本上覆盖所述管芯的所有侧壁,并且其中基本上没有所述第一填充胶直接位于所述管芯的所述第一表面上方并且接触所述管芯的所述第一表面,或位于所述管芯的所述第二表面下方并且接触所述管芯的所述第二表面。
根据本发明所述的器件,还包括:工件,通过倒装芯片接合与管芯接合;和第二底部填充胶,填充所述管芯和所述工件之间的间隙,其中所述第二底部填充胶延伸到所述第一底部填充胶的侧壁上,并且其中所述第一底部填充胶和所述第二底部填充胶互相不同。
根据本发明所述的器件,其中所述第一底部填充胶和所述第二底部填充胶包括相同的基础材料,并且其中所述第一底部填充胶中的填料的百分比高于所述第二底部填充胶中的填料的百分比。
根据本发明所述的器件,其中所述第一底部填充胶中的填料和所述第二底部填充胶中的填料由相同的材料形成。
根据本发明所述的器件,其中所述第一底部填充胶的第一热膨胀系数(CTE)小于所述第二底部填充胶的第二CTE。
根据本发明所述的一种形成器件的方法,所述方法包括:沿着晶圆的划线实施第一切割以形成第一沟槽,其中所述划线使所述晶圆中的多个管芯互相间隔分离;填充填角材料到所述第一沟槽中;实施第一硬化以至少部分地硬化所述填角材料;在所述填角材料上实施第二切割以形成第二沟槽,在所述第二切割之后,部分所述填角材料剩余在各自所述第二沟槽的对立面上;以及将多个管芯互相分离,所述多个管芯的每一个都包括由所述填角材料的剩余部分形成的填角,其中所述填角与所述多个管芯的每一个的侧壁接触。
根据本发明所述的方法,还包括:通过倒装芯片接合将所述多个管芯之一接合到工件上;和滴涂第一底部填充胶到所述多个管芯之一和所述工件之间的间隙中,其中所述第一底部填充胶接触所述填角。
根据本发明所述的方法,其中所述第一沟槽和所述第二沟槽的每一个都延伸到所述晶圆的底面。
根据本发明所述的方法,其中所述第一沟槽和所述第二沟槽之一停止在所述晶圆的顶面和底面之间的中间水平。
根据本发明所述的方法,其中在填充所述填角材料的步骤之后,所述填角材料的顶面基本上与所述晶圆的顶面持平。
根据本发明所述的方法,其中在填充所述填角材料的步骤之后,所述填角材料的顶面低于所述晶圆的顶面。
根据本发明所述的方法,还包括,在实施所述第二切割的步骤之前,实施预硬化以部分地硬化所述填角材料。
根据本发明所述的方法,其中分离所述多个管芯的步骤包括在所述晶圆上实施晶背研磨。
附图说明
为了更好地理解实施例及其优点,现在将结合附图所进行的以下描述作为参考,其中:
图1到图3B示出了管芯侧壁上填角形成的中间阶段的顶视图和横截面视图。
图4示出了侧壁上形成有填角的管芯的透视图。
图5和图6示出了管芯侧壁上填角形成的中间阶段的横截面视图,其中填角覆盖侧壁的下部。
图7示出了部分侧壁上形成有填角的管芯的透视图。
图8到图13示出了管芯与封装基板接合的中间阶段的横截面视图。
图14到图17示出了管芯侧壁上形成填角的中间阶段的横截面视图,其中使用了研磨前切割工艺。
具体实施方式
下面,详细讨论本发明优选实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式,而不用于限制本公开的范围。
根据实施例提供了一种新颖的封装结构和其制造方法。阐述了实施例制造的中间阶段。然后讨论了实施例的变化。在各个视图和阐述的实施例中,相同的参考数字用于指示相同的元件。
图1A示出了晶圆20的顶视图。晶圆20包括多个管芯(在本领域也称为芯片)22,和使管芯22互相间隔的划线24。划线24包括在第一方向上延伸的部分和在垂直于第一方向的第二方向上的部分。管芯22可以包括例如包含互补金属氧化物半导体(CMOS)器件(未示出)的集成电路,其形成在晶圆20中的半导体衬底(未示出)上。
参考图1C,其为图1A所示结构的横截面视图,晶圆20粘附在胶带26上。在实施例中,晶圆20的背表面接触胶带26,其背表面可以是其中各自的半导体衬底(未示出)的背表面。在可替换的实施例中,晶圆20的前表面可以接触胶带26,所述前表面上可以包括焊料凸块44(图1C中未示出,参考图4)。
图1B是晶圆20的部分28(图1A)的放大图。实施第一管芯切割以沿着划线24切割,其中形成沟槽32以使管芯22互相分离。在第一管芯切割中,晶圆20中的所有划线24都被切割。如图1C中所示,尽管沟槽32可以分离管芯22为离散管芯,但是由于管芯22与胶带26粘附,因此管芯22仍然被固定在它们原来的位置上。沟槽32的底面可以与晶圆20的底面在同一水平,而且也可以稍微延伸到胶带26中以确保管芯22分离。另外,沟槽32的宽度W1小于划线24的宽度W2。在实施例中,宽度W1在约50μm和约200μm之间。然而,应该认识到,整个描述中所述的尺寸仅仅是实例,并且可以被改变,例如,如果使用不同的形成技术。管芯切割之后,实施清洗以除去第一管芯切割中产生的颗粒。
参考图2A,其为部分28(图1A)的顶视图,使用填角材料36填充沟槽32,其为液态,并且可以被硬化以转化成固体材料。填角材料36的顶面可以基本上与晶圆20的顶面持平,如图2B所示,其为图2A所示结构的横截面视图,横截面视图从图2A中的平面横截线2B-2B处得来。在实施例中,填角材料36是底部填充胶。在可替换的实施例中,可以使用其它材料如树脂、聚酰亚胺和聚对二甲苯。另外,填角材料36可以是介电材料。如图1C所示的沟槽32可以被填角材料36完全填充,如图2B所示,或部分填充。填充方法包括毛细管填充、丝网印刷、喷射、化学气相沉积(CVD)等等。填充之后,如图2B所示,填角材料36至少填充沟槽32的下部,而且可能填充整个沟槽32,使填角材料36的顶面与晶圆20的顶面持平。
填角材料36填充之后,可以实施预硬化工艺以部分地硬化填角材料36。例如,预硬化工艺的硬化时间可以小于完全硬化填角材料36所需最小时间的二分之一或三分之一。结构预硬化之后,填角材料36可以仍然是稍微粘合的,并且还没有完全固化。可选地,预硬化可以完全硬化填角材料36。在示例性实施例中,预硬化可以在约150℃下实施约10分钟。可以发现,胶带26不应该被预硬化损坏。因此,需要选择合适类型的胶带26,和/或需要降低预硬化温度到不损坏胶带26的温度。
参考图3A,其为晶圆20的部分28(图1A)的顶视图,实施第二管芯切割以产生填角材料36中的沟槽40。沟槽40的宽度W3小于填角材料36的宽度W1。在实施例中,比例W3/W1在约0.2和约0.8之间,而且也可以在约0.4和0.6之间。另外,沟槽40可以位于各自的填角材料36中间,因此位于各自沟槽40的对立边上的填角材料36的剩余部分具有相同的宽度W4。在示例性实施例中,宽度W1是大约100μm,并且宽度W3是大约50μm。因此,填角材料36的剩余部分(下文中称为填角42)的宽度W4可以是例如约25μm。图3B是图3A所示结构的横截面视图,横截面视图从图3A中的平面横截线3B-3B处得来。当到达沟槽40的底部时第二管芯切割结束,而且可能稍微超过填角材料36的底部。
随后,使管芯22从胶带26分离。图4示出管芯22之一的透视图。可以观察到填角42可以形成在管芯22的所有侧壁上并与其接触,而且环绕各自的管芯22。另外,填角42可以从与管芯22的顶面基本持平延伸到与管芯22的底面基本持平(也参考图3B)。在实施例中,填角42可以不直接延伸在管芯22的顶面上方并与其接触。另外,填角42可以不直接延伸到管芯22的底面下面并与其接触。焊料凸块44被示出位于管芯22的表面上。
图5到图7是根据可替换的实施例,示出填角形成的中间阶段的横截面视图,其中填角材料36部分地填充沟槽32。参考图5,图1A到图1C示出的第一管芯切割工艺实施之后,填角材料36填充到沟槽32的下部中,而沟槽32的上部没有填充。图5中结构的顶视图也可以呈现出与图2A所示基本相同。这个实施例中使用的填角材料36可以与图1A到3B所示实施例中使用的基本相同。
随后,如图6所示,填角材料36的预硬化之后,实施第二管芯切割以形成沟槽40。第二管芯切割的工艺条件和沟槽40的位置和宽度W3可以与图1A到3B所示的实施例中的基本相同。第二管芯切割之后,管芯22侧壁被填角42覆盖的部分具有厚度T1,其中管芯22的厚度是T2。在实施例中,比例T1/T2可以在约1/2和约4/5之间,尽管可以使用不同的比例。
实施第二管芯切割之后,管芯22和填角42可以从胶带26分离。图7示出了管芯22之一的透视图。可以观察到,在得到的结构中,填角42只覆盖管芯22侧壁的一部分(图7中的下部),而仍然有一部分管芯22的侧壁(图7中的上部)不被填角覆盖。
图8到图10示出了毛细管底部填充胶(填充剂)工艺的中间阶段的横截面视图。参考图8,管芯22与工件50接合,其可以是封装衬底,器件管芯,插件等等。焊料凸块44位于管芯22和工件50之间并接合管芯22和工件50。随后,液态的底部填充胶52填充到管芯22和工件50之间的空隙54中。由于毛细管效应,底部填充胶52填充空隙54的全部,而且可能接触填角42的侧壁42A。图9示出了底部填充胶42滴涂之后所得的结构。填角42的侧壁42A的一部分被底部填充胶52覆盖。得到的底部填充胶52的高度H与底部填充胶52的粘度有关,粘度越大,高度H越高。当从顶部观察时,底部填充胶52也可以围绕和接触至少填角42的下部。可选地,底部填充胶52覆盖填角42的整个侧壁42A。
随后,如图10所示,实施硬化以完全硬化填角42和底部填充胶52。在实施例中,在约130℃和约160℃的温度之间实施硬化例如约20分钟和约40分钟。取决于填角42和底部填充胶52的材料,硬化工艺可以使用不同的温度和持续时间。硬化工艺之后,填角42可以仍然接触管芯22的整个侧壁22A。另外,底部填充胶52接触填角42。填角42和底部填充胶52具有相兼容的特性,因此在硬化后很好地互相接合。底部填充胶52的顶端也可以与管芯22的顶面持平,可以与管芯22的底面持平,或可以在管芯22的顶面和底面之间的任何水平。由于填角42覆盖管芯22的整个侧壁22A,因此填角42和底部填充胶52一起为管芯22的所有侧壁22A和拐角提供保护。
在整个描述中,填角42和底部填充胶52都包括基础材料,其在硬化之前为液体。填角42和底部填充胶52都可能包括填料,其在硬化之前和之后是固体形式。在实施例中,填料可以包括陶瓷材料如二氧化硅,氧化铝等等。在图10示出的结构中,填角42和底部填充胶52可以由相同的材料形成,这表示它们的基础材料和填料基本相同。即使填角42和底部填充胶52包括相同类型的基础材料和相同类型的填料,如果它们中填料的百分比如重量百分比不同,则认为填角42和底部填充胶52是彼此不同的。在可替换的实施例中,填角42和底部填充胶52由不同的材料形成。例如,填角42可以由与底部填充胶52兼容的树脂组成。填角42和底部填充胶52的基础材料相同或不同。填角42中的填料和填角52中的填料也可以由相同的或不同的材料形成,尽管填角42中填料的(重量)百分比和底部填充胶52中填料的(重量)百分比可以相同或不同。在实施例中,填角42中的填料材料比底部填充胶52中的多。
填角42可以具有与管芯22中半导体衬底和介电材料(未示出)的CTE接近的热膨胀系数(CTE)。由于底部填充胶的CTE一般比管芯22中的衬底和介电材料的CTE大得多,因此为了接近衬底和介电材料的CTE,填角42的CTE可以小于底部填充胶52的CTE(并且大于半导体衬底的CTE)。在实施例中,填角42的CTE比底部填充胶52的CTE小2ppm/℃,5ppm/℃,或10ppm/℃。例如,填角42的CTE可以小于约22ppm/℃,小于20ppm/℃,或小于15ppm/℃,而底部填充胶52的CTE可以大于约20ppm/℃,大于约25ppm/℃,或甚至接近30ppm/℃。为了降低填角42的CTE,需要增加填角42中填料的百分比。在实施例中,填角42中填料的第一百分比(P1)与底部填充胶52中填料的第二百分比(P2)之间的比例P1/P2大于约1.1,大于约1.2,或甚至大于约1.5。
另外,填角42的杨式模量可以与底部填充胶52的杨式模量不同。在实施例中,填角42的杨式模量大于底部填充胶52的,而且填角42的杨式模量与底部填充胶52的杨式模量之间的差值大于约2GPa。在示例性的实施例中,填角42的杨式模量大于约15GPa,而底部填充胶52的杨式模量小于约13GPa。
图11示出了一个实施例,其中填角42覆盖管芯22的侧壁22A的顶部部分,而侧壁22A的底部部分没有被填角42覆盖,其中相比于表面22D,侧壁22A的顶部部分更接近表面22C。相反,底部填充胶52接触侧壁22A的底部部分。形成图11结构的封装工艺可以与图8和图9所示基本相同,除了填角42是使用图5和图6所示工艺形成的。图11示出了底部填充胶52硬化之后得到的结构。在这个实施例中,底部填充胶52至少接触填角42的底面,因此填角42和底部填充胶52接合在一起形成集成元件,其可以为管芯22的整个侧壁22A提供保护。当从顶部观察时,底部填充胶52可以包围和可以接触管芯22的侧壁22A的下部。
图12和13示出了通过非流动底部填充点胶工艺接合管芯22和工件50。参考图12,底部填充胶52首先滴涂在工件50上。其上形成有填角42的管芯22随后被放置在工件50上方。施加力,使得焊料凸块44穿透底部填充胶从而接触工件50上的接合焊盘(未示出)。图13示出了得到的结构。底部填充胶52,除了填充管芯22和工件50之间的间隙,也会向旁边挤压。选择底部填充胶52的数量和厚度使得底部填充胶52至少接触填角42的底部,而且可以接触填角42的侧壁42A。在预硬化的填角42和底部填充胶52硬化之后,随后对焊料凸块44实施回流。
也可以使用非流动底部填充点胶工艺接合(粘结)管芯22(如图7所示)到工件50上。也可以使用图11表示得到的结构。在得到的结构中,填角42覆盖管芯22的侧壁22A的顶部部分,而侧壁22A的底部部分不被填角42覆盖。接合工艺可以与图11到图12所示基本相同。
图14到图17根据又一其它实施例,示出了管芯22的侧壁上填角42形成的中间阶段的横截面视图。在这个实施例中,使用了研磨前切割(DBG)工艺。参考图14,实施第一管芯切割以形成沟槽32。图14所示结构的顶视图与图1A所示结构基本相同。在这个实施例中,沟槽32停止在晶圆20的顶面和底面之间的中间水平,而且不延伸到晶圆20的底部。在实施例中,沟槽32的深度D在管芯22的厚度T2的约5%和约90%之间。随后,如图15所示,填角材料36填充到沟槽32中,然后预硬化。相似地,填角材料36可以完全填充沟槽32,或只填充沟槽32的下部,而不填充沟槽32的上部。虚线60示出了填角材料36的示例性顶面。
随后,如图16所示,实施第二管芯切割。第二管芯切割可以到达填角材料36中与第一管芯切割基本相同的深度D,尽管深度也可以稍微不同。在第二管芯切割之后,形成填角42。随后,如图17中所示,从晶圆20移除胶带26。这时,管芯22仍然互相连接。随后实施晶背研磨直到管芯22分离,并且暴露出填角42。虚线部分示出在晶背研磨中晶圆20被移除的部分。在晶背研磨过程中,载具64可以与晶圆20的前部连接以在研磨中支持管芯22。晶背研磨之后,从载具64移除管芯22。在随后的工艺步骤中,管芯22与工件50连接,其可以与图8到图13所示基本相同。
根据实施例,管芯具有第一表面,第一表面对面的第二表面,侧壁包括第一部分和第二部分,其中相比于第二部分,第一部分更接近第一表面。填角接近管芯侧壁的第一部分并且包围管芯。工件通过焊料凸块与管芯连接,其中第二表面面向工件。第一底部填充胶填充位于管芯和工件之间的间隙,其中第一底部填充胶接触填角,并且其中第一底部填充胶和填角由不同的材料形成。
根据其它实施例,管芯具有第一表面和第一表面对面的第二表面。底部填充胶排布在管芯的侧壁上并且包围管芯,其中底部填充胶基本上覆盖管芯的全部侧壁。基本上没有底部填充胶直接位于管芯的第一表面上方并且接触第一表面,或在管芯的第二表面下方并且接触第二表面。
根据又一其它实施例,方法包括沿着晶圆的划线实施第一切割以形成第一沟槽,其中划线使晶圆中的多个管芯互相间隔分离;填充填角材料到第一沟槽中;实施硬化以至少部分地硬化填角材料;和穿过填角材料实施第二切割以形成第二沟槽,其中第二切割之后,部分填角材料剩余在各自第二沟槽的对立边上。多个管芯互相分离,多个管芯的每一个都具有由填角材料的剩余部分形成的填角。填角与多个管芯的每一个的侧壁接触。
尽管已经详细地描述了实施例及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。
Claims (18)
1.一种半导体器件,包括:
管芯,所述管芯包括第一表面,与所述第一表面相对的第二表面,和侧壁,所述侧壁包括第一部分和第二部分,所述第一部分比所述第二部分更接近所述第一表面;
填角,接触所述管芯的所述侧壁的所述第一部分;
工件,所述工件通过焊料凸块与所述管芯接合,其中所述第二表面面向所述工件;和
第一底部填充胶,所述第一底部填充胶填充所述管芯和所述工件之间的间隙,其中所述第一底部填充胶接触所述填角,并且其中所述第一底部填充胶和所述填角由不同的材料形成,所述填角的材料包括树脂、聚酰亚胺、聚对二甲苯或介电材料。
2.根据权利要求1所述的器件,其中,所述第一底部填充胶包括第一填料,所述第一填料具有第一百分比,所述填角包括具有第二百分比的第二填料,而且其中所述第二百分比大于所述第一百分比。
3.根据权利要求1所述的器件,其中,所述填角基本上接触所述管芯的整个所有侧壁。
4.根据权利要求1所述的器件,其中,所述第一底部填充胶接触所述管芯的所述侧壁的所述第二部分,并且接触所述填角。
5.根据权利要求1所述的器件,其中,所述填角和所述第一底部填充胶不直接延伸到所述管芯的所述第一表面上方但接触所述管芯的所述第一表面。
6.根据权利要求1所述的器件,其中,所述第一底部填充胶具有第一热膨胀系数(CTE),而且其中所述填角具有小于所述第一CTE的第二CTE。
7.根据权利要求1所述的器件,其中所述第一底部填充胶具有第一杨式模量,而且其中所述填角具有与所述第一杨式模量不同的第二杨式模量。
8.一种半导体器件,包括:
管芯,包括第一表面和与所述第一表面相对的第二表面;和
第一底部填充胶,所述第一底部填充胶在所述管芯的侧壁上并且包围所述管芯,其中所述第一底部填充胶基本上覆盖所述管芯的所有侧壁,并且其中基本上没有所述第一底部填充胶直接位于所述管芯的所述第一表面上方但接触所述管芯的所述第一表面,或位于所述管芯的所述第二表面下方并且接触所述管芯的所述第二表面;
工件,通过倒装芯片接合与管芯接合;和
第二底部填充胶,填充所述管芯和所述工件之间的间隙,其中所述第二底部填充胶延伸到所述第一底部填充胶的侧壁上,并且其中所述第一底部填充胶和所述第二底部填充胶互相不同,其中,形成所述第一底部填充胶的材料包括树脂、聚酰亚胺、聚对二甲苯或介电材料。
9.根据权利要求8所述的器件,其中,所述第一底部填充胶和所述第二底部填充胶包括相同的基础材料,并且其中所述第一底部填充胶中的填料的百分比高于所述第二底部填充胶中的填料的百分比。
10.根据权利要求9所述的器件,其中,所述第一底部填充胶中的填料和所述第二底部填充胶中的填料由相同的材料形成。
11.根据权利要求8所述的器件,其中,所述第一底部填充胶的第一热膨胀系数(CTE)小于所述第二底部填充胶的第二CTE。
12.一种形成半导体器件的方法,所述方法包括:
沿着晶圆的划线实施第一切割以形成第一沟槽,其中所述划线使所述晶圆中的多个管芯互相间隔分离;
填充填角材料到所述第一沟槽中;
实施第一硬化以至少部分地硬化所述填角材料;
在所述填角材料上实施第二切割以形成第二沟槽,在所述第二切割之后,部分所述填角材料剩余在各自所述第二沟槽的相对面上;以及
将多个管芯互相分离,所述多个管芯的每一个都包括由所述填角材料的剩余部分形成的填角,其中所述填角与所述多个管芯的每一个的侧壁接触;
通过倒装芯片接合将所述多个管芯之一接合到工件上;和
滴涂第一底部填充胶到所述多个管芯之一和所述工件之间的间隙中,其中所述第一底部填充胶接触所述填角;
其中,所述填角材料包括树脂、聚酰亚胺、聚对二甲苯或介电材料。
13.根据权利要求12所述的方法,其中,所述第一沟槽和所述第二沟槽的每一个都延伸到所述晶圆的底面。
14.根据权利要求12所述的方法,其中,所述第一沟槽和所述第二沟槽之一停止在所述晶圆的顶面和底面之间的中间水平。
15.根据权利要求12所述的方法,其中,在填充所述填角材料的步骤之后,所述填角材料的顶面基本上与所述晶圆的顶面持平。
16.根据权利要求12所述的方法,其中,在填充所述填角材料的步骤之后,所述填角材料的顶面低于所述晶圆的顶面。
17.根据权利要求12所述的方法,还包括:
在实施所述第二切割的步骤之前,实施预硬化以部分地硬化所述填角材料。
18.根据权利要求12所述的方法,其中,分离所述多个管芯的步骤包括在所述晶圆上实施晶背研磨。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9390060B2 (en) * | 2011-09-02 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods, material dispensing methods and apparatuses, and automated measurement systems |
US9245773B2 (en) | 2011-09-02 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packaging methods and structures thereof |
US8841752B1 (en) * | 2011-09-27 | 2014-09-23 | Xilinx, Inc. | Semiconductor structure and method for interconnection of integrated circuits |
US9355924B2 (en) * | 2012-10-30 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit underfill scheme |
KR102107961B1 (ko) | 2013-11-14 | 2020-05-28 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
JP2018006591A (ja) * | 2016-07-04 | 2018-01-11 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置およびその製造方法、並びに電子機器 |
KR20180014903A (ko) * | 2016-08-01 | 2018-02-12 | 삼성디스플레이 주식회사 | 전자 소자, 이의 실장 방법 및 이를 포함하는 표시 장치의 제조 방법 |
US11605662B2 (en) * | 2017-01-11 | 2023-03-14 | Sony Semiconductor Solutions Corporation | Imaging element, imaging device, electronic device, and method of manufacturing imaging element |
DE102018106434B4 (de) * | 2017-06-30 | 2023-05-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleiter-Bauelement und Verfahren zu dessen Herstellung |
US11121050B2 (en) * | 2017-06-30 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacture of a semiconductor device |
KR102072994B1 (ko) | 2017-12-06 | 2020-02-04 | 엘비세미콘 주식회사 | 사이드 몰딩을 이용한 반도체 패키지의 제조방법 |
FR3094561B1 (fr) * | 2019-03-25 | 2022-08-26 | Commissariat Energie Atomique | Procédé de fabrication d’une structure |
JP2021048205A (ja) * | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | 半導体装置の製造方法 |
KR20220083438A (ko) * | 2020-12-11 | 2022-06-20 | 삼성전자주식회사 | 반도체 패키지 |
US20230060756A1 (en) * | 2021-08-31 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package structure with multiple gap-filling layers and fabricating method thereof |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4433845A1 (de) * | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung |
US5581122A (en) * | 1994-10-25 | 1996-12-03 | Industrial Technology Research Institute | Packaging assembly with consolidated common voltage connections for integrated circuits |
US5866943A (en) * | 1997-06-23 | 1999-02-02 | Lsi Logic Corporation | System and method for forming a grid array device package employing electomagnetic shielding |
JP3655069B2 (ja) * | 1997-10-27 | 2005-06-02 | 沖電気工業株式会社 | 樹脂封止型半導体装置とその製造方法 |
JP2000150729A (ja) * | 1998-11-10 | 2000-05-30 | Hitachi Ltd | 樹脂封止半導体装置 |
US6245595B1 (en) * | 1999-07-22 | 2001-06-12 | National Semiconductor Corporation | Techniques for wafer level molding of underfill encapsulant |
US6338980B1 (en) * | 1999-08-13 | 2002-01-15 | Citizen Watch Co., Ltd. | Method for manufacturing chip-scale package and manufacturing IC chip |
US6316287B1 (en) * | 1999-09-13 | 2001-11-13 | Vishay Intertechnology, Inc. | Chip scale surface mount packages for semiconductor device and process of fabricating the same |
US6700209B1 (en) * | 1999-12-29 | 2004-03-02 | Intel Corporation | Partial underfill for flip-chip electronic packages |
KR100398716B1 (ko) * | 2000-06-12 | 2003-09-19 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 모듈 및 반도체 장치를 접속한 회로 기판 |
US6391683B1 (en) | 2000-06-21 | 2002-05-21 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package structure and process for fabricating the same |
US6372544B1 (en) | 2000-06-23 | 2002-04-16 | Advanced Micro Devices, Inc. | Method to reduce occurrences of fillet cracking in flip-chip underfill |
US6559537B1 (en) * | 2000-08-31 | 2003-05-06 | Micron Technology, Inc. | Ball grid array packages with thermally conductive containers |
US7011985B2 (en) * | 2001-06-16 | 2006-03-14 | Oticon A/S | Method for producing miniature amplifier and signal processing unit |
US6762509B2 (en) | 2001-12-11 | 2004-07-13 | Celerity Research Pte. Ltd. | Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material |
TWI282158B (en) | 2002-10-11 | 2007-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor package with ground-enhancing chip and fabrication method thereof |
US7105931B2 (en) * | 2003-01-07 | 2006-09-12 | Abbas Ismail Attarwala | Electronic package and method |
US7372151B1 (en) * | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
TWI250592B (en) * | 2004-11-16 | 2006-03-01 | Siliconware Precision Industries Co Ltd | Multi-chip semiconductor package and fabrication method thereof |
US7148560B2 (en) * | 2005-01-25 | 2006-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | IC chip package structure and underfill process |
US7838331B2 (en) | 2005-11-16 | 2010-11-23 | Denso Corporation | Method for dicing semiconductor substrate |
US20080036097A1 (en) * | 2006-08-10 | 2008-02-14 | Teppei Ito | Semiconductor package, method of production thereof and encapsulation resin |
US7824962B2 (en) * | 2008-01-29 | 2010-11-02 | Infineon Technologies Ag | Method of integrated circuit fabrication |
US20090309238A1 (en) * | 2008-06-13 | 2009-12-17 | Mun Leong Loke | Molded flip chip package with enhanced mold-die adhesion |
JP2010171125A (ja) * | 2009-01-21 | 2010-08-05 | Sharp Corp | 半導体装置およびその製造方法 |
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