CN102455972A - Programming device - Google Patents
Programming device Download PDFInfo
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- CN102455972A CN102455972A CN2010105289946A CN201010528994A CN102455972A CN 102455972 A CN102455972 A CN 102455972A CN 2010105289946 A CN2010105289946 A CN 2010105289946A CN 201010528994 A CN201010528994 A CN 201010528994A CN 102455972 A CN102455972 A CN 102455972A
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Abstract
The invention provides a programming device which is applied to testing and burning an electrically erasable and programmable read-only memory (EEPROM) and which comprises a peripheral component interconnect express (PCIE) type electric bridge, a microcontroller, a universal input/output connector and a burning connector. The PCIE type electric bridge receives a first signal and outputs a second signal. The microcontroller is coupled with the PCIE type electric bridge, and receives a second signal to provide an internal integrated circuit signal, a serial peripheral interface bus signal and a universal input/output signal, wherein the microcontroller performs burning on the internal integrated circuit signal and the serial peripheral interface bus signal to the correspondingly connected EEPROM through the burning connector and performs testing on the universal input/output signal to the correspondingly connected EEPROM through the universal input/output connector. The programming device improves the problems present in the prior art, saves the time and manpower costs and improves the production efficiency and the burning quality.
Description
Technical field
The present invention relates to a kind of programmer, especially a kind of programmer that is used to test with burning.
Background technology
General industry is in the server production run; The EEPROM or the majorities such as EEPROM of serial peripheral interface pattern that are used for the internal integration circuit pattern of mainboard are to carry out the off-line burning with the manual work mode, and after the off-line burning is accomplished, are equipped with the color mark with the manual work mode again or label.Owing to be to adopt the off-line burning in process of production, and human cost is high, and this mode is difficult to guarantee absolutely do not have error.
Produce at present line to burning after the quality of EEPROM very pay attention to; Therefore the covering demand to test point almost reaches 100%; If but test for ease and on some bus, add extra test point, this is very unreasonable as far as signal integrity, but when running into some problem; Also be difficult to avoid needs to add extra test point, otherwise problem more is difficult to resolve certainly.
How to realize the burning of EEPROM and can reduce test point to EEPROM, what can guarantee simultaneously again to test normally carries out, and this is one has problem to be overcome.
Summary of the invention
In order to overcome above-mentioned defective, the present invention proposes a kind of programmer, is applicable to test and burning one EEPROM.Said programmer comprises: a quick peripheral hardware interconnect standard pattern electric bridge receives one first signal, and exports a secondary signal; One microcontroller couples said quick peripheral hardware interconnect standard pattern electric bridge, receives said secondary signal and an internal integration circuit signal, a serial peripheral bus interface signal and a general input/output signal are provided; One general input and output connector couples said microcontroller, in order to connect said EEPROM; And one burning use connector, couple said microcontroller, in order to connect said EEPROM.Wherein, Said microcontroller carries out said internal integration circuit signal, said serial peripheral bus interface signal burning to the said EEPROM of corresponding connection, and said general input/output signal is tested the said EEPROM of corresponding connection through said general input and output connector.
In one embodiment of this invention, said programmer is applicable to the EEPROM of internal integration circuit pattern or the EEPROM of serial peripheral interface pattern.
In one embodiment of this invention, with a signal wire that is used to test said EEPROM on the said general input and output connector relevant for two pins of said general input/output signal.
In one embodiment of this invention, if during the said signal wire of test, said microcontroller is judged about output in two pins of said general input/output signal and input coupling, and then the test of said signal wire is normal.
In one embodiment of this invention, said first signal is quick peripheral hardware interconnect standard pattern signal.
In one embodiment of this invention, said first signal is to see through the quick peripheral hardware interconnect standard pattern signal that a USB port is transmitted.
In one embodiment of this invention, said secondary signal is a kind of signal of synchronizing sequence data protocol and the combination of look-at-me.
In one embodiment of this invention; Said programmer also comprises the golden finger of a quick peripheral hardware interconnect standard pattern; Wherein said golden finger couples said quick peripheral hardware interconnect standard pattern electric bridge, transmits said first signal to said quick peripheral hardware interconnect standard pattern electric bridge through said golden finger.
In one embodiment of this invention; Said programmer also comprises a joint test working group connector; And when said programmer comprises a plurality of microcontroller; One joint test working group signal sees through said joint test working group connector and connects each microcontroller, forms tandem burning pattern.
Programmer of the present invention is tested the EEPROM (EEPROM) of corresponding connection because of adopting general input/output signal; And internal integration circuit signal, serial peripheral bus interface signal are carried out burning to the EEPROM of corresponding connection; Therefore save time in process of production and human cost, can enhance productivity and burning quality.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs., elaborates as follows.
Description of drawings
Fig. 1 is the calcspar according to the programmer of the embodiment of the invention.
Fig. 2 is the calcspar according to the programmer of another embodiment of the present invention.
Fig. 3 is the calcspar according to the programmer of another embodiment of the present invention.
Reference numeral:
100,200,300: programmer; 110,210:PCIE pattern electric bridge;
120: microcontroller; 140: connector is used in burning;
220: the first microcontrollers; 230: the second microcontrollers;
Connector is used in burning in 240: the first; Connector is used in burning in 260: the second;
150:EEPROM; The golden finger of 160:PCIE pattern;
280: joint test working group connector; IS1: first group of output signal;
IS2: second group of output signal; JTAG: joint test working group signal;
Sig_1: first signal; Sig_2, Sig_21: secondary signal;
Sig_22: the 3rd signal; I2C: internal integration circuit signal;
SPI: serial peripheral bus interface signal; GPIO: general input/output signal;
GPIO1: the first general input/output signal; GPIO2: the second general input/output signal;
250: the first general input and output connectors; 270: the second general input and output connectors;
130: general input and output connector.
Embodiment
Now please with reference to accompanying drawing, wherein shown in only for the preferred embodiments of the present invention are described, but not limited to its category.
Fig. 1 is the calcspar according to the programmer of the embodiment of the invention.Please with reference to Fig. 1; Programmer 100 can comprise that quick peripheral hardware interconnect standard (Peripheral Component Interconnect Express abbreviates PCIE as) pattern electric bridge 110, microcontroller 120, general input and output connector 130 and burning are with connector 140.Microcontroller 120 couples PCIE pattern electric bridge 110.General input and output connector 130 couples microcontroller 120, in order to connect an EEPROM to be measured (Electrically Erasable Programmable Read-Only Memory abbreviates EEPROM as) 150.Burning also is coupled to microcontroller 120 with connector 140, likewise is used for connecting EEPROM150.
Hold above-mentionedly, PCIE pattern electric bridge 110 receives the first signal Sig_1, and output secondary signal Sig_2.PCIE pattern electric bridge 110 can be supported hot-swappable property, also support three kinds of voltages be respectively+3.3V, 5V and+12V.The first signal Sig_1 can be a PCIE pattern signal, or sees through the PCIE pattern signal that a USB port is transmitted, and wherein PCIE pattern signal can promote the speed of inner all buses.Secondary signal Sig_2 can be a kind of signal of synchronizing sequence data protocol and the combination of look-at-me, is applicable to that doing data between PCIE pattern electric bridge 110 and the microcontroller 120 transmits.Microcontroller 120 receives secondary signal Sig_2 and an internal integration circuit (Inter-Integrated Circuit, I is provided
2C) signal I2C, a serial peripheral bus interface (Serial Peripheral Interface Bus) signal SPI and a general input/output signal GPIO.Wherein, internal integration circuit signal I2C is a kind of signal of tandem communication bus, can be used in many client/servers.Serial peripheral bus interface signal SPI is a kind of signal of synchronizing sequence data protocol.Microcontroller 120 can be done control to a certain pin through general input/output signal GPIO, can be through reading the height of certain pin level.Microcontroller 120 can carry out burning with internal integration circuit signal I2C, serial peripheral bus interface signal SPI to the EEPROM 150 of corresponding connection with connector 140 through burning; Microcontroller 120 can be tested general input/output signal GPIO through general input and output connector 130 to the EEPROM 150 of corresponding connection.Therefore, programmer 100 can be used for burning EEPROM 150 and the test EEPROM 150.
It should be noted that aforesaid EEPROM 150 can be the EEPROM of internal integration circuit signal I2C pattern or the EEPROM of serial peripheral bus interface signal SPI pattern.Can be with a signal wire that is used to test EEPROM 150 on the general input and output connector 130 relevant for two pins of general input/output signal GPIO.When this signal wire of test; If microcontroller 120 is judged about output in two pins of general input/output signal GPIO and input coupling (the coupling here is meant approximately and equates); Then the test of said signal wire is normal, therefore can reduce test point to EEPROM.
Via above-mentioned explanation; Internal integration circuit signal I2C, serial peripheral bus interface (Serial Peripheral Interface Bus) signal SPI that programmer 100 can utilize microcontroller 120 to be provided carry out burning on the line to the EEPROM 150 at corresponding connectors interface; The general input/output signal GPIO that programmer 100 can utilize microcontroller 120 to be provided carries out testing on the line to the EEPROM150 at corresponding connectors interface.Present embodiment can solve the defective of off-line burning in the prior art, also practices thrift human cost.
We can increase microcontroller and number of connectors, implement the present invention with enumerating another embodiment so that present technique field personnel can see through the instruction of embodiment, to quicken test and the burn job of EEPROM.
Fig. 2 is the calcspar according to the programmer of another embodiment of the present invention.Please with reference to Fig. 2, programmer 200 can comprise PCIE pattern electric bridge 210, first microcontroller 220, second microcontroller, 230, first general input and output connector 250, the second general input and output connector 270 and first burning with connector 240 and second burning with connector 260.First microcontroller 220 couples PCIE pattern electric bridge 210.Second microcontroller 230 also couples PCIE pattern electric bridge 210.First general input and output connector 250, the second general input and output connector 270 couples first microcontroller 220 respectively and 230, the first burnings of second microcontroller are coupled to first microcontroller 220 and second microcontroller 230 with connector 240, second burning respectively with connector 260.
Hold above-mentionedly, PCIE pattern electric bridge 210 receives the first signal Sig_1, and output secondary signal Sig_21 and the 3rd signal Sig_22.PCIE pattern electric bridge 210 can be supported hot-swappable property, also support three kinds of voltages be respectively+3.3V, 5V and+12V.The first signal Sig_1 can be a PCIE pattern signal, or sees through the PCIE pattern signal that a USB port is transmitted, and wherein PCIE pattern signal can promote the speed of inner all buses.Secondary signal Sig_21 and the 3rd signal Sig_22 can be a kind of signal of synchronizing sequence data protocol and the combination of look-at-me, are applicable to that doing data between the PCIE pattern electric bridge 210 and first microcontroller 220 transmits.First microcontroller 220 receives secondary signal Sig_21 and the first group of output signal IS1 and the first general input/output signal GPIO1 is provided.Second microcontroller 230 receives the 3rd signal Sig_22 and the second group of output signal IS2 and the second general input/output signal GPIO2 is provided.Wherein the output signal of each group microcontroller comprises an internal integration circuit signal and a serial peripheral bus interface signal.Wherein, the internal integration circuit signal is a kind of signal of tandem communication bus, can be used in many client/servers.Serial peripheral bus interface signal is a kind of signal of synchronizing sequence data protocol.
What deserves to be mentioned is that programmer 200 can also comprise a joint test working group (Joint TestAction Group) connector 280.This joint test working group connector 280 is in order to transmit a signal JTAG of joint test working group.Each microcontroller can see through the signal JTAG of this joint test working group and connect; Because have only a signal line; The communication protocol of first microcontroller 220 and second microcontroller 230 is the tandem transmission; Read, control first microcontroller 220 and second microcontroller 230 through being written into the different commands pattern, thereby form a tandem burning pattern.So the practice can reduce the quantity of the signal JTAG of joint test working group, and makes things convenient for burning.Wherein, the signal JTAG of joint test working group connects the quantity of microcontroller, does not limit its scope at this.Present embodiment can be accelerated test and the burning quantity of EEPROM, solves the defective of off-line burning in the prior art, also practices thrift human cost, enhances productivity significantly.
Fig. 3 is the calcspar according to the programmer of another embodiment of the present invention.Please with reference to Fig. 3; Programmer 300 is similar to the programmer 100 of Fig. 1; Difference can also comprise the golden finger 160 of a PCIE pattern at programmer 300; Wherein the golden finger 160 of PCIE pattern couples PCIE pattern electric bridge 110, through golden finger 160 transmission first signal Sig_1 to the PCIE pattern electric bridge 110 of PCIE pattern.
Though programmer has been depicted several possible kenels in the foregoing description; But the person of ordinary skill in the field should know; Each manufacturer is all different for the design of programmer, and therefore application of the present invention is when being not restricted to the possible kenel of this kind.In other words, so long as the burning of EEPROM can onlinely be carried out, maybe can be reduced test point to EEPROM with test, just be to have met spirit of the present invention place.
In sum; Programmer of the present invention is because of adopting online burning and test; Use general input/output signal that the EEPROM of corresponding connection is tested, and internal integration circuit signal, serial peripheral bus interface signal are carried out burning to the EEPROM of corresponding connection, therefore save time in process of production and human cost; Can reduce test point to EEPROM, and then enhance productivity and burning quality.
Though the present invention discloses as above with embodiment; But it is not in order to limit the present invention; Any person of ordinary skill in the field; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that accompanying claims defines.
Claims (9)
1. a programmer is applicable to test and burning one EEPROM, it is characterized in that said programmer comprises:
One quick peripheral hardware interconnect standard pattern electric bridge receives one first signal, and exports a secondary signal;
One microcontroller couples said quick peripheral hardware interconnect standard pattern electric bridge, receives said secondary signal and an internal integration circuit signal, a serial peripheral bus interface signal and a general input/output signal are provided;
One general input and output connector couples said microcontroller, in order to connect said EEPROM; And
Connector is used in one burning, couples said microcontroller, in order to connect said EEPROM;
Wherein, Said microcontroller carries out burning with said internal integration circuit signal, said serial peripheral bus interface signal to the said EEPROM of corresponding connection with connector through said burning, and said microcontroller is tested said general input/output signal through said general input and output connector to the said EEPROM of corresponding connection.
2. programmer according to claim 1 is characterized in that, said programmer is applicable to the EEPROM of internal integration circuit pattern or the EEPROM of serial peripheral interface pattern.
3. programmer according to claim 1 is characterized in that, with a signal wire that is used to test said EEPROM on the said general input and output connector relevant for two pins of said general input/output signal.
4. programmer according to claim 3 is characterized in that, if during the said signal wire of test, said microcontroller is judged about output in two pins of said general input/output signal and input coupling, and then the test of said signal wire is normal.
5. programmer according to claim 1 is characterized in that, said first signal is quick peripheral hardware interconnect standard pattern signal.
6. programmer according to claim 5 is characterized in that, said first signal is to see through the quick peripheral hardware interconnect standard pattern signal that a USB port is transmitted.
7. programmer according to claim 1 is characterized in that, said secondary signal is a kind of signal of synchronizing sequence data protocol and the combination of look-at-me.
8. programmer according to claim 1; It is characterized in that; Said programmer also comprises the golden finger of a quick peripheral hardware interconnect standard pattern; Wherein said golden finger couples said quick peripheral hardware interconnect standard pattern electric bridge, transmits said first signal to said quick peripheral hardware interconnect standard pattern electric bridge through said golden finger.
9. programmer according to claim 1; It is characterized in that; Said programmer also comprises a joint test working group connector; And when said programmer comprised a plurality of microcontroller, a joint test working group signal saw through said joint test working group connector and connects each microcontroller, formed tandem burning pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105289946A CN102455972A (en) | 2010-10-25 | 2010-10-25 | Programming device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105289946A CN102455972A (en) | 2010-10-25 | 2010-10-25 | Programming device |
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| CN102455972A true CN102455972A (en) | 2012-05-16 |
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| CN2010105289946A Pending CN102455972A (en) | 2010-10-25 | 2010-10-25 | Programming device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103309782A (en) * | 2013-06-28 | 2013-09-18 | 广州视源电子科技股份有限公司 | Burning and testing integrated system |
| FR3009633A1 (en) * | 2013-08-08 | 2015-02-13 | St Microelectronics Rousset | COMMUNICATION ON I2C BUS |
| CN106802816A (en) * | 2016-12-29 | 2017-06-06 | 上海天马有机发光显示技术有限公司 | The preparation method of driver element and the display device comprising the driver element |
| CN115098146A (en) * | 2022-07-12 | 2022-09-23 | 深圳市航顺芯片技术研发有限公司 | Burning method, device, medium and terminal |
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| CN101154207A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | Operating method for configured interface of microcontroller |
| US7369958B1 (en) * | 2007-02-19 | 2008-05-06 | Inventec Corporation | System and method for setting motherboard testing procedures |
| CN101419485A (en) * | 2008-11-24 | 2009-04-29 | 电子科技大学 | Function-variable portable computer mainboard |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103309782A (en) * | 2013-06-28 | 2013-09-18 | 广州视源电子科技股份有限公司 | Burning and testing integrated system |
| FR3009633A1 (en) * | 2013-08-08 | 2015-02-13 | St Microelectronics Rousset | COMMUNICATION ON I2C BUS |
| US9753886B2 (en) | 2013-08-08 | 2017-09-05 | Stmicroelectronics (Rousset) Sas | Communication on an I2C bus |
| CN106802816A (en) * | 2016-12-29 | 2017-06-06 | 上海天马有机发光显示技术有限公司 | The preparation method of driver element and the display device comprising the driver element |
| CN106802816B (en) * | 2016-12-29 | 2020-09-22 | 上海天马有机发光显示技术有限公司 | Manufacturing method of driving unit and display device comprising driving unit |
| CN115098146A (en) * | 2022-07-12 | 2022-09-23 | 深圳市航顺芯片技术研发有限公司 | Burning method, device, medium and terminal |
| CN115098146B (en) * | 2022-07-12 | 2023-04-18 | 深圳市航顺芯片技术研发有限公司 | Burning method, device, medium and terminal |
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Application publication date: 20120516 |