CN102437881A

CN102437881A - Receiving state recovery device for optical line terminal (OLT) optical module

Info

Publication number: CN102437881A
Application number: CN2011103114528A
Authority: CN
Inventors: 宋岩; 王婧; 齐彦龙
Original assignee: SUPERXON TECHNOLOGY (CHENGDU) Co Ltd
Current assignee: Chengdu Youbochuang Communication Technology Co ltd
Priority date: 2011-10-14
Filing date: 2011-10-14
Publication date: 2012-05-02
Anticipated expiration: 2031-10-14
Also published as: CN102437881B

Abstract

The invention discloses a receiving state recovery device for an optical line terminal (OLT) optical module. On the basis of the conventional OLT optical module receiver, a quick standard deviation (SD) generating circuit and a logic programmable logic are additionally arranged, and by virtue of the two circuits, a Reset signal for being used by a receiving state recovery circuit is automatically generated in the optical module, so that an OLT system is not required to supply the Reset signal, and the design complexity of the OLT system is reduced; and meanwhile, the OLT system can meet larger splitting ratio application and farther scene application and the problem of the Reset signal loss caused by the addition of a relay amplifier can be avoided.

Description

A kind of accepting state recovery device that is used for the OLT optical module

Technical field

The present invention relates to the optical communication technique field, relate in particular to and a kind ofly can let OLT among the GPON receive the device that quickly recovers to accepting state behind the burst uplink optical signal.

Background technology

GPON (Gigabit-Capable Passive Optical Network gigabit passive optical network) is based on the G.984.x latest generation BPON access standard of standard of ITU-T; Has high bandwidth; High efficiency, large coverage, numerous advantages such as user interface is abundant; Be regarded as realizing that by most of operators the Access Network business is broadband, the desirable technique that synthesization is transformed.GPON a bit arrives multipoint system, and an OLT (Optical Line Terminal optical line terminal) is connected through tree-like optical fiber link with a plurality of ONU (Optical Network Unit optical network unit).The GPON business is asynchronous, the descending 2.488Gbits/s that is defined as, the up 1.244Gbits/s that is defined as.At up direction, transfer of data from each ONU to OLT adopts the mode of time division multiple access, and promptly the business from ONU to OLT is discontinuous, forms the data flow that flows to OLT by burst packet one by one, so the OLT receiving unit has the characteristics of burst type reception.The speed of the uplink burst data bag that GPON requires is very fast; And the Data Receiving of traditional mode optical receiver is very long its settling time; Much larger than hundreds of nanosecond even several microsecond; Can not satisfy the application of GPON system, so the burst mode of GPON OLT receives strict index request is arranged, allowing the maximum continuous code length is 72 bits at all.

Existing GPON OLT optical module generally adopts ac-coupled circuit to accomplish burst mode and receives.Since the filtering of AC coupled high pass filter receive the low frequency component in the data, can cause when data continue " 1 " or " 0 " for long polyphone the pulse top to be fallen and then produce distortion.For preventing such distortion, existing GPON OLT optical module is general to adopt a big coupling capacitor to reduce low-frequency cut-off frequency.And the use of big coupling capacitor can cause the receiver in the OLT optical module not make quick response to the DC level variation of burst packet because of its long time that discharges and recharges again.Thereby satisfy the requirement of GPON for the response speed that guarantees the OLT optical module; In ac-coupled circuit, introduced the speed-sensitive switch chip again; Be used at short notice resistance shorted on both ends, help the coupling capacitance repid discharge, to satisfy the demand of response fast the AC coupled part.The switch of speed-sensitive switch chip is controlled by Reset (reset signal).

Reset plays important effect in the burst optical receiver of OLT optical module, in the prior art generally all be Reset to be provided signal for the OLT optical module by GPON OLT system, but increased the difficulty of GPON OLT system design greatly like this; Existing simultaneously GPON system is subject to optical power budget, is difficult to satisfy big splitting ratio and uses apart from scene with long, amplifies transmission signals if increase relay amplifier in the transmission intergrade, and then relay amplifier can't provide Reset again.Therefore pressing for a kind of OLT of need not system in the practical application provides the GPON OLT optical module that can recover accepting state voluntarily of Reset signal.

Summary of the invention

To the problems referred to above, the object of the present invention is to provide a kind of OLT system that need not of the OLT of being used for optical module that the device that can recover accepting state voluntarily of Reset signal is provided.

The object of the invention is accomplished through following technical scheme:

A kind of accepting state recovery device that is used for the OLT optical module; Comprise APD-TIA (the Avalanche Photo Diode-Trans-impedance Amplifier that is used for light signal is converted into differential electric signal of part at least; Avalanche photodide-trans-impedance amplifier); At least partly the accepting state restore circuit that is used for recovering accepting state to the differential electric signal shaping and according to the Reset signal; At least the limiting amplifier that is used for the differential electric signal after the shaping is amplified and converted into Rx Data (reception data) signal of part comprises that also the quick SD that is used for Rx Data signal being detected output SD (input) signal of part at least produces circuit, and part is used for the PLD according to the low level duration output of SD signal Reset signal at least; APD-TIA voltage termination bias voltage, light signal is input to the accepting state restore circuit after APD-TIA converts differential electric signal into; Differential electric signal is input to limiting amplifier after the shaping of accepting state restore circuit; Differential electric signal after the shaping is amplified and is converted Rx Data signal into through limiting amplifier and outwards exports, and Rx Data signal also is input to quick SD and produces circuit; SD produces circuit and outwards exports the SD signal fast, and the SD signal also is input to programmable logic device; Programmable logic device is to accepting state restore circuit output Reset signal.

Further, said programmable logic device comprise not gate, with reference to logic level road, delay logic level road, the 5th with door; The SD signal of SD generation circuit is input to reference to logic level road and delay logic level road after the not gate anti-phase simultaneously fast; With reference to logic level road output be connected to the 5th with the Men Yiduan input, be used for the level conversion of preface in short-term of the SD signal after the anti-phase is long sequential level; Delay logic level road output be connected to the 5th with a door other end input, be used for the SD signal after the anti-phase is postponed to handle, and with the level conversion of preface in short-term of the SD signal after the anti-phase for postponing long sequential level; The 5th with door be used for to long sequential level with postpone long sequential level and carry out and computing output Reset signal.Programmable logic device is through to carrying out and computing with reference to the signal on logic level road and the signal on delay logic level road; And then can judge that continuous low level is the Light Condition after continuous data " 0 " or data have finished receiving, prevents the wrong generation that recovers the situation of accepting state.

Further again, said quick SD produces circuit and comprises the standard electric level road, data level road and comparator; Standard electric level road outputting standard level is to comparator one end input, and comparator other end input is arrived according to the level input data level of Rx Data signal in the data level road, output SD signal after comparator standard of comparison level and the data level.Fast SD produce the comparison of circuit through standard electric level road and data level road can sensitivity and export the SD signal fast.

Further, said standard electric level road comprises resistance R 2, resistance R 3, capacitor C 1 and digital to analog converter DAC in addition; Resistance R 2 one termination voltage VCC, resistance R 2 another termination comparator one end inputs; Capacitor C 1 one end ground connection, capacitor C 1 another termination comparator one end input, digital to analog converter DAC aanalogvoltage output connecting resistance R3 one end, resistance R 3 another termination comparator one end inputs.The standard electric level road increases digital to analog converter DAC can artificially be regulated and control fiduciary level, is convenient to engineering debug, can adapt to real world applications environment widely.

Further again, said data level road comprises signal sample circuit, and this signal sample circuit comprises diode Q1, capacitor C 2 and resistance R 4; The anodal input of diode Q1 Rx Data signal, diode Q1 negative pole connects comparator other end input; Capacitor C 2 one end ground connection, capacitor C 2 another termination comparator other end inputs; Resistance R 4 is connected in parallel on capacitor C 2 two ends.Signal sample circuit can be gathered the level of Rx Data signal fast, and SD signal generation speed is met the demands.

Also further, said data level road also comprises emitter follower T1 and resistance R 1; This emitter follower T1 base stage input Rx Data signal, collector electrode meets voltage VCC, and the diode Q1 that emitter-base bandgap grading connects in the signal sample circuit is anodal; Resistance R 1 one end ground connection, another terminating diode Q1 is anodal.The use of emitter follower can be isolated Rx Data signal, thereby the phase place and the amplitude that guarantee the used signal of subsequent conditioning circuit are undistorted.

Beneficial effect of the present invention is: the accepting state recovery device of the OLT of being used for optical module of the present invention has increased quick SD at general OLT optical module receiver and has produced circuit and PLD; Through these two circuit; In optical module, having generated the Reset signal voluntarily supplies the accepting state restore circuit to use; No longer need the OLT system that Reset is provided signal; Thereby reduced the design complexities of OLT system, also can the OLT system satisfy bigger splitting ratio application and farther scene application simultaneously, and not worry increasing the problem that relay amplifier makes the Reset dropout; Fast the emitter follower that produces in the circuit of SD can prevent distorted signals, guarantee signal accurately, the size that DAC can the artificial adjustment fiduciary level simultaneously can make the accepting state recovery device adapt to range of application widely; Programmable logic device can be good at distinguishing the Light Condition after continuous data " 0 " are accomplished with Data Receiving through with reference to the setting on logic level road and delay logic level road, prevents mistake recovery accepting state.

Description of drawings

Fig. 1 is the modularization block diagram of the specific embodiment of the invention;

Fig. 2 is the electrical block diagram that the quick SD of the specific embodiment of the invention produces circuit;

Fig. 3 is the logic circuit structure sketch map of the programmable logic device of the specific embodiment of the invention;

Fig. 4 is the signal sequence sketch map of the specific embodiment of the invention.

Embodiment

Disclosed all characteristics in this specification, or the step in disclosed all methods or the process except mutually exclusive characteristic and/or the step, all can make up by any way.

Disclosed arbitrary characteristic in this specification (comprising any claim, summary and accompanying drawing) is only if special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, only if special narration, each characteristic is an example in a series of equivalences or the similar characteristics.The description to alternative features is to being equal to the description of technical characterictic, must not being regarded as the donation to the public in this specification simultaneously.

Term in this specification (comprising any claim, summary and accompanying drawing) like no specified otherwise, all is defined as the peculiar implication in this area if having the peculiar implication of general sense and this area simultaneously.

As shown in Figure 1, be the modularization block diagram of the specific embodiment of the invention.The APD-TIA voltage end is connected to the bias voltage by the booster circuit generation of OLT optical module, makes the input of APD-TIA output output differential electric signal to the accepting state restore circuit; The accepting state restore circuit is used for differential electric signal is handled and shaping, and accepting state restore circuit output is connected to the input of limiting amplifier; Limiting amplifier is used for giving the OLT system equipment with differential electric signal amplification and output Rx Data, and the output of limiting amplifier is connected to the input that quick SD produces circuit; SD generation circuit is used to produce the SD signal fast, and SD produces circuit output end and is connected to the programmable logic device input fast; Thereby programmable logic device is used for carrying out logic determines output Reset signal according to the SD signal; The Reset signal output part of programmable logic device is connected to another input of accepting state restore circuit; Make the accepting state restore circuit utilize this Reset signal to realize the fast quick-recovery and elimination common-mode voltage difference of differential electric signal accepting state; Programmable logic device is also exported BCDR Reset signal, is used to supply the burst clock recovery and the data shaping of follow-up OLT system device.

The structure of APD-TIA, accepting state restore circuit and limiting amplifier and design be identical with appropriate section in traditional GPON OLT optical module in the present embodiment, is full-fledged device, installs according to the common mode of prior art to get final product.Key of the present invention be to increase can the detection signal state quick SD produce circuit; And the programmable logic device that produces the Reset signal according to the SD signal; So can make the OLT optical module produce the Reset signal voluntarily and supply the accepting state restore circuit to use, and need not provide by the OLT system.

As shown in Figure 2, produce the electrical block diagram of circuit for the quick SD of the specific embodiment of the invention.Be input to the base stage of triode T1 from the Rx Data signal of limiting amplifier; The collector electrode of T1 is connected to supply voltage VCC, and the level output of penetrating of T1 is connected respectively to an end of resistance R 1 and the positive pole of diode Q1, and an other end of resistance R 1 is connected to ground; The triode T1 that so connects method uses as emitter follower in this circuit; Can isolation signals, avoid influencing the sensitivity of signal, guarantee that the phase place and the amplitude of the used signal of subsequent conditioning circuit is undistorted; The negative pole of diode Q1 is connected to resistance R 4 and the end of C2 and an input of comparator; Resistance R 4 and capacitor C 2 parallel connections; And the another one common port of resistance R 5 and capacitor C 2 is connected to ground; Diode Q1, resistance R 4, capacitor C 2 are together as signal acquisition circuit, and the level that can gather Rx Data signal supplies comparator to compare.

The data level road that emitter follower and signal acquisition circuit produce circuit as quick SD together is used for gathering the reception data level and supplies comparator to compare.Wherein the effect of diode Q1 and capacitor C 2 is level states that peak value detects Rx Data signal, and resistance R 4 then is the time that is used to control the C2 discharge; When Rx Data signal normal transmission, constantly give capacitor C 2 chargings through diode Q1, make the level of capacitor C 2 higher relatively; When being in Light Condition when existing continuous data " 0 " perhaps not have data in the Rx Data signal data, capacitor C 2 no longer is recharged but through resistance R 4 discharges, its voltage level constantly reduces, final fiduciary level less than the other input of comparator.

The standard electric level road then is made up of resistance R 2, resistance R 3, capacitor C 1 and digital to analog converter DAC; Resistance R 2 one termination voltage VCC, resistance R 2 another termination comparator one end inputs; Capacitor C 1 one end ground connection, capacitor C 1 another termination comparator one end input; Digital to analog converter DAC aanalogvoltage output connecting resistance R3 one end, resistance R 3 another termination comparator one end inputs; So the standard electric level road of circuit connection can provide fiduciary level; Digital to analog converter DAC can make fiduciary level regulated and control by manual work simultaneously; So that adapt to real world applications environment widely, the variation that DAC can also offset supply voltage guarantees the stability of SD signal.

Comparator is used to produce the SD signal, when fiduciary level greater than data level time output high level, when fiduciary level output low level during less than data level.For the SD signal stabilization, comparator generally adopts Schmidt's comparator, and it is interval to increase the hysteresis of judging; For the quick response of SD signal, require to select the comparator that its response time is fast, bandwidth big, transmission delay ns level is following for use simultaneously, medium-to-high grade on the market comparator generally can satisfy this requirement.

As shown in Figure 3, be the logic circuit structure sketch map of the programmable logic device of the specific embodiment of the invention.Programmable logic array PLA (Programmable Logic Array) is made up of programmable and array and programmable or array.The configuration data of PLA has determined the interconnected relationship and the logic function of PLA local array, changes these data, has also just changed the logic function of device.The development day crescent of singlechip technology is beneficial now, and function has all increased the function of PLA from strength to strength in a lot of little process chip, such as the ADuC702x series of products of ADI company.

The programmable logic device of the embodiment of the invention is by not gate, form with door with reference to logic level road, delay logic level road, the 5th.The SD signal of SD generation circuit is input to reference to logic level road and delay logic level road after the not gate anti-phase simultaneously fast.

With reference to logic level route first d type flip flop, second d type flip flop, first and door, second with the door composition; The clock signal that d type flip flop is required; SD signal after the anti-phase is input to the first flip-flop data end, first and Men Yiduan input, second and the Men Yiduan input simultaneously respectively; The first d type flip flop output be connected to first with a door other end input; First is connected to the second d type flip flop data terminal with gate output terminal, the second d type flip flop output be connected to second with a door other end input, second with gate output terminal be connected to programmable logic device the 5th with the Men Yiduan input.The required CLK clock signal of d type flip flop is provided by the clock chip of little process chip, puts 1 end and puts 0 end and all connect high level.With reference to the blocking effect of logic level road through d type flip flop; Can the change frequency of SD signal level be reduced; Then again through with door and computing; Further reduced the change frequency of signal level, floating changed frequent preamble section in short-term, preamble section highlights when making consecutive identical long of level.

Delay logic level route delay cell, 3d flip-flop, four d flip-flop, the 3rd are formed with door with door, the 4th; SD signal after the anti-phase be input to respectively simultaneously the 3rd flip-flop data end, the 3rd with the Men Yiduan input, the 4th with the Men Yiduan input; The 3d flip-flop output be connected to the 3rd with a door other end input; The 3rd with gate output terminal be connected to the four d flip-flop data terminal; The four d flip-flop output be connected to the 4th with a door other end input, the 4th with gate output terminal be connected to programmable logic device the 5th with a door other end input.The effect on delay logic level road has just increased individual delay cell with originally identical with reference to the logic level roadbed, can the sequential of signal level be delayed.

The 5th with door be used for to long sequential level with postpone long sequential level and carry out and computing output Reset signal.Since delay logic level road send to the 5th with the long sequential level of the delay of door with respect to the delay that the long period is arranged with reference to the long sequential level on logic level road; Carry out and computing with door through the 5th; Can reject the continuous low level part of the SD signal that falls short of; And then can judge that continuous low level is the Light Condition after continuous data " 0 " or data have finished receiving, prevents the wrong generation that recovers the situation of accepting state.

Programmable logic device also becomes BCDR Reset signal through the 5th d type flip flop with Reset signal delay a period of time, so that the burst clock recovery and the data shaping of subsequent device.

In one embodiment of the invention; The clock cycle of d type flip flop is about 24ns; The delay units delay time is about 12ns, has realized that successfully the minimum of programmable logic device 12ns is judged the cycle, thereby has improved the precision that SD signal level duration length is judged.

As shown in Figure 4, be the signal sequence sketch map of the specific embodiment of the invention.Preamble section when the frequent preamble section in short-term that changes in the SD signal is grown with variation more slowly; After the processing with reference to logic level road and delay logic level road, preface has become long sequential in short-term, has formed long sequential level respectively and has postponed long sequential level; Long sequential level with postpone long sequential level through the 5th with door with computing after, produced the Reset signal; The Reset signal is then postponed to become BCDR Reset signal after a period of time by the 5th d type flip flop.

Claims

1. accepting state recovery device that is used for the OLT optical module; Comprise the APD-TIA that is used for light signal is converted into differential electric signal of part at least; At least partly the accepting state restore circuit that is used for recovering accepting state to the differential electric signal shaping and according to the Reset signal; At least partly the limiting amplifier that is used for the differential electric signal after the shaping is amplified and converted into Rx Data signal is characterized in that:

Also comprise the quick SD generation circuit that is used for Rx Data signal is detected output SD signal of part, the PLD that is used for exporting the Reset signal of part at least at least according to the low level duration of SD signal;

APD-TIA voltage termination bias voltage, light signal is input to the accepting state restore circuit after APD-TIA converts differential electric signal into; Differential electric signal is input to limiting amplifier after the shaping of accepting state restore circuit; Differential electric signal after the shaping is amplified and is converted Rx Data signal into through limiting amplifier and outwards exports, and Rx Data signal also is input to quick SD and produces circuit; SD produces circuit and outwards exports the SD signal fast, and the SD signal also is input to programmable logic device; Programmable logic device is to accepting state restore circuit output Reset signal.

2. according to the said accepting state recovery device that is used for the OLT optical module of claim 1, it is characterized in that:

Said programmable logic device comprise not gate, with reference to logic level road, delay logic level road, the 5th with door;

The SD signal of SD generation circuit is input to reference to logic level road and delay logic level road after the not gate anti-phase simultaneously fast; With reference to logic level road output be connected to the 5th with the Men Yiduan input, be used for the level conversion of preface in short-term of the SD signal after the anti-phase is long sequential level; Delay logic level road output be connected to the 5th with a door other end input, be used for the SD signal after the anti-phase is postponed to handle, and with the level conversion of preface in short-term of the SD signal after the anti-phase for postponing long sequential level; The 5th with door be used for to long sequential level with postpone long sequential level and carry out and computing output Reset signal.

3. according to the said accepting state recovery device that is used for the OLT optical module of claim 1, it is characterized in that:

Said quick SD produces circuit and comprises the standard electric level road, data level road and comparator; Standard electric level road outputting standard level is to comparator one end input, and comparator other end input is arrived according to the level input data level of Rx Data signal in the data level road, output SD signal after comparator standard of comparison level and the data level.

4. according to the said accepting state recovery device that is used for the OLT optical module of claim 3, it is characterized in that:

Said standard electric level road comprises resistance R 2, resistance R 3, capacitor C 1 and digital to analog converter DAC; Resistance R 2 one termination voltage VCC, resistance R 2 another termination comparator one end inputs; Capacitor C 1 one end ground connection, capacitor C 1 another termination comparator one end input, digital to analog converter DAC aanalogvoltage output connecting resistance R3 one end, resistance R 3 another termination comparator one end inputs.

5. according to the said accepting state recovery device that is used for the OLT optical module of claim 3, it is characterized in that:

Said data level road comprises signal sample circuit, and this signal sample circuit comprises diode Q1, capacitor C 2 and resistance R 4; The anodal input of diode Q1 Rx Data signal, diode Q1 negative pole connects comparator other end input; Capacitor C 2 one end ground connection, capacitor C 2 another termination comparator other end inputs; Resistance R 4 is connected in parallel on capacitor C 2 two ends.

6. according to the said accepting state recovery device that is used for the OLT optical module of claim 5, it is characterized in that:

Said data level road also comprises emitter follower T1 and resistance R 1; This emitter follower T1 base stage input Rx Data signal, collector electrode meets voltage VCC, and the diode Q1 that emitter-base bandgap grading connects in the signal sample circuit is anodal; Resistance R 1 one end ground connection, another terminating diode Q1 is anodal.