CN102437881B - A kind of accepting state recovery device for OLT optical module - Google Patents
A kind of accepting state recovery device for OLT optical module Download PDFInfo
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- CN102437881B CN102437881B CN201110311452.8A CN201110311452A CN102437881B CN 102437881 B CN102437881 B CN 102437881B CN 201110311452 A CN201110311452 A CN 201110311452A CN 102437881 B CN102437881 B CN 102437881B
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Abstract
The invention discloses a kind of accepting state recovery device for OLT optical module, in existing OLT optical module receiver, add quick SD produce circuit and Programmable Logic Device, by these two circuit, Reset signal is generated voluntarily for accepting state restore circuit in optical module, OLT system is no longer needed to provide Reset signal, thus reduce the design complexities of OLT system, also OLT system can meet larger splitting ratio application and the application of farther scene simultaneously, and not worry increasing the problem that relay amplifier makes Reset dropout.
Description
Technical field
The present invention relates to technical field of photo communication, particularly relate to a kind of the OLT in GPON can be allowed to receive burst upstream light signal after quickly recover to the device of accepting state.
Background technology
GPON(Gigabit-CapablePassiveOpticalNetwork gigabit passive optical network) be based on ITU-TG.984.x standard latest generation broadband passive optical network access standard, there is high bandwidth, high efficiency, large coverage, user interface is abundant waits many merits, be considered as realizing Access Network business by most of operator broadband, the desirable technique of synthesization transformation.GPON is a point-to-multi-point system, an OLT(OpticalLineTerminal optical line terminal) with multiple ONU(OpticalNetworkUnit optical network unit) be connected by tree-like optical fiber link.GPON business is asynchronous, is descendingly defined as 2.488Gbits/s, is uply defined as 1.244Gbits/s.At up direction, adopt the mode of time division multiple access from the transfer of data of each ONU to OLT, the business namely from ONU to OLT is discontinuous, and form by burst packet one by one the data flow flowing to OLT, therefore OLT receiving unit has the feature of burst type reception.The speed of the uplink burst data bag that GPON requires quickly, and the data receiver of traditional mode optical receiver is very long for its settling time, much larger than hundreds of nanosecond even several microsecond, GPON systematic difference can not be met at all, therefore the burst-mode receiver of GPONOLT has strict index request, allows maximum continuous code length to be 72 bits.
Existing GPONOLT optical module generally adopts ac-coupled circuit to complete burst-mode receiver.Receive the low frequency component in data due to the filtering of AC coupled high pass filter, can cause when data for long go here and there continuous print " 1 " or " 0 " time pulse top fall and then produce distortion.For preventing such distortion, existing GPONOLT optical module generally adopts a large coupling capacitor to reduce low-frequency cut-off frequency.And the use of large coupling capacitor, can, because of its longer discharge and recharge time, cause the receiver in OLT optical module can not make quick response to the DC level change of burst packet again.Thus in order to ensure that the response speed of OLT optical module meets the requirement of GPON, speed-sensitive switch chip is introduced again in ac-coupled circuit, for at short notice by the resistance shorted on both ends of AC coupled part, help coupling capacitance repid discharge, to meet the demand of response fast.The switch of speed-sensitive switch chip is by Reset(reset signal) control.
Reset plays very important effect in the burst mode optical receivers of OLT optical module, is generally all provide Reset signal by GPONOLT system to OLT optical module, but considerably increases the difficulty of GPONOLT system like this in prior art; Simultaneously existing GPON system is limited to optical power budget, is difficult to satisfied large splitting ratio and the application of long distance scene, if intercaste increases relay amplifier and amplifies signal transmission in the transmission, then relay amplifier cannot provide Reset again.Therefore in practical application in the urgent need to a kind of GPONOLT optical module that can recover accepting state voluntarily providing Reset signal without the need to OLT system.
Summary of the invention
For the problems referred to above, the object of the present invention is to provide a kind of device that can recover accepting state voluntarily that Reset signal is provided without the need to OLT system for OLT optical module.
Object of the present invention has been come by following technical scheme:
A kind of accepting state recovery device for OLT optical module, comprise at least part of APD-TIA(AvalanchePhotoDiode-Trans-impedanceAmplifier for light signal being converted to differential electric signal, , avalanche photodide-trans-impedance amplifier), at least part of for differential electric signal shaping and according to the accepting state restore circuit of Reset signal recuperation accepting state, at least part of for the differential electric signal after shaping being amplified and being converted to RxData(reception data) limiting amplifier of signal, also comprising and at least part of export SD(input for carrying out RxData signal detecting) the quick SD of signal produces circuit, at least part of Programmable Logic Device for exporting Reset signal according to the low level duration of SD signal, APD-TIA voltage termination bias voltage, light signal is converted to after differential electric signal through APD-TIA and is input to accepting state restore circuit, differential electric signal is input to limiting amplifier after the shaping of accepting state restore circuit, differential electric signal after shaping is amplified through limiting amplifier and is converted to RxData signal and outwards exports, and RxData signal is also input to quick SD and produces circuit, quick SD produces circuit and outwards exports SD signal, and SD signal is also input to programmable logic device, programmable logic device exports Reset signal to accepting state restore circuit.
Further, described programmable logic device comprises not gate, with reference to logic level road, delay logic level road, the 5th and door; Quick SD produces the SD signal of circuit after not gate is anti-phase, is input to reference to logic level road and delay logic level road simultaneously; With reference to logic level road output be connected to the 5th with door one end input, for being long sequential level by the level conversion of sequence in short-term of the SD signal after anti-phase; Delay logic level road output be connected to the 5th with door other end input, for carrying out delay disposal to the SD signal after anti-phase, and by the level conversion of sequence in short-term of the SD signal after anti-phase for postponing long sequential level; 5th is used for long sequential level with door and postpones long sequential level and carry out and computing, output Reset signal.Programmable logic device is by carrying out and computing with reference to the signal on logic level road and the signal on delay logic level road, and then can judge that continuous print low level is the Light Condition after continuous print data " 0 " or data finish receiving, prevent the generation of the situation of Fault recovery accepting state.
Further again, described quick SD produces circuit and comprises standard electric level road, data level road and comparator; Standard electric level road outputting standard level is to comparator one end input, and data level road to comparator other end input, exports SD signal after comparator standard of comparison level and data level according to the level input data level of RxData signal.Quick SD produces circuit can be sensitive and export SD signal fast by comparing of standard electric level road and data level road.
Further another, described standard electric level road comprises resistance R2, resistance R3, electric capacity C1 and digital to analog converter DAC; Another termination comparator one end input of resistance R2 mono-termination voltage VCC, resistance R2; Electric capacity C1 one end ground connection, another termination comparator one end input of electric capacity C1, digital to analog converter DAC analog voltage output connecting resistance R3 one end, another termination comparator one end input of resistance R3.Standard electric level road increases digital to analog converter DAC and can artificially regulate and control fiduciary level, is convenient to engineering debug, can adapts to real world applications environment widely.
Further, described data level road comprises signal sample circuit, and this signal sample circuit comprises diode Q1, electric capacity C2 and resistance R4; Diode Q1 positive pole input RxData signal, diode Q1 negative pole connects comparator other end input; Electric capacity C2 one end ground connection, another termination comparator other end input of electric capacity C2; Resistance R4 is connected in parallel on electric capacity C2 two ends.Signal sample circuit can the level of Quick Acquisition RxData signal, makes SD signal produce speed and meets the demands.
Also further, described data level road also comprises emitter follower T1 and resistance R1; This emitter follower T1 base stage input RxData signal, collector electrode meets voltage VCC, and emitter-base bandgap grading connects the diode Q1 positive pole in signal sample circuit; Resistance R1 one end ground connection, another terminating diode Q1 positive pole.The use of emitter follower can isolate RxData signal, thus ensure the phase place of subsequent conditioning circuit signal used and amplitude undistorted.
Beneficial effect of the present invention is: the accepting state recovery device for OLT optical module of the present invention adds quick SD and produces circuit and Programmable Logic Device in general OLT optical module receiver, by these two circuit, Reset signal is generated voluntarily for accepting state restore circuit in optical module, OLT system is no longer needed to provide Reset signal, thus reduce the design complexities of OLT system, also OLT system can meet larger splitting ratio application and the application of farther scene simultaneously, and do not worry increasing the problem that relay amplifier makes Reset dropout, the emitter follower that quick SD produces in circuit can prevent distorted signals, ensures the accurate of signal, and DAC can the size of artificial adjustment fiduciary level simultaneously, and accepting state recovery device can be made to adapt to range of application widely, programmable logic device by reference to the setting on logic level road and delay logic level road, can be good at distinguishing continuous print data " 0 " and data receiver complete after Light Condition, prevent Fault recovery accepting state.
Accompanying drawing explanation
Fig. 1 is the modularization block diagram of the specific embodiment of the invention;
Fig. 2 is the electrical block diagram of the quick SD generation circuit of the specific embodiment of the invention;
Fig. 3 is the logic circuit structure schematic diagram of the programmable logic device of the specific embodiment of the invention;
Fig. 4 is the signal sequence schematic diagram of the specific embodiment of the invention.
Embodiment
All features disclosed in this specification, or the step in disclosed all methods or process, except mutually exclusive feature and/or step, all can combine by any way.
Arbitrary feature disclosed in this specification (comprising any claim, summary and accompanying drawing), unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object.That is, unless specifically stated otherwise, each feature is an example in a series of equivalence or similar characteristics.Be simultaneously the description to technical equivalents to the description of alternative features in this specification, the donation to the public must not be considered as.
This specification (comprising any claim, summary and accompanying drawing), if middle term has general sense and this area spy is significant simultaneously, if no special instructions, is all defined as the peculiar implication in this area.
As shown in Figure 1, be the modularization block diagram of the specific embodiment of the invention.APD-TIA voltage end is connected to the bias voltage produced by the booster circuit of OLT optical module, makes APD-TIA output export the input of differential electric signal to accepting state restore circuit; Accepting state restore circuit is used for processing and shaping differential electric signal, and accepting state restore circuit output is connected to the input of limiting amplifier; Limiting amplifier is used for differential electric signal being amplified and exporting RxData to OLT system equipment, and the output of limiting amplifier is connected to the input that quick SD produces circuit; Quick SD produces circuit for generation of SD signal, and quick SD produces circuit output end and is connected to programmable logic device input; Programmable logic device is used for carrying out Logic judgment according to SD signal thus exporting Reset signal, the Reset signal output part of programmable logic device is connected to another input of accepting state restore circuit, accepting state restore circuit is made to utilize this Reset signal realize the fast quick-recovery of differential electric signal accepting state and eliminate common-mode voltage difference, programmable logic device also exports BCDRReset signal, recovers and data shaping for the burst clock for follow-up OLT system device.
Structure and the design of APD-TIA in the present embodiment, accepting state restore circuit and limiting amplifier are identical with the appropriate section in traditional GPONOLT optical module, and be full-fledged device, normal method conventionally carries out installing.Key of the present invention is to add and the quick SD of detection signal state can produces circuit, and the programmable logic device of Reset signal is produced according to SD signal, OLT optical module so can be made to produce Reset signal voluntarily for accepting state restore circuit, and do not need to be provided by OLT system.
As shown in Figure 2, be the electrical block diagram of the quick SD generation circuit of the specific embodiment of the invention.RxData signal from limiting amplifier is input to the base stage of triode T1, the collector electrode of T1 is connected to supply voltage VCC, the level output of penetrating of T1 is connected respectively to one end of resistance R1 and the positive pole of diode Q1, other one end of resistance R1 is connected to ground, the triode T1 of connection like this uses as emitter follower in this circuit, can isolation signals, avoid the sensitivity affecting signal, ensure the phase place of subsequent conditioning circuit signal used and amplitude undistorted; The negative pole of diode Q1 is connected to one end of resistance R4 and C2 and an input of comparator, resistance R4 and electric capacity C2 is in parallel, and the another one common port of resistance R5 and electric capacity C2 is connected to ground, diode Q1, resistance R4, electric capacity C2 are together as signal acquisition circuit, and the level that can gather RxData signal compares for comparator.
Emitter follower produces the data level road of circuit together with signal acquisition circuit as quick SD, compare for comparator for gathering reception data level.Wherein the effect of diode Q1 and electric capacity C2 is the level state of peakvalue's checking RxData signal, and resistance R4 is then the time of discharging for control C2; When RxData signal normal transmission, charge constantly to electric capacity C2 by diode Q1, make the level of electric capacity C2 relatively high; When there are continuous print data " 0 " in RxData signal data or not having data and be in Light Condition, electric capacity C2 is no longer charged but is discharged by resistance R4, and its voltage level constantly reduces, and is finally less than the fiduciary level of the other input of comparator.
Standard electric level road is then made up of resistance R2, resistance R3, electric capacity C1 and digital to analog converter DAC; Another termination comparator one end input of resistance R2 mono-termination voltage VCC, resistance R2; Electric capacity C1 one end ground connection, another termination comparator one end input of electric capacity C1; Digital to analog converter DAC analog voltage output connecting resistance R3 one end, another termination comparator one end input of resistance R3; The standard electric level road that circuit like this connects can provide fiduciary level, digital to analog converter DAC can make fiduciary level by manually regulating and controlling simultaneously, to adapt to real world applications environment widely, DAC can also the change of offset supply voltage, ensures the stability of SD signal.
Comparator, for generation of SD signal, exports high level when fiduciary level is greater than data level, the output low level when fiduciary level is less than data level.In order to SD signal stabilization, comparator generally adopts Schmidt's comparator, increases the hysteresis judged interval; Simultaneously in order to the quick response of SD signal, require to select that its response time is fast, with the comparator below roomy, transmission delay ns level, comparator medium-to-high grade on the market generally can meet this requirement.
As shown in Figure 3, be the logic circuit structure schematic diagram of the programmable logic device of the specific embodiment of the invention.Programmable logic array PLA(ProgrammableLogicArray), by programmable with array and programmable or array form.The configuration data of PLA determines interconnected relationship and the logic function of PLA local array, changes these data, also just changes the logic function of device.The development day crescent benefit of present singlechip technology, function from strength to strength, both increases the function of PLA in a lot of micro-chip processor, the ADuC702x series of products of such as ADI company.
The programmable logic device of the embodiment of the present invention is made up of with door not gate, reference logic level road, delay logic level road, the 5th.Quick SD produces the SD signal of circuit after not gate is anti-phase, is input to reference to logic level road and delay logic level road simultaneously.
With reference to logic level route first d type flip flop, second d type flip flop, first and door, second forms with door, clock signal needed for d type flip flop, SD signal after anti-phase is input to the first flip-flop data end simultaneously respectively, first with door one end input, second with door one end input, first d type flip flop output is connected to first and door other end input, first is connected to the second d type flip flop data terminal with gate output terminal, second d type flip flop output is connected to second and door other end input, second is connected to the 5th and door one end input of programmable logic device with gate output terminal.CLK clock signal needed for d type flip flop is provided by the clock chip of micro-chip processor, puts 1 end and set to 0 end all to connect high level.With reference to the blocking effect of logic level road by d type flip flop, the change frequency of SD signal level can be reduced, then again by with door and computing, reduce further the change frequency of signal level, floating change preamble section in short-term frequently, when making level consecutive identical long, preamble section highlights.
Delay logic level routing delay unit, 3d flip-flop, four d flip-flop, the 3rd form with door with door, the 4th, SD signal after anti-phase be input to respectively simultaneously the 3rd flip-flop data end, the 3rd with door one end input, the 4th with door one end input, 3d flip-flop output is connected to the 3rd and door other end input, 3rd is connected to four d flip-flop data terminal with gate output terminal, four d flip-flop output is connected to the 4th and door other end input, and the 4th is connected to the 5th and door other end input of programmable logic device with gate output terminal.The effect on delay logic level road, with originally identical with reference to logic level roadbed, only increase a delay cell, the sequential of signal level can be delayed.
5th is used for long sequential level with door and postpones long sequential level and carry out and computing, output Reset signal.Because delay logic level road sends to the 5th to have the delay of long period relative to the long sequential level with reference to logic level road with the delay long sequential level of door, carry out and computing with door by the 5th, the continuous low level part of the SD signal fallen short of can be rejected, and then can judge that continuous print low level is the Light Condition after continuous print data " 0 " or data finish receiving, prevent the generation of the situation of Fault recovery accepting state.
Reset signal delay a period of time is also become BCDRReset signal by the 5th d type flip flop by programmable logic device, so that the burst clock of subsequent device recovers and data shaping.
In one embodiment of the invention, the clock cycle of d type flip flop is about 24ns, the delay units delay time is about 12ns, successfully achieves the minimum judgement cycle of programmable logic device 12ns, thus improves the precision of SD signal level time duration judgement.
As shown in Figure 4, be the signal sequence schematic diagram of the specific embodiment of the invention.Change in SD signal frequently in short-term preamble section and change longer time preamble section; After the process on logic level road and delay logic level road, sequence will become long sequential in short-term, and form respectively long sequential level and postpone long sequential level; Long sequential level and postpone long sequential level through the 5th with door with computing after, create Reset signal; Reset signal becomes BCDRReset signal after then being postponed a period of time by the 5th d type flip flop.
Claims (6)
1. the accepting state recovery device for OLT optical module, comprise at least part of APD-TIA for light signal being converted to differential electric signal, at least part of for differential electric signal shaping and according to the accepting state restore circuit of Reset signal recuperation accepting state, at least part of for the differential electric signal after shaping being amplified and being converted to the limiting amplifier of RxData signal, it is characterized in that:
Also comprise at least part of quick SD generation circuit for carrying out detecting output SD signal to RxData signal, at least part of programmable logic device for exporting Reset signal according to the low level duration of SD signal;
APD-TIA voltage termination bias voltage, light signal is converted to after differential electric signal through APD-TIA and is input to accepting state restore circuit; Differential electric signal is input to limiting amplifier after the shaping of accepting state restore circuit; Differential electric signal after shaping is amplified through limiting amplifier and is converted to RxData signal and outwards exports, and RxData signal is also input to quick SD and produces circuit; Quick SD produces circuit and outwards exports SD signal, and SD signal is also input to programmable logic device; Programmable logic device exports Reset signal to accepting state restore circuit.
2., according to claim 1 for the accepting state recovery device of OLT optical module, it is characterized in that:
Described programmable logic device comprises not gate, with reference to logic level road, delay logic level road, the 5th and door;
Quick SD produces the SD signal of circuit after not gate is anti-phase, is input to reference to logic level road and delay logic level road simultaneously; With reference to logic level road output be connected to the 5th with door one end input, for being long sequential level by the level conversion of sequence in short-term of the SD signal after anti-phase; Delay logic level road output be connected to the 5th with door other end input, for carrying out delay disposal to the SD signal after anti-phase, and by the level conversion of sequence in short-term of the SD signal after anti-phase for postponing long sequential level; 5th is used for long sequential level with door and postpones long sequential level and carry out and computing, output Reset signal.
3., according to claim 1 for the accepting state recovery device of OLT optical module, it is characterized in that:
Described quick SD produces circuit and comprises standard electric level road, data level road and comparator; Standard electric level road outputting standard level is to comparator one end input, and data level road to comparator other end input, exports SD signal after comparator standard of comparison level and data level according to the level input data level of RxData signal.
4., according to claim 3 for the accepting state recovery device of OLT optical module, it is characterized in that:
Described standard electric level road comprises resistance R2, resistance R3, electric capacity C1 and digital to analog converter DAC; Another termination comparator one end input of resistance R2 mono-termination voltage VCC, resistance R2; Electric capacity C1 one end ground connection, another termination comparator one end input of electric capacity C1, digital to analog converter DAC analog voltage output connecting resistance R3 one end, another termination comparator one end input of resistance R3.
5., according to claim 3 for the accepting state recovery device of OLT optical module, it is characterized in that:
Described data level road comprises signal sample circuit, and this signal sample circuit comprises diode Q1, electric capacity C2 and resistance R4; Diode Q1 positive pole input RxData signal, diode Q1 negative pole connects comparator other end input; Electric capacity C2 one end ground connection, another termination comparator other end input of electric capacity C2; Resistance R4 is connected in parallel on electric capacity C2 two ends.
6., according to claim 5 for the accepting state recovery device of OLT optical module, it is characterized in that:
Described data level road also comprises emitter follower T1 and resistance R1; This emitter follower T1 base stage input RxData signal, collector electrode meets voltage VCC, and emitter-base bandgap grading connects the diode Q1 positive pole in signal sample circuit; Resistance R1 one end ground connection, another terminating diode Q1 positive pole.
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| CN201682594U (en) * | 2009-11-02 | 2010-12-22 | 青岛海信宽带多媒体技术有限公司 | Optical line terminal of gigabit passive light network |
| CN102026047A (en) * | 2009-09-10 | 2011-04-20 | 华为技术有限公司 | Method, device and system for transmitting reset signals and rate indication signals |
| CN102075256A (en) * | 2011-01-24 | 2011-05-25 | 成都优博创技术有限公司 | Method and device for improving sensitivity of burst light receiver |
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| WO2010018913A1 (en) * | 2008-08-13 | 2010-02-18 | Electronics And Telecommunications Research Institute | Burst-mode optical signal receiver |
| CN102026047A (en) * | 2009-09-10 | 2011-04-20 | 华为技术有限公司 | Method, device and system for transmitting reset signals and rate indication signals |
| CN201682594U (en) * | 2009-11-02 | 2010-12-22 | 青岛海信宽带多媒体技术有限公司 | Optical line terminal of gigabit passive light network |
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