CN102412294B - 用作静电防护结构的器件 - Google Patents

用作静电防护结构的器件 Download PDF

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CN102412294B
CN102412294B CN 201010290452 CN201010290452A CN102412294B CN 102412294 B CN102412294 B CN 102412294B CN 201010290452 CN201010290452 CN 201010290452 CN 201010290452 A CN201010290452 A CN 201010290452A CN 102412294 B CN102412294 B CN 102412294B
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高翔
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

本发明公开了一种用作静电防护结构的器件，是一种改进的n型LDMOS器件，其改进体现在：一般LDMOS在n型轻掺杂区(11)中只有一个n型重掺杂区作为漏极，本发明则在n型轻掺杂区(11)中增加了一个p型重掺杂区(22)，且该p型重掺杂区(22)将原本为一个的n型重掺杂区***为两个彼此独立的、不连通的n型重掺杂区(21、23)。其中靠近栅极(14)的n型重掺杂区(21)没有引出端，而远离栅极(14)的n型重掺杂区(23)和p型重掺杂区(22)一起引出接输出入焊垫。本发明所述器件具有较好的静电防护性能，可以提高器件在ESD保护中的稳定性，并且较好的保持器件原有的驱动功能。

Description

用作静电防护结构的器件
技术领域
本发明涉及一种半导体集成电路器件，特别是涉及一种作为高压电路的静电保护结构的MOS晶体管。
背景技术
静电对于电子产品的伤害一直是不易解决的问题，目前在半导体集成电路中使用最多的ESD（Electrical Static Discharge，静电放电）保护结构为GGMOS（Ground Gate MOSFET，栅极接地的MOS晶体管）。GGMOS器件具体包括低压MOS（即普通MOS晶体管）、LDMOS（Latetal DiffusionMOSFET，横向扩散MOS晶体管）和DDDMOS（Double Diffusion Drain MOSFET，双扩散漏极MOS晶体管）等。其中低压MOS主要作为低压电路的静电保护结构，LDMOS和DDDMOS主要作为高压电路的静电保护结构。
目前用作静电保护结构的主要是n型MOS晶体管，本申请文件中涉及的低压MOS、LDMOS、DDDMOS均以n型为例进行说明。
请参阅图1，这是一种现有的用作静电防护结构的n型LDMOS。在p型衬底10上为p阱12，p阱12中有n型轻掺杂区（即n阱）11。隔离结构131、132在p阱12中。隔离结构133在n型轻掺杂区11中。隔离结构134在n型轻掺杂区11和/或p阱12中。所述隔离结构131、132、133、134例如为场氧隔离（LOCOS）结构或浅槽隔离（STI）结构。p阱12之上为栅极14，栅极14的一侧在p阱12之上，另一侧在隔离结构133之上。栅极14两侧为侧墙15。栅极14例如为多晶硅，侧墙15例如为氮化硅。p阱12中且在隔离结构131、132之间为p型重掺杂区161，作为p阱12的引出端。p阱12中且在隔离结构132和栅极14的的一侧侧墙15之间为n型重掺杂区162，作为源极。n型轻掺杂区11中且在隔离结构133、134之间且靠近隔离结构133一侧有n型重掺杂区163，作为漏极。n型轻掺杂区11中且在隔离结构133、134之间且靠近隔离结构134一侧有p型重掺杂区164。所述LDMOS用作半导体集成电路的静电保护结构时，p型重掺杂区161和源极162接地（即GND），栅极14接内部电路（也可通过一电阻接地），漏极163和p型重掺杂区164接输出入焊垫。所述输出入焊垫即接静电。
上述图1为简化起见，一些细微结构如栅极下方的栅氧化层、沟槽侧壁和底部的衬垫氧化层、衬底之上可能存在的外延层等均未作图示和说明。
图1所示的LDMOS是在漏极163远离栅极14的一侧增加一个p型重掺杂区164，形成寄生硅控整流管来提高静电保护能力。
请参阅图2和图3，所述寄生硅控整流管在ESD发生下的工作原理是这样的：
在静电正电荷从输出入焊垫进入图1所示LDMOS器件后，会抬高n型轻掺杂区11的电位，通常电压击穿点在LDMOS器件沟道下方处的n型轻掺杂区11边界，即图2所示的早期失效点A处。
击穿电流通过p阱12中的p型重掺杂区161引出，同时抬高p阱12的电位，导致图3中的横向寄生三极管导通。该横向寄生三极管是由n型轻掺杂区11、LDMOS器件沟道下方的p阱12、源极162组成的横向的NPN型三极管。在ESD发生时，这个横向寄生三极管会开启泻流。
但研究中发现，横向寄生三极管开启后漏极163的电流主要从栅极14跨过的场氧化区133下方的n型轻掺杂区11流到整个LDMOS沟道下方的n型轻掺杂区11边界并注入p阱12，因此p型重掺杂区164下方的n型轻掺杂区11的电位较难下降例如0.7V而达到图3中纵向寄生三级管的开启条件。这便致使纵向寄生三级管开启时，横向寄生三级管的开启程度已经较大。所述纵向寄生三极管是由p型重掺杂区164、n型轻掺杂区11和p阱12所组成的纵向的PNP型三极管。
而横向寄生三级管的电流接近LDMOS器件表面，同时在漏极163与隔离结构133交界处的电场强度较大，在大的表面电流和大电场下，该处的发热功率较大，通常还未达到纵向寄生三级管开启条件时，此处已经出现损坏，如图2所示的早期损坏点B处。
如果调节n型轻掺杂区11中p型重掺杂区164与n型轻掺杂区11边界的距离C使击穿电压发生在n型轻掺杂区11靠近p型重掺杂区164一侧，避开早期失效点A，但形成的穿通击穿电压不稳定，因此其调节出的静电触发电压也不稳定。
发明内容
本发明所要解决的技术问题是提供一种高压电路中用作静电防护结构的器件，该器件在ESD放电中静电触发开启电压是可调的。
为解决上述技术问题，本发明用作静电防护结构的器件为：在p型衬底10上为p阱12，p阱12中有n型轻掺杂区11；隔离结构131、132在p阱12中；隔离结构133在n型轻掺杂区11中；隔离结构134在n型轻掺杂区11和/或p阱12中；p阱12之上为栅极14，栅极14的一侧在p阱12之上，另一侧在隔离结构133之上，栅极14的下方包括部分的n型轻掺杂区11；栅极14两侧为侧墙15；p阱12中且在隔离结构131、132之间为p型重掺杂区161，作为p阱12的引出端；p阱12中且在隔离结构132和栅极14的的一侧侧墙15之间为n型重掺杂区162，作为源极；n型轻掺杂区11中且在隔离结构133、134之间且靠近隔离结构133一侧有n型重掺杂区21；n型轻掺杂区11中且在隔离结构133、134之间且靠近隔离结构134一侧有n型重掺杂区23，作为漏极；n型轻掺杂区11中且在n型重掺杂区21和n型重掺杂区23之间有p型重掺杂区22；所述器件用作半导体集成电路的静电保护结构时，p型重掺杂区161和源极162接地，栅极14接内部电路，p型重掺杂区22和漏极23接输出入焊垫；所述输出入焊垫即接静电。
本发明用作静电防护结构的器件可以在不改变器件驱动工作性能的情况下提高寄生硅控整流管的ESD开启效果，提高ESD性能。具体而言可以改善ESD出现时的电压击穿位置，从而提高器件在ESD保护中的稳定性。本发明还可通过具体参数设置来调节静电触发电压，并且可以快速开启纵向寄生三级管，降低电压击穿对器件沟道区损伤和纵向寄生三极管无法开启的风险。
附图说明
图1是现有的一种用作静电防护结构的LDMOS的结构示意图；
图2是图1所示器件在ESD发生时的工作原理示意图；
图3是图1中横向寄生三极管和纵向寄生三极管的示意图；
图4是本发明用作静电防护结构的器件的结构示意图；
图5是图5所示器件在ESD发生时的工作原理示意图；
图6是图5中横向寄生三极管和纵向寄生三极管的示意图；
图7是本发明运用的实际电路图。
图中附图标记说明：
10为p型衬底；11为n型轻掺杂区；12为p阱；131、132、133、134为隔离区；14为栅极；15为侧墙；161为p型重掺杂区；162为源极；163为漏极；164为p型重掺杂区；21为n型重掺杂区；22为p型重掺杂区；23为漏极；A、B为早期失效点；C为尺寸；D为电压击穿区。
具体实施方式
请参阅图4，本发明用作静电防护结构的器件也是一种n型LDMOS器件，具体包括：在p型衬底10上为p阱12，p阱12中有n型轻掺杂区11。隔离结构131、132在p阱12中。隔离结构133在n型轻掺杂区11中。隔离结构134在n型轻掺杂区11和/或p阱12中。所述隔离结构131、132、133、134例如为场氧隔离结构或浅槽隔离结构。p阱12之上为栅极14，栅极14的一侧在p阱12之上，另一侧在隔离结构133之上。栅极14两侧为侧墙15。栅极14例如为多晶硅材料，侧墙15例如为氮化硅材料。p阱12中且在隔离结构131、132之间为p型重掺杂区161，作为p阱12的引出端。p阱12中且在隔离结构132和栅极14的的一侧侧墙15之间为n型重掺杂区162，作为源极。n型轻掺杂区11中且在隔离结构133、134之间且靠近隔离结构133一侧有n型重掺杂区21。n型轻掺杂区11中且在隔离结构133、134之间且靠近隔离结构134一侧有n型重掺杂区23，作为漏极。n型轻掺杂区11中且在n型重掺杂区21和n型重掺杂区23之间有p型重掺杂区22。所述LDMOS器件用作半导体集成电路的静电保护结构时，p型重掺杂区161和源极162接地，栅极14接内部电路（或通过一电阻接地，此时则只具有静电防护功能，而不具有输出驱动功能），p型重掺杂区22和漏极23接输出入焊垫。所述输出入焊垫即接静电。
本发明用作静电防护结构的器件是一种改进的n型LDMOS器件，其改进体现在：一般LDMOS在n型轻掺杂区11中只有一个n型重掺杂区作为漏极，本发明则在n型轻掺杂区11中增加了一个p型重掺杂区22，且该p型重掺杂区22将原本为一个的n型重掺杂区***为两个彼此独立的、不连通的n型重掺杂区21、23。其中靠近栅极14的n型重掺杂区21没有引出端，而远离栅极14的n型重掺杂区23和p型重掺杂区22一起引出接输出入焊垫。
图4所示器件中，n型重掺杂区21、p型重掺杂区22、n型重掺杂区23之间也可以包括隔离结构（未图示）。而p型重掺杂区161和源极162之间的隔离结构132也可以取消。
请参阅图5和图6，本发明用作静电防护结构的器件（n型LDMOS器件）在ESD发生下的工作原理是这样的：
在静电正电荷从输出入焊垫进入漏极23后，导致漏极23和n型轻掺杂区11的电位抬高，通过调节n型轻掺杂区11的边界与漏极23的边界的尺寸C，可以使图5中的D处比n型轻掺杂区11其他位置与p阱12的击穿电压小，因此D处成为电压击穿区。其击穿电流流经p阱12，从p阱12的引出端p型重掺杂区161流出，同时抬高p阱12的电位。当p阱12的电位抬高到例如0.7V时，图5所示的横向寄生三极管导通，泻放静电电流。该横向寄生三极管是由n型轻掺杂区11、LDMOS器件沟道下方的p阱12、源极162组成的横向的NPN型三极管。
当该横向寄生三极管导通后，从漏极23流入的静电电流将主要流经p型重掺杂区22下方的n型轻掺杂区11，并从LDMOS器件沟道下的n型轻掺杂区11边界注入p阱12，同时降低p型重掺杂区22下方的电位。当p型重掺杂区22下方的n型轻掺杂区11电位比漏极23的电位低例如0.7V时，图6所示的纵向寄生三极管导通开启，与之前开启的横向寄生三级管形成开启的硅控整流管，泻放静电电流。该纵向寄生三极管是由p阱12、n型轻掺杂区11、p型重掺杂区22组成的纵向的PNP型三级管。
请参阅图7，其表明了本发明所述器件在电路中的连接方法。与图4相对应，源极162和p型重掺杂区161（衬底引出端）接地，栅极14接内部电路，漏极23和p型重掺杂区22接输出入焊垫。在电路正常工作时，本发明所述器件可用作输出组件，提供输出驱动功能。在静电发生时，可以提供ESD电荷泄放通路，保证该具有驱动功能的器件及其后方的内部电路不被静电损坏。
本发明用作静电防护结构的主要优点在于：
其一，利用漏极23远离栅极14一侧的边界、与n型轻掺杂区11远离栅极14一侧的边界，两个边界的间距C来改变n型轻掺杂区11的击穿电压，从而使静电放电时的触发电压可按照设计要求进行调整。
其二，击穿电压发生的位置在图5中的D处，这是远离LDMOS器件沟道的地方，使得ESD发生时的击穿过程对LDMOS器件沟道区和栅氧化层的损伤较小，提高静电防护的稳定性。
其三，图5所示的横向寄生三级管开启后，电流主要从p型重掺杂区22下方的n型轻掺杂区11流过，有利于快速开启纵向寄生三级管，提高ESD电流的泄放能力。
其四，该结构不改变LDMOS器件工作区的结构，对LDMOS器件的驱动工作性能的影响较小。
其五，n型轻掺杂区11中靠近栅极14的n型重掺杂区21使该LDMOS器件在正常工作时的电流路径更类似无寄生硅控整流管的LDMOS器件的情形，并促进硅控整流管中的ESD电流向LDMOS器件纵深流动，避免开启的横向寄生三级管的表面电流对LDMOS器件结构的损伤。
综上所述，本发明用作静电防护结构的器件具有较好的静电防护性能，并且提高了器件在ESD保护中的稳定性。

Claims (5)

1.一种用作静电防护结构的器件，其特征是：在p型衬底（10）上为p阱（12），p阱（12）中有n型轻掺杂区（11）；隔离结构（131、132）在p阱（12）中；隔离结构（133）在n型轻掺杂区（11）中；隔离结构（134）在n型轻掺杂区（11）和/或p阱（12）中；p阱（12）之上为栅极14，栅极（14）的一端在p阱（12）之上，另一端在隔离结构（133）之上，栅极（14）的中间部分在n型轻掺杂区（11）之上；栅极（14）两侧为侧墙（15）；p阱（12）中且在隔离结构（131、132）之间为p型重掺杂区（161），作为p阱（12）的引出端；p阱（12）中且在隔离结构（132）和栅极（14）的一侧侧墙15之间为n型重掺杂区（162），作为源极；n型轻掺杂区（11）中且在隔离结构（133、134）之间且靠近隔离结构（133）一侧有n型重掺杂区（21）；n型轻掺杂区（11）中且在隔离结构（133、134）之间且靠近隔离结构（134）一侧有n型重掺杂区（23），作为漏极；n型轻掺杂区（11）中且在n型重掺杂区（21）和n型重掺杂区（23）之间有p型重掺杂区（22）；所述器件用作半导体集成电路的静电保护结构时，p型重掺杂区（161）和源极（162）接地，栅极（14）接内部电路，p型重掺杂区（22）和漏极（23）接输出入焊垫；所述输出入焊垫接静电。
2.根据权利要求1所述的用作静电防护结构的器件，其特征是，所述n型重掺杂区（21）和n型重掺杂区（23）不联通，且所述n型重掺杂区（21）没有引出端。
3.根据权利要求1所述的用作静电防护结构的器件，其特征是，所述n型重掺杂区（21）、p型重掺杂区（22）和n型重掺杂区（23）之间还具有隔离结构。
4.根据权利要求1所述的用作静电防护结构的器件，其特征是，所述器件的静电电压击穿位置为所述n型轻掺杂区（11）远离栅极（14）一侧的边界，静电电流从所述p型重掺杂区（22）流向所述源极（162）。
5.根据权利要求1所述的用作静电防护结构的器件，其特征是，所述器件的静电触发电压由所述n型轻掺杂区（11）远离栅极（14）一侧的边界，与所述漏极（23）远离栅极（14）一侧的边界，两个边界的间距来调节。
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