CN103378087B - 静电释放保护结构及其制造方法 - Google Patents
静电释放保护结构及其制造方法 Download PDFInfo
- Publication number
- CN103378087B CN103378087B CN201210130387.3A CN201210130387A CN103378087B CN 103378087 B CN103378087 B CN 103378087B CN 201210130387 A CN201210130387 A CN 201210130387A CN 103378087 B CN103378087 B CN 103378087B
- Authority
- CN
- China
- Prior art keywords
- substrate
- well region
- district
- contra
- isolated area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 201
- 238000002955 isolation Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 230000001105 regulatory effect Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thyristors (AREA)
Abstract
本发明涉及一种静电释放保护结构,包括:衬底,具有第一导电类型;阱区,具有第二导电类型;衬底接触区,设于衬底内,具有第一导电类型;阱区接触区,设于阱区内,具有第二导电类型;衬底反掺杂区,位于衬底接触区和阱区接触区之间,具有第二导电类型;阱区反掺杂区,位于衬底接触区和阱区接触区之间,具有第一导电类型;连通区,设于衬底和阱区的横向交界处;第一隔离区,处于衬底反掺杂区和连通区之间;第二隔离区,处于阱区反掺杂区和连通区之间;氧化层,一端设于第一隔离区上,另一端设于衬底上;场板结构,设于氧化层上。本发明还涉及一种静电释放保护结构制造方法。本发明可通过调节场板结构的宽度和位置来调整开启电压。
Description
技术领域
本发明半导体制造领域,特别是涉及一种静电释放保护结构,还涉及一种静电释放保护结构的制造方法。
背景技术
静电释放(Electro-StaticDischarge,ESD)会造成半导体元器件的损坏。
一种传统的静电释放保护结构是采用可控硅(Siliconcontrolledrectifier,SCR),如图1所示。该可控硅结构形成于一p型衬底上,通过n-掺杂在该p型衬底上形成n阱,从而在p型衬底和n阱间形成PN结结构。同时分别在p型衬底和n阱内掺杂形成n+和p+区域,作为接触区。在衬底和阱区的横向交界处与接触区之间,分别通过重掺杂形成p+和n+反掺杂区。n阱内的n+接触区和p+反掺杂区通过金属引线电连接形成阳极。同样地,p型衬底内的p+接触区和n+反掺杂区通过金属引线电连接形成阴极。n+反掺杂区相当于NPN三极管的发射极,p+反掺杂区相当于PNP三极管的发射极。该NPN三极管和PNP三极管互联形成可控硅。
在器件正常工作时(前述阳极的电势高于阴极),n阱和p型衬底间形成的二极管反偏,工作电压低于二极管的击穿电压,该可控硅不会被触发且电流极小。但当静电释放浪涌产生时,前述阳极的电压达到雪崩电压,因碰撞电离产生大量的电子-空穴对,电子和空穴分别在电场作用下向n阱/p型衬底移动。空穴漂移穿入p型衬底导致电位下降,进而使得基极和发射极之间的PN结导通,电子从发射极注入基极。同样的机制使得n阱内也产生载流子漂移,空穴从发射极注入基极。电子和空穴的漂移会使得电位进一步上升或下降,进一步增强碰撞电离的程度。这一自举过程将使得可控硅形成一个适于静电释放的、低阻且能够通过大电流的电流通道。
然而,这种传统的静电释放保护结构存在触发电压(或称为开启电压)较高的问题,对于氧化层较薄、敏感易损的元器件,可能因该较高的触发电压造成ESD损坏。
发明内容
基于此,有必要针对传统的静电释放保护结构触发电压较高的问题,提供一种易于通过设计制造时的简单调整而调节触发电压的静电释放保护结构。
一种静电释放保护结构,包括:衬底,具有第一导电类型;阱区,设于所述衬底内,具有第二导电类型;衬底接触区,设于所述衬底内,具有所述第一导电类型;阱区接触区,设于所述阱区内,具有所述第二导电类型;衬底反掺杂区,设于所述衬底内,且位于所述衬底接触区和阱区接触区之间,具有所述第二导电类型;阱区反掺杂区,设于所述阱区内,且位于所述衬底接触区和阱区接触区之间,具有所述第一导电类型;连通区,设于所述衬底和阱区的横向交界处,且设于所述衬底反掺杂区和阱区反掺杂区之间,直接接触所述衬底和阱区;第一隔离区,设于所述衬底内,且处于所述衬底反掺杂区和连通区之间;第二隔离区,设于所述阱区内,且处于所述阱区反掺杂区和连通区之间;氧化层,靠近所述连通区设置,所述氧化层一端设于所述第一隔离区上,另一端设于所述衬底上;或所述氧化层一端设于所述第二隔离区上,另一端设于所述阱区上;所述氧化层不与所述连通区直接接触;场板结构,设于所述氧化层上。
在其中一个实施例中,所述第一导电类型是p型,所述第二导电类型是n型,所述连通区具有n型导电类型,所述氧化层一端设于所述第一隔离区上,另一端设于所述衬底上,所述静电释放保护结构还包括阳极引线和阴极引线,所述阳极引线电性连接所述阱区反掺杂区和阱区接触区,所述阴极引线电性连接所述衬底接触区、衬底反掺杂区和场板结构。
在其中一个实施例中,所述第一导电类型是p型,所述第二导电类型是n型,所述连通区具有p型导电类型,所述氧化层一端设于所述第二隔离区上,另一端设于所述阱区上,所述静电释放保护结构还包括阳极引线和阴极引线,所述阳极引线电性连接所述阱区反掺杂区、阱区接触区及场板结构,所述阴极引线电性连接所述衬底接触区和衬底反掺杂区。
在其中一个实施例中,所述第一导电类型是n型,所述第二导电类型是p型,所述连通区具有p型导电类型,所述氧化层一端设于所述第一隔离区上,另一端设于所述衬底上,所述静电释放保护结构还包括阳极引线和阴极引线,所述阳极引线电性连接所述衬底接触区、衬底反掺杂区及场板结构,所述阴极引线电性连接所述阱区反掺杂区和阱区接触区。
在其中一个实施例中,所述第一导电类型是n型,所述第二导电类型是p型,所述连通区具有n型导电类型,所述氧化层一端设于所述第二隔离区上,另一端设于所述阱区上,所述静电释放保护结构还包括阳极引线和阴极引线,所述阳极引线电性连接所述衬底接触区和衬底反掺杂区,所述阴极引线电性连接所述阱区反掺杂区、阱区接触区及场板结构。
在其中一个实施例中,所述场板结构的材质为多晶硅。
在其中一个实施例中,所述第一隔离区和第二隔离区为浅沟槽隔离结构。
还有必要提供一种上述静电释放保护结构的制造方法。
一种静电释放保护结构的制造方法,包括下列步骤:提供衬底,所述衬底具有第一导电类型;在所述衬底内形成第一隔离区和第二隔离区;通过离子注入在所述衬底内形成具有第二导电类型的阱区,所述第一隔离区处于所述衬底内,所述第二隔离区处于所述阱区内;通过热氧化形成氧化层,所述氧化层一端设于所述第一隔离区上,另一端设于所述衬底上;或所述氧化层一端设于所述第二隔离区上,另一端设于所述阱区上;通过淀积在所述氧化层上形成场板结构;通过离子注入在所述衬底和阱区内形成接触区、反掺杂区及连通区,所述接触区包括设于所述衬底内、具有所述第一导电类型的衬底接触区,设于所述阱区内、具有所述第二导电类型阱区接触区;所述反掺杂区包括设于所述衬底内且位于所述衬底接触区和阱区接触区之间、具有所述第二导电类型的衬底反掺杂区,设于所述阱区内且位于所述衬底接触区和阱区接触区之间、具有所述第一导电类型阱区反掺杂区;所述连通区设于所述衬底和阱区的横向交界处,且设于所述衬底反掺杂区和阱区反掺杂区之间,直接接触所述衬底和阱区。
在其中一个实施例中,所述通过离子注入在所述衬底和阱区内形成接触区和连通区的步骤之后,还包括形成阳极引线和阴极引线的步骤。
在其中一个实施例中,所述场板结构的材质为多晶硅。
在其中一个实施例中,所述第一隔离区和第二隔离区为浅沟槽隔离结构。
上述静电释放保护结构,当静电释放发生时,阳极电势升高,耗尽区在衬底和阱区内形成,在衬底表面的耗尽区宽度受到场板结构的宽度(即场板结构边缘的位置)所限。随着阳极电压进一步升高,电场强度逐渐增强,直到达到连通衬底和阱区的连通区形成的单向二极管(one-sidediode)的雪崩击穿电压。此时大量的电子-空穴对产生,使得可控硅被触发,形成静电释放通道,起到静电释放保护的作用。其中可控硅的开启电压、即单向二极管的雪崩击穿电压可以通过在设计制造时,调节场板结构的宽度和位置来进行调整。且由于设置了连通区,使得开启电压比传统技术更低。
附图说明
图1是一传统的采用了可控硅的静电释放保护结构的剖面结构示意图;
图2是静电释放保护结构第一实施例的剖面结构示意图;
图3是静电释放保护结构第二实施例的剖面结构示意图;
图4是静电释放保护结构第三实施例的剖面结构示意图;
图5是静电释放保护结构第四实施例的剖面结构示意图;
图6是静电释放保护结构的制造过程中步骤S11完成后的剖面结构示意图;
图7是静电释放保护结构的制造过程中步骤S21完成后的剖面结构示意图;
图8是静电释放保护结构的制造过程中步骤S31完成后的剖面结构示意图;
图9是静电释放保护结构的制造过程中步骤S41完成后的剖面结构示意图;
图10是静电释放保护结构的制造过程中步骤S51完成后的剖面结构示意图;
图11是静电释放保护结构的制造过程中步骤S61完成后的剖面结构示意图;
图12是一实施例中静电释放保护结构的制造方法的流程图。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。
实施例一:
图2是静电释放保护结构第一实施例的剖面结构示意图,包括p型衬底110,通过轻掺杂在p型衬底110内形成的n阱121。n阱121内通过重掺杂形成n+的阱区接触区131和p+的阱区反掺杂区133,相应地在p型衬底110内通过重掺杂形成p+的衬底接触区132和n+的衬底反掺杂区134。其中衬底反掺杂区134和阱区反掺杂区133均位于衬底接触区132与阱区接触区131之间。
在衬底反掺杂区134和阱区反掺杂区133之间、同时又是p型衬底110和n阱121表面的横向交界处,通过重掺杂形成n+的连通区135。连通区135连通p型衬底110和n阱121,在p型衬底110和n阱121表面将n阱121延伸入p型衬底110内,形成单向二极管。设置连通区135可以降低阱区反掺杂区133-n阱121-p型衬底110-衬底反掺杂区134形成的横向可控硅的触发电压。
连通区135和衬底反掺杂区134之间形成有第一隔离区141,连通区135和阱区反掺杂区133之间形成有第二隔离区142。在本实施例中,第一隔离区141和第二隔离区142采用浅沟槽隔离(STI)结构。在其它实施例中也可以采用其它隔离结构,例如硅的局部场氧化(LOCOS)结构。第一隔离区141和第二隔离区142用于定义上述单向二极管。
在p型衬底110上、连通区135和衬底反掺杂区134之间设有二氧化硅材质的氧化层151。氧化层151一端设于第一隔离区141上,另一端设于p型衬底110上。注意氧化层151应不与连通区135直接接触。氧化层151上设有场板结构161。在本实施例中场板结构161为多晶硅材质,该多晶硅可以根据需求进行掺杂,在其他实施例中也可以使用金属场板,例如铝场板。
p型衬底110上设有阴极引线,电性连接衬底接触区132、衬底反掺杂区134及场板结构161。n阱121上设有阳极引线,电性连接阱区反掺杂区133和阱区接触区131。注意图2中的阳极引线和阴极引线在图上表示的是连线,而不是由连线围成的矩形。
上述静电释放保护结构,当静电释放发生时,阳极电势升高,耗尽区在p型衬底110和n阱121内形成,场板结构161电性连接阴极作为电场板,p型衬底110表面的耗尽区宽度受到场板结构161的宽度(即场板结构161边缘的位置)所限。随着阳极电压进一步升高,电场强度逐渐增强,直到达到单向二极管的雪崩击穿电压。此时大量的电子-空穴对产生,分别进入n阱121和p型衬底110,使得可控硅被触发。衬底反掺杂区134-p型衬底110-n阱121形成的NPN三极管,以及阱区反掺杂区133-n阱121-p型衬底110形成的PNP三极管均导通,形成静电释放通路,起到静电释放保护的作用。其中可控硅的开启电压、即单向二极管的雪崩击穿电压可以通过在设计制造时,调节场板结构161的宽度和位置来进行调整。而可控硅固有的电传导能力受单向二极管的影响较小。
实施例二:
图3是静电释放保护结构第二实施例的剖面结构示意图,其结构和工作原理与第一实施例相似。具体地,静电释放保护结构包括p型衬底210,通过轻掺杂在p型衬底210内形成的n阱221。n阱221内通过重掺杂形成n+的阱区接触区231和p+的阱区反掺杂区233,相应地在p型衬底210内通过重掺杂形成p+的衬底接触区232和n+的衬底反掺杂区234。其中衬底反掺杂区234和阱区反掺杂区233均位于衬底接触区232与阱区接触区231之间。
在衬底反掺杂区234和阱区反掺杂区233之间、同时又是p型衬底210和n阱221表面的横向交界处,通过重掺杂形成p+的连通区236。连通区236连通p型衬底210和n阱221,将p型衬底210延伸入n阱221内,形成单向二极管。
连通区236和衬底反掺杂区234之间形成有第一隔离区241,连通区236和阱区反掺杂区233之间形成有第二隔离区242。在本实施例中,第一隔离区241和第二隔离区242采用浅沟槽隔离(STI)结构。在其它实施例中也可以采用其它隔离结构,例如硅的局部场氧化(LOCOS)结构。
在n阱221上、连通区236和阱区反掺杂区233之间设有二氧化硅材质的氧化层251。氧化层251一端设于第二隔离区242上,另一端设于n阱221上。注意氧化层251应不与连通区236直接接触。氧化层251上设有场板结构261。在本实施例中场板结构261为多晶硅材质,在其他实施例中也可以使用金属场板,例如铝场板。
p型衬底210上设有阴极引线,电性连接衬底接触区232和衬底反掺杂区234。n阱221上设有阳极引线,电性连接阱区反掺杂区233、阱区接触区231以及场板结构261。注意图3中的阳极引线和阴极引线在图上表示的是连线,而不是由连线围成的矩形。
实施例三:
图4是静电释放保护结构第三实施例的剖面结构示意图,该实施例是将实施例一的p型衬底n阱结构变换成n型衬底p阱结构后的实施例。包括n型衬底310,通过轻掺杂在n型衬底310内形成的p阱321。p阱321内通过重掺杂形成p+的阱区接触区331和n+的阱区反掺杂区333,相应地在n型衬底310内通过重掺杂形成n+的衬底接触区132和p+的衬底反掺杂区334。其中衬底反掺杂区334和阱区反掺杂区333均位于衬底接触区332与阱区接触区331之间。
在衬底反掺杂区334和阱区反掺杂区333之间、同时又是n型衬底310和p阱321表面的横向交界处,通过重掺杂形成p+的连通区335。连通区335连通n型衬底310和p阱321,将p阱321延伸入n型衬底310内,形成单向二极管。
连通区335和衬底反掺杂区334之间形成有第一隔离区341,连通区335和阱区反掺杂区333之间形成有第二隔离区342。在本实施例中,第一隔离区341和第二隔离区342采用浅沟槽隔离(STI)结构。在其它实施例中也可以采用其它隔离结构,例如硅的局部场氧化(LOCOS)结构。
在n型衬底310上、连通区335和衬底反掺杂区334之间设有二氧化硅材质的氧化层351。氧化层351一端设于第一隔离区341上,另一端设于n型衬底310上。注意氧化层351应不与连通区335直接接触。氧化层351上设有场板结构361。在本实施例中场板结构361为多晶硅材质,在其他实施例中也可以使用金属场板,例如铝场板。
n型衬底310上设有阳极引线,电性连接衬底接触区332、衬底反掺杂区334及场板结构361。p阱321上设有阴极引线,电性连接阱区反掺杂区333和阱区接触区331。注意图4中的阳极引线和阴极引线在图上表示的是连线,而不是由连线围成的矩形。
实施例四:
图5是静电释放保护结构第四实施例的剖面结构示意图,该实施例是将实施例二的p型衬底n阱结构变换成n型衬底p阱结构后的实施例。包括n型衬底410,通过轻掺杂在n型衬底410内形成的p阱421。p阱421内通过重掺杂形成p+的阱区接触区431和n+的阱区反掺杂区433,相应地在n型衬底410内通过重掺杂形成n+的衬底接触区432和p+的衬底反掺杂区434。其中衬底反掺杂区434和阱区反掺杂区433均位于衬底接触区432与阱区接触区431之间。
在衬底反掺杂区434和阱区反掺杂区433之间、同时又是n型衬底410和p阱421表面的横向交界处,通过重掺杂形成n+的连通区436。连通区436连通n型衬底410和p阱421,将n型衬底410延伸入p阱421内,形成单向二极管。
连通区436和衬底反掺杂区434之间形成有第一隔离区441,连通区436和阱区反掺杂区433之间形成有第二隔离区442。在本实施例中,第一隔离区441和第二隔离区442采用浅沟槽隔离(STI)结构。在其它实施例中也可以采用其它隔离结构,例如硅的局部场氧化(LOCOS)结构。
在p阱421上、连通区436和衬底接触区433之间设有二氧化硅材质的氧化层451。氧化层451一端设于第二隔离区442上,另一端设于p阱421上。注意氧化层451应不与连通区436直接接触。氧化层451上设有场板结构461。在本实施例中场板结构461为多晶硅材质,在其他实施例中也可以使用金属场板,例如铝场板。
n型衬底410上设有阳极引线,电性连接衬底接触区432和衬底反掺杂区434。p阱421上设有阴极引线,电性连接阱区反掺杂区433、阱区接触区431及场板结构461。注意图5中的阳极引线和阴极引线在图上表示的是连线,而不是由连线围成的矩形。
图6~图11示出了静电释放保护结构的制造过程中静电释放保护结构的剖面结构示意图。
图12是一实施例中静电释放保护结构的制造方法的流程图,包括下列步骤:
S11,提供衬底,该衬底具有第一导电类型。
参见图6,以制造实施例一所述静电释放保护结构为例,是采用轻掺杂的p型硅片作为p型衬底110。
S21,在衬底内形成第一隔离区和第二隔离区。
参见图7,第一隔离区141和第二隔离区142采用浅沟槽隔离(STI)结构。在其它实施例中也可以采用其它隔离结构,例如硅的局部场氧化(LOCOS)结构。
S31,通过离子注入在衬底内形成具有第二导电类型的阱区。
第二隔离区应处于阱区内,第一隔离区应处于阱区外的衬底内。参见图8,以制造实施例一所述静电释放保护结构为例,是通过轻掺杂的离子注入形成n阱121。
S41,通过热氧化形成氧化层。
氧化层形成于硅片表面,在一个实施例中,氧化层一端设于第一隔离区上,另一端设于衬底上;在另一个实施例中,氧化层一端设于第二隔离区上,另一端设于阱区上。参见图9,以制造实施例一所述静电释放保护结构为例,氧化层151(即二氧化硅层)形成于p型衬底110表面,不与n阱121接触。氧化层151一端设于第一隔离区141上,另一端设于p型衬底110上。
S51,通过淀积在氧化层上形成场板结构。
参见图10,场板结构161为多晶硅材质,,该多晶硅可以根据需求进行掺杂,在其他实施例中也可以使用金属场板,例如铝场板。
S61,通过离子注入在衬底和阱区内形成接触区、反掺杂区及连通区。
接触区包括衬底接触区、衬底反掺杂区、阱区反掺杂区以及阱区接触区。衬底接触区设于衬底内,具有第一导电类型。衬底反掺杂区设于衬底内,具有第二导电类型。阱区反掺杂区设于阱区内,具有第一导电类型。阱区接触区设于阱区内,具有第二导电类型。
连通区设于衬底和阱区的横向交界处,且设于衬底反掺杂区和阱区反掺杂区之间,延伸入衬底和阱区内,直接接触衬底和阱区。
参见图11,以制造实施例一所述静电释放保护结构为例,接触区包括衬底接触区132和阱区接触区131。反掺杂区包括衬底反掺杂区134和阱区反掺杂区133。第二隔离区142位于阱区反掺杂区133和连通区135之间,将阱区反掺杂区133和连通区135隔离开。第一隔离区141位于衬底反掺杂区134和连通区135之间,将衬底反掺杂区134和连通区135隔离开。由于第一隔离区141会作为离子注入时的阻挡层,因此第一隔离区141紧贴衬底反掺杂区134和连通区135。
步骤S61之后,还包括形成阳极引线和阴极引线的步骤。以制造实施例一所述静电释放保护结构为例,可以通过淀积在p型衬底110上形成阴极引线,电性连接衬底接触区132、衬底反掺杂区134及场板结构161;在n阱121上形成阳极引线,电性连接阱区反掺杂区133和阱区接触区131。
上述静电释放保护结构的制造方法,与传统的CMOS制造工艺相兼容,具有较低的生产成本。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,例如将本发明的静电释放保护结构中的单阱结构替换为双阱结构,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (5)
1.一种静电释放保护结构的制造方法,包括下列步骤:
提供衬底,所述衬底具有第一导电类型;
在所述衬底内形成第一隔离区和第二隔离区;
通过离子注入在所述衬底内形成具有第二导电类型的阱区,所述第一隔离区处于所述衬底内,所述第二隔离区处于所述阱区内;
通过热氧化形成氧化层,所述氧化层一端设于所述第一隔离区上,另一端设于所述衬底上;或所述氧化层一端设于所述第二隔离区上,另一端设于所述阱区上;
通过淀积在所述氧化层上形成场板结构;
通过离子注入在所述衬底和阱区内形成接触区、反掺杂区及连通区,所述接触区包括设于所述衬底内、具有所述第一导电类型的衬底接触区,设于所述阱区内、具有所述第二导电类型阱区接触区;所述反掺杂区包括设于所述衬底内且位于所述衬底接触区和阱区接触区之间、具有所述第二导电类型的衬底反掺杂区,设于所述阱区内且位于所述衬底接触区和阱区接触区之间、具有所述第一导电类型阱区反掺杂区;所述连通区设于所述衬底和阱区的横向交界处,且设于所述衬底反掺杂区和阱区反掺杂区之间,直接接触所述衬底和阱区。
2.根据权利要求1所述的静电释放保护结构的制造方法,其特征在于,所述通过离子注入在所述衬底和阱区内形成接触区和连通区的步骤之后,还包括形成阳极引线和阴极引线的步骤。
3.根据权利要求1所述的静电释放保护结构的制造方法,其特征在于,所述场板结构的材质为多晶硅。
4.根据权利要求1所述的静电释放保护结构的制造方法,其特征在于,所述第一隔离区和第二隔离区为浅沟槽隔离结构。
5.一种采用如权利要求1-4中任意一项所述的制造方法进行制造的静电释放保护结构,其特征在于,包括:
衬底,具有第一导电类型;
阱区,设于所述衬底内,具有第二导电类型;
衬底接触区,设于所述衬底内,具有所述第一导电类型;
阱区接触区,设于所述阱区内,具有所述第二导电类型;
衬底反掺杂区,设于所述衬底内,且位于所述衬底接触区和阱区接触区之间,具有所述第二导电类型;
阱区反掺杂区,设于所述阱区内,且位于所述衬底接触区和阱区接触区之间,具有所述第一导电类型;
连通区,设于所述衬底和阱区的横向交界处,且设于所述衬底反掺杂区和阱区反掺杂区之间,直接接触所述衬底和阱区;
第一隔离区,设于所述衬底内,且处于所述衬底反掺杂区和连通区之间;
第二隔离区,设于所述阱区内,且处于所述阱区反掺杂区和连通区之间;
氧化层,靠近所述连通区设置,所述氧化层一端设于所述第一隔离区上,另一端设于所述衬底上;或所述氧化层一端设于所述第二隔离区上,另一端设于所述阱区上;所述氧化层不与所述连通区直接接触;
场板结构,设于所述氧化层上。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210130387.3A CN103378087B (zh) | 2012-04-28 | 2012-04-28 | 静电释放保护结构及其制造方法 |
EP13781103.0A EP2717317B1 (en) | 2012-04-28 | 2013-04-27 | Electrostatic discharge protection structure and fabrication method therefor |
JP2014521946A JP5918365B2 (ja) | 2012-04-28 | 2013-04-27 | 静電気放電保護構造及びその製造方法 |
PCT/CN2013/074896 WO2013159746A1 (zh) | 2012-04-28 | 2013-04-27 | 静电释放保护结构及其制造方法 |
US14/130,481 US9343454B2 (en) | 2012-04-28 | 2013-04-27 | Electrostatic discharge protection structure and fabrication method thereof |
US15/055,613 US9780084B2 (en) | 2012-04-28 | 2016-02-28 | Electrostatic discharge protection structure and fabrication method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210130387.3A CN103378087B (zh) | 2012-04-28 | 2012-04-28 | 静电释放保护结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103378087A CN103378087A (zh) | 2013-10-30 |
CN103378087B true CN103378087B (zh) | 2016-02-24 |
Family
ID=49462977
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210130387.3A Active CN103378087B (zh) | 2012-04-28 | 2012-04-28 | 静电释放保护结构及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US9343454B2 (zh) |
EP (1) | EP2717317B1 (zh) |
JP (1) | JP5918365B2 (zh) |
CN (1) | CN103378087B (zh) |
WO (1) | WO2013159746A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8896064B2 (en) * | 2010-10-18 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection circuit |
CN105448979B (zh) * | 2014-06-12 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 横向双扩散场效应管及其形成方法 |
US9621058B2 (en) * | 2015-01-20 | 2017-04-11 | Infineon Technologies Austria Ag | Reducing switching losses associated with a synchronous rectification MOSFET |
CN105185777B (zh) * | 2015-07-30 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | 用于soi工艺静电保护的lvtscr及其制造方法 |
JP6529681B1 (ja) * | 2017-11-13 | 2019-06-12 | 新電元工業株式会社 | ワイドギャップ半導体装置 |
US11342323B2 (en) | 2019-05-30 | 2022-05-24 | Analog Devices, Inc. | High voltage tolerant circuit architecture for applications subject to electrical overstress fault conditions |
US11362203B2 (en) * | 2019-09-26 | 2022-06-14 | Analog Devices, Inc. | Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions |
CN112002692B (zh) * | 2020-08-06 | 2022-10-25 | 杰华特微电子股份有限公司 | 用于静电防护的晶体管及其制造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101290933A (zh) * | 2007-01-23 | 2008-10-22 | 三星电子株式会社 | 静电放电保护装置 |
CN102420245A (zh) * | 2010-09-28 | 2012-04-18 | 比亚迪股份有限公司 | 用于esd防护的低电压触发硅控整流器及其制造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020036326A1 (en) * | 1994-08-11 | 2002-03-28 | Harris Corporation | Analog-to-digital converter and method of fabrication |
US5856214A (en) * | 1996-03-04 | 1999-01-05 | Winbond Electronics Corp. | Method of fabricating a low voltage zener-triggered SCR for ESD protection in integrated circuits |
US6144070A (en) * | 1997-08-29 | 2000-11-07 | Texas Instruments Incorporated | High breakdown-voltage transistor with electrostatic discharge protection |
TW457689B (en) * | 2000-01-11 | 2001-10-01 | Winbond Electronics Corp | High current ESD protection circuit |
TW511269B (en) * | 2001-03-05 | 2002-11-21 | Taiwan Semiconductor Mfg | Silicon-controlled rectifier device having deep well region structure and its application on electrostatic discharge protection circuit |
JP4146672B2 (ja) * | 2002-06-14 | 2008-09-10 | シャープ株式会社 | 静電気保護素子 |
JP3810375B2 (ja) * | 2003-03-14 | 2006-08-16 | ローム株式会社 | 半導体装置 |
CN100364093C (zh) * | 2004-04-06 | 2008-01-23 | 世界先进积体电路股份有限公司 | 具有间隙结构的高压静电放电保护装置 |
US7638857B2 (en) * | 2008-05-07 | 2009-12-29 | United Microelectronics Corp. | Structure of silicon controlled rectifier |
US8193585B2 (en) * | 2009-10-29 | 2012-06-05 | Freescale Semiconductor, Inc. | Semiconductor device with increased snapback voltage |
US8120108B2 (en) * | 2010-01-27 | 2012-02-21 | Texas Instruments Incorporated | High voltage SCRMOS in BiCMOS process technologies |
CN101789428B (zh) * | 2010-03-10 | 2012-01-04 | 浙江大学 | 一种内嵌pmos辅助触发可控硅结构 |
CN102412294B (zh) * | 2010-09-25 | 2013-09-11 | 上海华虹Nec电子有限公司 | 用作静电防护结构的器件 |
-
2012
- 2012-04-28 CN CN201210130387.3A patent/CN103378087B/zh active Active
-
2013
- 2013-04-27 WO PCT/CN2013/074896 patent/WO2013159746A1/zh active Application Filing
- 2013-04-27 US US14/130,481 patent/US9343454B2/en active Active
- 2013-04-27 JP JP2014521946A patent/JP5918365B2/ja active Active
- 2013-04-27 EP EP13781103.0A patent/EP2717317B1/en active Active
-
2016
- 2016-02-28 US US15/055,613 patent/US9780084B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101290933A (zh) * | 2007-01-23 | 2008-10-22 | 三星电子株式会社 | 静电放电保护装置 |
CN102420245A (zh) * | 2010-09-28 | 2012-04-18 | 比亚迪股份有限公司 | 用于esd防护的低电压触发硅控整流器及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2014525147A (ja) | 2014-09-25 |
JP5918365B2 (ja) | 2016-05-18 |
US9343454B2 (en) | 2016-05-17 |
CN103378087A (zh) | 2013-10-30 |
US9780084B2 (en) | 2017-10-03 |
US20140138740A1 (en) | 2014-05-22 |
US20160181237A1 (en) | 2016-06-23 |
EP2717317A4 (en) | 2014-12-03 |
EP2717317A1 (en) | 2014-04-09 |
EP2717317B1 (en) | 2017-03-15 |
WO2013159746A1 (zh) | 2013-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103378087B (zh) | 静电释放保护结构及其制造方法 | |
US9520488B2 (en) | Silicon-controlled rectifier electrostatic discharge protection device and method for forming the same | |
US9911728B2 (en) | Transient voltage suppressor (TVS) with reduced breakdown voltage | |
US8896093B2 (en) | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter | |
US9748346B2 (en) | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter | |
US8338854B2 (en) | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode | |
KR102303403B1 (ko) | 쇼트키 배리어 다이오드 | |
JPWO2015022989A1 (ja) | 半導体装置 | |
JP5043990B2 (ja) | 半導体装置およびその製造方法 | |
TW200308032A (en) | A method and structure for low capacitance ESD robust diodes | |
CN104851919A (zh) | 双向穿通半导体器件及其制造方法 | |
US20210167206A1 (en) | Electrostatic discharge guard ring with complementary drain extended devices | |
CN104716132B (zh) | 一种低触发电压和高维持电压的硅控整流器及其电路 | |
CN105609488A (zh) | 一种用于esd保护的低触发电压scr器件 | |
CN102315212B (zh) | 栅驱动晶闸管电路以及静电保护电路 | |
CN104638021A (zh) | 一种横向恒流二极管及其制造方法 | |
CN105244349A (zh) | 静电保护电路 | |
CN105679836A (zh) | 一种超低电容tvs二极管结构及其制备方法 | |
CN104681603A (zh) | Bcd工艺中纵向双极型晶体管 | |
CN106816463B (zh) | 一种终端结构、半导体器件及其制备方法 | |
CN107425071B (zh) | 一种具有抗单粒子辐照能力的vdmos器件 | |
CN104241265A (zh) | 静电放电保护结构 | |
CN105529364A (zh) | 用于esd保护的pldmos | |
CN104485355A (zh) | Rc-igbt器件 | |
CN114121940A (zh) | 触发电压可调的esd保护结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP03 | Change of name, title or address | ||
CP03 | Change of name, title or address |
Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |