CN102403304B - 一种互连结构及其制作方法 - Google Patents

一种互连结构及其制作方法 Download PDF

Info

Publication number
CN102403304B
CN102403304B CN201110401441.9A CN201110401441A CN102403304B CN 102403304 B CN102403304 B CN 102403304B CN 201110401441 A CN201110401441 A CN 201110401441A CN 102403304 B CN102403304 B CN 102403304B
Authority
CN
China
Prior art keywords
connected medium
interconnection
layer
medium layer
carbon nano
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110401441.9A
Other languages
English (en)
Other versions
CN102403304A (zh
Inventor
赵宇航
康晓旭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Original Assignee
Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Integrated Circuit Research and Development Center Co Ltd filed Critical Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority to CN201110401441.9A priority Critical patent/CN102403304B/zh
Priority to US14/125,313 priority patent/US9312223B2/en
Priority to PCT/CN2011/085150 priority patent/WO2013082844A1/en
Publication of CN102403304A publication Critical patent/CN102403304A/zh
Application granted granted Critical
Publication of CN102403304B publication Critical patent/CN102403304B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53276Conductive materials containing carbon, e.g. fullerenes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors
    • H01L2221/1094Conducting structures comprising nanotubes or nanowires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

本发明涉及一种互连结构及其制作方法,采用牺牲层在互连介质之间形成空腔,使用碳纳米管作为局部互连的通孔互连材料,使用石墨烯纳米带作为金属线互连材料,互连介质中含有空腔,并使用传统CMOS后道铜互连技术应用在中间互连层次和全局互连层次中,可以有效地解决铜互连技术在局部互连尺寸较小时带来的高寄生电阻和寄生电容问题,其中通孔或接触孔内的碳纳米管和用于连接碳纳米管的石墨烯纳米带大幅度降低寄生电阻,互连介质中的空腔有效地降低层间寄生电容,同时石墨烯纳米带很薄,其连线之间的寄生电容也大幅度得到降低;本发明还兼容了现有的CMOS铜互连技术,有效地降低互连RC延迟,提高芯片性能,控制芯片成本。

Description

一种互连结构及其制作方法
技术领域
本发明涉及半导体领域,特别涉及一种互连结构及其制作方法。
背景技术
现在社会信息量急剧增加,对信息的处理、传输和存储提出越来越高的要求。作为信息产业的支柱,半导体产业尤其是CMOS技术在这一需求的推动下,一直按摩尔定律高速发展,成为近50年发展最迅猛的产业。
随着CMOS技术的高速发展,芯片上器件的集成度不断提高,芯片速度也越来越快。为了满足器件集成度和速度的需求,Cu互连逐渐取代传统Al互连成为主流,同时互连的线宽也不断减小,布线密度也越来越高。然而随着Cu互连线宽的进一步减小,由晶界和表面引起的电子散射将造成铜电阻率的大幅度上升,加剧了由电阻和电容(RC)引起的互连延迟,造成芯片整体性能的下降。
器件的延迟和互连的延迟共同决定着电路的最高工作频率。随着器件尺寸的不断缩小,互连延迟已经超越了器件级延迟,成为影响电路工作频率的主要因素;特别是线宽的缩小使Cu线电子输运受到表面和晶粒间界的散射增强,100nm以下Cu线电阻率急剧上升,这将极大地影响电路的性能。low-k介质的使用可以降低互连引入的寄生电容,然而其应用也带来很多其它问题,如集成问题、可靠性问题等等,同时low-k材料介电常数也将在1.5左右达到极限。预计电化学法或CVD法淀积Cu的技术和low-k材料的应用可以继续到2020年,但后Cu互连技术(包括光互连、碳纳米材料互连等技术)的研发已刻不容缓。
石墨烯是一种新颖的材料,它其实是单原子层的石墨,是指由单层碳原子组成的六角型蜂巢晶格平面单层薄膜,是由一个碳原子层厚度组成的二维材料。而石墨烯纳米带则是带状石墨烯,或者可以理解为展开的单壁碳纳米管,或者图形化后的石墨烯结构。石墨烯材料具有非常优异的性能,包括高载流子迁移率、高电流密度、高机械强度、高热传导性能等。
石墨烯纳米带具有了石墨烯材料的优异性能及其自身的独特特性,包括:
1、高电导特性:有报道称其平均自由程可以有几百纳米,高电子迁移率近几个微米;多层石墨纳米带的并联能大幅降低电阻,改善性能,小尺寸特性远远优于铜互连;
2、抗电迁移性能优越:其相邻碳原子依靠SP2价键形成键合,机械强度和抗电迁移特性非常优越10E9A/cm2对比与Cu的10E6A/cm2,能够承载更大的电流密度;
3、热导性能更优越:单层石墨烯的热导有报道为5300W/mK,应用到互连技术中时,可以具有更为优异的散热特性,从而提高互连的可靠性性能;
4、电阻率随不同GNR边缘状态可以由半导体变化为导体,如图1所示,其中Zigzag边缘结构11为导体,而另外一种armchair边缘结构12则是半导体,可以针对不同边界结构来设计其不同的应用范围。
碳纳米管则是一种管状的碳分子,管上每个碳原子采取SP2杂化,相互之间以碳-碳σ键结合起来,形成由六边形组成的蜂窝状结构作为碳纳米管的骨架。每个碳原子上未参与杂化的一对p电子相互之间形成跨越整个碳纳米管的共轭π电子云。按照管子的层数不同,分为单壁碳纳米管和多壁碳纳米管。管子的半径方向非常细,只有纳米尺度,而纳米管的长度可以达到数百微米。
碳纳米管具有非常优异的机械和电学特性,也是一种应用于互连技术的极具潜力的纳米材料,尤其是其沿催化剂的导向性生长特性。
碳基纳米材料的优异特性逐渐被业界所关注,YujiAwano等人早在IEDM2009上发表文章指出石墨烯互连和碳纳米管互连将是后CMOS时候互连技术的一种极具潜力的技术。
现有先进CMOS技术中一般定义互连为3个类型的层次,分别是局部互连、中间互连和全局互连,其中局部互连为尺寸较小的层次,处于互连结构的底层,包括contact、metal1、via1、metal2、via2等层次,因其尺寸较小布线密度较高,更容易受到小尺寸Cu互连中寄生电阻和寄生电容以及热散失引起的性能和可靠性影响;而中间互连和全局互连尺寸比较大,布线密度较低,故而受到小尺寸效应的影响相对较小。
发明内容
本发明的目的是提供一种互连结构及其制作方法,以有效地降低互连RC延迟,提高芯片性能,控制芯片成本。
本发明提供一种互连结构,包括衬底上的互连介质,所述互连介质自下而上包括第一互连介质层和第二互连介质层,还包括贯穿第一互连介质层和第二互连介质层的多个接触孔或通孔,所述第二互连介质层上有用于连接碳纳米管的石墨烯互连线,所述第一互连介质层和碳纳米管之间包括空腔,所述空腔顶部为第二互连介质层,所述空腔底部为衬底。
作为优选:所述石墨烯纳米带为单层或多层。
本发明的还提供一种互连结构的制作方法,包括以下步骤:
在衬底上沉积第一互连介质层;
刻蚀第一互连介质层形成多个支撑柱;
在衬底上沉积牺牲层,研磨牺牲层至支撑柱;
在上述结构表面沉积第二互连介质层;
在对应于相邻支撑柱之间的位置刻蚀第二互连介质层和牺牲层形成多个接触孔或通孔;
去除第二互连介质层和衬底之间的牺牲层;
在上述结构表面沉积金属接触层和碳纳米管催化剂,在碳纳米管催化剂上自下而上生长成碳纳米管,在支撑柱和碳纳米管之间形成密闭空腔;
去除第二互连介质层上的碳纳米管和金属接触层;
在上述结构表面生长石墨烯薄膜,刻蚀石墨烯薄膜形成石墨烯纳米带,形成互连线。
作为优选:所述在衬底上沉积第一互连介质层还包括在衬底上沉积绝缘层。
作为优选:所述牺牲层材料为硅或聚酰胺。
作为优选:所述牺牲层的材料为硅,采用XeF2去除。
作为优选:所述金属接触层和碳纳米管催化剂采用PVD、CVD、PLD或ALD方式沉积。
作为优选:所述金属接触层材料为Ta、TaN、Ti或TiN,所述碳纳米管催化剂的材料为Co、Ni、Pt或Ru。
作为优选:所述在上述结构表面生长石墨烯薄膜为CVD直接沉积或通过物理转移方法形成。
作为优选:所述采用CVD直接沉积石墨烯薄膜工艺中,其方法采用PECVD、微波等离子体CVD、表面波等离子体CVD、LPCVD或APCVD,其工艺温度为300C~1200C。
作为优选:所述在上述结构表面通过物理转移方法形成石墨烯薄膜包括以下步骤:
在一体金属衬底上形成石墨烯薄膜;
在石墨烯薄膜上形成有机玻璃;
去除体金属衬底;
将有机玻璃支撑的石墨烯薄膜贴在上述结构表面;
去除有机玻璃。
作为优选:所述在一体金属衬底上形成石墨烯薄膜采用化学气相沉积或离子注入。
作为优选:所述体金属衬底包括源衬底、源衬底上依次沉积的二氧化硅和金属催化剂。
作为优选:所述石墨烯纳米带为单层或多层。
作为优选:所述石墨烯纳米带的电阻率通过掺杂或离子注入来调节。
作为优选:所述去除第二互连介质层上的碳纳米管和金属接触层采用化学机械研磨。
作为优选:所述采用化学机械研磨去除第二互连介质层上的碳纳米管和金属接触层的步骤还包括在接触孔或通孔区域的碳纳米管上沉积或旋涂互连介质层。
与现有技术相比,本发明将碳纳米互连技术嵌入传统的CMOS局部铜互连技术中,使用碳纳米管作为局部互连的通孔或接触孔的互连材料,使用石墨烯纳米带作为局部互连的金属线互连材料,使用空腔作为局部互连的互连介质,并使用传统CMOS后道铜互连技术应用在中间互连层次和全局互连层次中,可以有效地解决铜互连技术在局部互连尺寸较小时带来的高寄生电阻和寄生电容问题,其中通孔或接触孔内的碳纳米管和用于连接碳纳米管的石墨烯纳米带大幅度降低寄生电阻,互连介质中的空腔有效地降低层间寄生电容,同时石墨烯纳米带很薄,其连线之间的寄生电容也大幅度得到降低;同时兼容了现有的CMOS铜互连技术,有效地降低了互连RC延迟,提高了芯片性能,控制了芯片成本。
附图说明
图1是石墨烯边缘状态示意图。
图2是本发明互连结构的制作方法流程图。
图3a-3j是本发明一实施例制作流程中各个工艺步骤的剖面图。
图4a-4j是本发明另一实施例制作流程中各个工艺步骤的剖面图。
图5a-5d是本发明石墨烯薄膜形成过程中各个工艺步骤的剖面图。
具体实施方式
本发明下面将结合附图作进一步详述:
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施的限制。
其次,本发明利用示意图进行详细描述,在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是实例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。
请参阅图3j所示,一种互连结构,包括衬底200上的互连介质,所述互连介质自下而上包括第一互连介质层203和第二互连介质层205,还包括贯穿第一互连介质层203和第二互连介质层205的多个接触孔或通孔,在所述接触孔或通孔内形成碳纳米管208,所述第二互连介质层205上有用于连接碳纳米管208的石墨烯互连线211,所述第一互连介质层205和碳纳米管208之间包括空腔209,所述空腔209顶部与第二互连介质205相连,所述空腔209底部与衬底200相连。所述石墨烯互连线211为单层或多层。
图2示出了本发明的制作流程图。
请参阅图3a-3j所示,在本实施例中,互连结构的制作方法,包括以下步骤:
在步骤101中,如图3a所示,在衬底200上依次沉积绝缘层201和第一互连介质层202;所述绝缘层201材料为SiN或SiO2,所述绝缘层201的厚度为300-2000埃,所述第一互连介质层202材料为SiO2,所述第一互连介质层202厚度为300-2000埃;
在步骤102中,如图3b所示,刻蚀第一互连介质层202形成多个支撑柱203;
在步骤103中,如图3c所示,在绝缘层201上沉积牺牲层204,研磨牺牲层204使牺牲层204的表面与支撑柱203的表面平齐;所述牺牲层204材料为硅或铬,所述牺牲层204的厚度为500-2000埃,在本实施例中,所述牺牲层204的材料为硅,采用XeF2去除。
在步骤104中,如图3d所示,在上述结构表面沉积第二互连介质层205,所述第二互连介质层205的材料为SiO2、FSG、SiN,所述第二互连介质层205厚度为300-1000埃;
在步骤105中,如图3e所示,在对应于相邻支撑柱203之间的位置刻蚀第二互连介质层205、牺牲层204和绝缘层201形成多个接触孔206;
在步骤106中,如图3f所示,采用释放工艺,去除第二互连介质层205和绝缘层201之间的牺牲层204;
在步骤107中,如图3g所示,在上述结构表面沉积金属接触层207和碳纳米管催化剂(图中未示),在碳纳米管催化剂上自下而上生长成碳纳米管208,在支撑柱203和碳纳米管208之间形成空腔209;所述金属接触层和碳纳米管催化剂采用PVD、CVD、PLD或ALD方式沉积,所述金属接触层材料为Ta、TaN、Ti或TiN,所述碳纳米管催化剂的材料为Co、Ni、Pt或Ru。
化学机械研磨去除第二互连介质层205上的碳纳米管208和金属接触层207,为了达到较好的化学机械研磨效果,如图3h所示,在接触孔区域的碳纳米管208上沉积第三介质层210,研磨去除第二互连介质层205上的碳纳米管208、第三介质层210和金属接触层207,停止在第二互连介质层205上,得到如图3i所示的结构,所述第三介质层210的材料为SiO2或SOG;
如图3j所示,在上述结构表面生长石墨烯薄膜(图中未示),刻蚀石墨烯薄膜形成zigzag边缘结构的石墨烯纳米带,形成第一互连线211。所述在上述结构表面生长石墨烯薄膜为CVD直接沉积或通过物理转移方法形成。所述采用CVD直接沉积石墨烯薄膜工艺中,其方法采用PECVD、微波等离子体CVD、表面波等离子体CVD、LPCVD或APCVD,其工艺温度为300C~1200C。所述在上述结构表面通过物理转移方法形成石墨烯薄膜包括以下步骤:如图5a所示,所述体金属衬底5包括在源衬底51上依次沉积的二氧化硅52和金属催化剂52,所述在体金属衬底5上化学气相沉积或离子注入形成石墨烯薄膜6的步骤为在体金属衬底5上利用CH4气体高温化学气相沉积形成或利用C离子注入形成。如图5b所示,在体金属衬底5上化学气相沉积或离子注入形成石墨烯薄膜6;如图5c所示,在石墨烯薄膜6上形成有机玻璃7;如图5d所示,去除体金属衬底5;将有机玻璃7支撑的石墨烯薄膜6贴在第二互连介质层205上;去除有机玻璃7,在上述结构表面形成石墨烯薄膜。所述石墨烯纳米带为单层或多层。所述石墨烯纳米带的电阻率通过掺杂或离子注入来调节。
另一实施例为制作通孔的第二互连层,请参阅图4a-4j所示
如图4a所示,在第一互连线211上沉积第四互连介质层300和第五互连介质层301,所述第四互连介质层300的材料为SiO2、FSG、SiN,所述第五互连介质层301的材料为SiO2,如图4b所示,刻蚀第五互连介质层301,在对应于相邻碳纳米管208之间的上方形成多个支撑柱302;
如图4c所示,在第四互连介质层300上沉积牺牲层303,研磨牺牲层303使牺牲层303的表面与支撑柱302的表面平齐;
如图4d所示,在上述结构表面沉积第六互连介质层304,所述第六互连介质层304的材料为SiO2、FSG、SiN,所述第六互连介质层304厚度为300-1000埃;
如图4e所示,在对应于相邻支撑柱302之间的位置刻蚀第六互连介质层304、牺牲层303和第四互连介质层300形成多个与第一互连线211接触的通孔305;
如图4f所示,采用释放工艺,去除第六互连介质层304和第四互连介质层300之间的牺牲层303;
如图4g所示,在上述结构表面沉积金属接触层306和碳纳米管催化剂(图中未示),在碳纳米管催化剂上自下而上生长成碳纳米管307,在支撑柱302和碳纳米管307之间形成空腔308;
如图4h所示,化学机械研磨去除第六互连介质层304上的碳纳米管307和金属接触层306,为了达到较好的化学机械研磨效果,如图3h所示,在通孔区域的碳纳米管307上沉积或旋涂第七互连介质层309,所述第七介质层309的材料为SiO2或SOG,研磨去除第六互连介质层304上的碳纳米管307、第七互连介质层309和金属接触层306,停止在第六互连介质层304上,如图4i所示;
如图4g所示,在上述结构表面生长石墨烯薄膜(图中未示),刻蚀石墨烯薄膜形成zigzag边缘结构的石墨烯纳米带,形成第二互连线310。
所述第二互连层的制作工艺条件和材料与第一互连层的相同。采用上述步骤形成第三、第四或第五后续互连层。本发明将碳纳米互连技术嵌入传统的CMOS局部铜互连技术中,使用碳纳米管作为局部互连的通孔或接触孔的互连材料,使用石墨烯纳米带作为局部互连的金属线互连材料,使用空腔作为局部互连的互连介质,并使用传统CMOS后道铜互连技术应用在中间互连层次和全局互连层次中,可以有效地解决铜互连技术在局部互连尺寸较小时带来的高寄生电阻和寄生电容问题,其中通孔或接触孔内的碳纳米管和用于连接碳纳米管的石墨烯纳米带大幅度降低寄生电阻,互连介质中的空腔有效地降低层间寄生电容,同时石墨烯纳米带很薄,其连线之间的寄生电容也大幅度得到降低;同时本发明兼容了现有的CMOS铜互连技术,有效地降低了互连RC延迟,提高了芯片性能,控制了芯片成本。
以上所述仅为本发明的较佳实施例,凡依本发明权利要求范围所做的均等变化与修饰,皆应属本发明权利要求的涵盖范围。

Claims (17)

1.一种互连结构,包括衬底上的互连介质,其特征在于:所述互连介质自下而上包括第一互连介质层和第二互连介质层,还包括贯穿第一互连介质层和第二互连介质层的多个接触孔或通孔,在所述接触孔或通孔内形成碳纳米管,所述第二互连介质层上有用于连接碳纳米管的石墨烯互连线,所述第一互连介质层和碳纳米管之间包括空腔,所述空腔顶部为第二互连介质,所述空腔底部为衬底;其中,接触孔或通孔位于所述空腔上方对应的所述第二互连介质层部分,所述碳纳米管穿过所述接触孔或通孔进入所述空腔并且接触到所述衬底;所述空腔中还设置有多个支撑柱。
2.根据权利要求1所述的互连结构,其特征在于:所述石墨烯互连线为单层或多层。
3.一种互连结构的制作方法,其特征在于,包括以下步骤:
在衬底上沉积第一互连介质层;
刻蚀第一互连介质层形成多个支撑柱;
在衬底上沉积牺牲层,研磨牺牲层使牺牲层表面与支撑柱表面平齐;
在上述结构表面沉积第二互连介质层;
在对应于相邻支撑柱之间的位置刻蚀第二互连介质层和牺牲层形成多个接触孔或通孔;
去除第二互连介质层和衬底之间的牺牲层;
在上述结构表面沉积金属接触层和碳纳米管催化剂,在碳纳米管催化剂上自下而上生长形成碳纳米管,在支撑柱和碳纳米管之间形成密闭空腔;
去除第二互连介质层上的碳纳米管和金属接触层;
在上述结构表面生长石墨烯薄膜,刻蚀石墨烯薄膜形成石墨烯纳米带,形成互连线。
4.根据权利要求3所述的互连结构的制作方法,其特征在于:所述在衬底上沉积第一互连介质层还包括在衬底上沉积绝缘层。
5.根据权利要求3所述的互连结构的制作方法,其特征在于:所述牺牲层材料为硅或聚酰胺。
6.根据权利要求5所述的互连结构的制作方法,其特征在于:所述牺牲层的材料为硅,采用XeF2去除。
7.根据权利要求3所述的互连结构的制作方法,其特征在于:所述金属接触层和碳纳米管催化剂采用PVD、CVD、PLD或ALD方式沉积。
8.根据权利要求7所述的互连结构的制作方法,其特征在于:所述金属接触层材料为Ta、TaN、Ti或TiN,所述碳纳米管催化剂的材料为Co、Ni、Pt或Ru。
9.根据权利要求3所述的互连结构的制作方法,其特征在于,所述在上述结构表面生长石墨烯薄膜为CVD直接沉积或通过物理转移方法形成。
10.根据权利要求9所述的互连结构的制作方法,其特征在于:所述采用CVD直接沉积石墨烯薄膜工艺中,其方法采用PECVD、微波等离子体CVD、表面波等离子体CVD、LPCVD或APCVD,其工艺温度为300℃~1200℃。
11.根据权利要求9所述的互连结构的制作方法,其特征在于,所述在上述结构表面通过物理转移方法形成石墨烯薄膜包括以下步骤:
在一体金属衬底上形成石墨烯薄膜;
在石墨烯薄膜上形成有机玻璃;
去除体金属衬底;
将有机玻璃支撑的石墨烯薄膜贴在第二互连介质层上;
去除有机玻璃。
12.根据权利要求11所述的互连结构的制作方法,其特征在于:所述在一体金属衬底上形成石墨烯薄膜采用化学气相沉积或离子注入。
13.根据权利要求11所述的互连结构的制作方法,其特征在于:所述体金属衬底包括源衬底、源衬底上依次沉积的二氧化硅和金属催化剂。
14.根据权利要求3所述的互连结构的制作方法,其特征在于:所述石墨烯纳米带为单层或多层。
15.根据权利要求3所述的互连结构的制作方法,其特征在于:所述石墨烯纳米带的电阻率通过掺杂或离子注入来调节。
16.根据权利要求3所述的互连结构的制作方法,其特征在于:所述去除第二互连介质层上的碳纳米管和金属接触层采用化学机械研磨。
17.根据权利要求16所述的互连结构的制作方法,其特征在于:所述采用化学机械研磨去除第二互连介质层上的碳纳米管和金属接触层的步骤还包括在接触孔或通孔区域的碳纳米管上沉积或旋涂互连介质层。
CN201110401441.9A 2011-12-06 2011-12-06 一种互连结构及其制作方法 Active CN102403304B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201110401441.9A CN102403304B (zh) 2011-12-06 2011-12-06 一种互连结构及其制作方法
US14/125,313 US9312223B2 (en) 2011-12-06 2011-12-31 Method for fabricating a carbon nanotube interconnection structure
PCT/CN2011/085150 WO2013082844A1 (en) 2011-12-06 2011-12-31 Interconnection structure and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110401441.9A CN102403304B (zh) 2011-12-06 2011-12-06 一种互连结构及其制作方法

Publications (2)

Publication Number Publication Date
CN102403304A CN102403304A (zh) 2012-04-04
CN102403304B true CN102403304B (zh) 2016-03-16

Family

ID=45885356

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110401441.9A Active CN102403304B (zh) 2011-12-06 2011-12-06 一种互连结构及其制作方法

Country Status (3)

Country Link
US (1) US9312223B2 (zh)
CN (1) CN102403304B (zh)
WO (1) WO2013082844A1 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103187391B (zh) 2011-12-31 2016-01-06 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
CN103456679B (zh) * 2012-06-05 2016-02-03 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
CN103456677A (zh) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
CN103531525B (zh) * 2012-07-02 2016-01-06 中芯国际集成电路制造(上海)有限公司 金属互连结构的制作方法
TWI466253B (zh) * 2012-10-08 2014-12-21 Ind Tech Res Inst 雙相介金屬接點結構及其製作方法
CN102956611B (zh) * 2012-11-12 2017-03-15 上海集成电路研发中心有限公司 一种空气隙/石墨烯互连结构及其制备方法
US9202743B2 (en) 2012-12-17 2015-12-01 International Business Machines Corporation Graphene and metal interconnects
US9293412B2 (en) 2012-12-17 2016-03-22 International Business Machines Corporation Graphene and metal interconnects with reduced contact resistance
JP5624600B2 (ja) * 2012-12-27 2014-11-12 株式会社東芝 配線及び半導体装置の製造方法
US9006095B2 (en) * 2013-02-19 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9257391B2 (en) * 2013-04-30 2016-02-09 GlobalFoundries, Inc. Hybrid graphene-metal interconnect structures
US9431346B2 (en) 2013-04-30 2016-08-30 GlobalFoundries, Inc. Graphene-metal E-fuse
JP6129772B2 (ja) * 2014-03-14 2017-05-17 株式会社東芝 半導体装置及び半導体装置の製造方法
JP6077076B1 (ja) 2015-09-11 2017-02-08 株式会社東芝 グラフェン配線構造及びグラフェン配線構造の作製方法
CN106847790A (zh) * 2017-01-17 2017-06-13 华南理工大学 一种集成碳纳米管和石墨烯的互连结构及其制造方法
CN107369896A (zh) * 2017-02-17 2017-11-21 全普光电科技(上海)有限公司 天线结构及其制备方法、超薄手机及其制备方法
CN107359236A (zh) * 2017-02-17 2017-11-17 全普光电科技(上海)有限公司 石墨烯薄膜、制备方法及半导体器件
CN107168002A (zh) * 2017-02-17 2017-09-15 全普光电科技(上海)有限公司 柔性薄膜幕、制备方法、投影方法以及投影仪
CN107464995A (zh) * 2017-08-01 2017-12-12 全普光电科技(上海)有限公司 一种薄膜天线及其制备方法
CN108336071B (zh) * 2018-02-12 2019-09-24 湖州一力电子有限公司 一种石墨烯电容及其制造方法
CN113555227B (zh) * 2021-07-19 2022-12-27 上海集成电路制造创新中心有限公司 片上全固态超级电容及其制备方法
CN113539955B (zh) * 2021-08-05 2024-02-06 长鑫存储技术有限公司 半导体结构及其制作方法
CN114604855A (zh) * 2022-03-14 2022-06-10 无锡东恒新能源科技有限公司 一种基于原子层沉积催化合成单壁碳纳米管的方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100369205C (zh) * 2003-05-01 2008-02-13 三星电子株式会社 用碳纳米管形成半导体装置用导电线的方法及半导体装置
CN101573797A (zh) * 2006-09-04 2009-11-04 皇家飞利浦电子股份有限公司 互连结构中的碳纳米结构生长的控制

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100314094B1 (ko) * 1999-08-12 2001-11-15 김순택 전기 영동법을 이용한 카본나노튜브 필드 에미터의 제조 방법
KR100480773B1 (ko) * 2000-01-07 2005-04-06 삼성에스디아이 주식회사 카본 나노 튜브를 이용한 3극 전계방출소자의 제작방법
US6448701B1 (en) * 2001-03-09 2002-09-10 The United States Of America As Represented By The Secretary Of The Navy Self-aligned integrally gated nanofilament field emitter cell and array
US6448177B1 (en) * 2001-03-27 2002-09-10 Intle Corporation Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
US6924538B2 (en) * 2001-07-25 2005-08-02 Nantero, Inc. Devices having vertically-disposed nanofabric articles and methods of making the same
WO2004051726A1 (ja) * 2002-11-29 2004-06-17 Nec Corporation 半導体装置およびその製造方法
JP4208668B2 (ja) * 2003-08-22 2009-01-14 富士通株式会社 半導体装置およびその製造方法
DE10359424B4 (de) * 2003-12-17 2007-08-02 Infineon Technologies Ag Umverdrahtungsplatte für Halbleiterbauteile mit engem Anschlussraster und Verfahren zur Herstellung derselben
US7135773B2 (en) * 2004-02-26 2006-11-14 International Business Machines Corporation Integrated circuit chip utilizing carbon nanotube composite interconnection vias
US20060066217A1 (en) * 2004-09-27 2006-03-30 Son Jong W Cathode structure for field emission device
KR100822799B1 (ko) * 2006-04-25 2008-04-17 삼성전자주식회사 나노크기의 도전성 구조물을 위한 선택적인 촉매 형성 방법및 선택적인 나노크기의 도전성 구조물 형성 방법
DE102007050843A1 (de) * 2006-10-26 2008-05-21 Samsung Electronics Co., Ltd., Suwon Integrierte Schaltung mit Kohlenstoffnanoröhren und Verfahren zu deren Herstellung unter Verwendung von geschützten Katalysatorschichten
FR2910706B1 (fr) * 2006-12-21 2009-03-20 Commissariat Energie Atomique Element d'interconnexion a base de nanotubes de carbone
JP2009070911A (ja) * 2007-09-11 2009-04-02 Fujitsu Ltd 配線構造体、半導体装置および配線構造体の製造方法
US8298911B2 (en) * 2009-03-26 2012-10-30 Samsung Electronics Co., Ltd. Methods of forming wiring structures
JP5439120B2 (ja) * 2009-11-02 2014-03-12 株式会社東芝 半導体装置およびその製造方法
JP5238775B2 (ja) * 2010-08-25 2013-07-17 株式会社東芝 カーボンナノチューブ配線の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100369205C (zh) * 2003-05-01 2008-02-13 三星电子株式会社 用碳纳米管形成半导体装置用导电线的方法及半导体装置
CN101573797A (zh) * 2006-09-04 2009-11-04 皇家飞利浦电子股份有限公司 互连结构中的碳纳米结构生长的控制

Also Published As

Publication number Publication date
CN102403304A (zh) 2012-04-04
US9312223B2 (en) 2016-04-12
US20140138829A1 (en) 2014-05-22
WO2013082844A1 (en) 2013-06-13

Similar Documents

Publication Publication Date Title
CN102403304B (zh) 一种互连结构及其制作方法
Vyas et al. On-chip interconnect conductor materials for end-of-roadmap technology nodes
CN1996634B (zh) 碳纳米管相变存储器的制作方法
TWI460839B (zh) 石墨烯(graphene)內連線及其製造方法
CN105206561B (zh) 互连结构的形成方法和半导体结构
CN103456677A (zh) 半导体器件及其制造方法
KR100858453B1 (ko) 전기적 접속 구조, 그 제조 방법 및 반도체 집적 회로 장치
US9305838B2 (en) BEOL interconnect with carbon nanotubes
Yeh et al. Scalable graphite/copper bishell composite for high-performance interconnects
JP2009070911A (ja) 配線構造体、半導体装置および配線構造体の製造方法
JP2008137846A (ja) 炭素細長構造束状体、その製造方法および電子素子
US9355900B2 (en) Semiconductor device and method of manufacturing the same
Rai et al. Carbon nanotube as a VLSI interconnect
CN102956611B (zh) 一种空气隙/石墨烯互连结构及其制备方法
CN101276802A (zh) 布线结构及其形成方法
JP2014051413A (ja) グラフェン−cnt構造及びその製造方法
JP6180977B2 (ja) グラフェン配線及び半導体装置
CN103456679B (zh) 互连结构及其制造方法
JP5233125B2 (ja) 半導体装置
US20120112364A1 (en) Wiring structure of semiconductor device
CN103594378A (zh) 凹槽结构的悬空石墨烯沟道晶体管的制备方法
Vyas et al. Effect of improved contact on reliability of sub-60 nm carbon nanotube vias
JP5289678B2 (ja) 電界効果型トランジスタ
JP5637231B2 (ja) 電界効果型トランジスタの製造方法
US20240014071A1 (en) Cmos-compatible graphene structures, interconnects and fabrication methods

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant