CN102373492A - Method for carrying out selective electroplating on surface of circuit board, and circuit board - Google Patents
Method for carrying out selective electroplating on surface of circuit board, and circuit board Download PDFInfo
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- CN102373492A CN102373492A CN2010102540928A CN201010254092A CN102373492A CN 102373492 A CN102373492 A CN 102373492A CN 2010102540928 A CN2010102540928 A CN 2010102540928A CN 201010254092 A CN201010254092 A CN 201010254092A CN 102373492 A CN102373492 A CN 102373492A
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Abstract
The invention discloses a method for carrying our selective electroplating on the surface of a circuit board, and a circuit board. The method comprises steps that: a conductive layer is coated on the surface of a circuit board; an anti-electroplating protective layer is coated on non-electroplating areas on the surface of the conductive layer; electroplating is carried out upon electroplating areas which are not coated with the anti-electroplating protective layer, such that an electroplated metal layer processed through a primary surface treatment is obtained; a non-primary surface treatment is carried out, wherein an anti-electroplating protective layer is coated on the surface formed by the previous surface treatment, and on non-electroplating areas of the non-primary surface treatment; electroplating is carried out upon electroplating areas which are not coated with the anti-electroplating protective layer, such that an electroplated metal layer processed through a non-primary surface treatment is obtained; the anti-electroplating protective layer is removed, and the conductive layer which is not coated with the electroplated metal layer is removed by etching. With the method provided by the invention, electroplating lead wires are not required to be arranged on the surface of the circuit board, such that an influence of the electroplating lead wires on wiring density can be avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the Method and circuits plate that circuit board surface carries out selective electroplating.
Background technology
In the circuit board making process, need be to the handling of circuit board surface, as thick metal plated, electroless plating NiPdAu etc.For the semiconductor product of lower procedure for the lead-in wire bonding, the surface treatment of its para-linkage position requires relatively stricter.
Because the noble metal cost to the surface treatment of the circuit card of this series products is required is higher; So generally all adopt surface treatment of selectivity second time electroplating or selectivity secondary deposition surface metal; Only the special pattern zone is electroplated, to reduce the consumption of such noble metal.
The general electroplate lead wire mode that adopts realizes the electroplating surface of circuit card is handled in the prior art; This mode need be used to connect the electroplate lead wire of electroplating clamp in the surface arrangement of circuit card; Be used at its electric action of electroplating process; Because electroplate lead wire need occupy the space of circuit board surface, thereby makes the wiring density of circuit board surface be affected.
And along with the miniaturized and the slimming of unicircuit development; Requirement to circuit card also develops towards light, thin, short, little direction; This wiring density to circuit card proposes increasingly high requirement; Promptly hope to obtain the more wiring density of crypto set, reach the purpose that reduces the circuit card overall dimensions; Or not under the condition of enlarged, wiring density is increased with integrated more function in available circuit slab integral size.
Therefore, the circuit board surface processing mode of Traditional use electroplate lead wire, more next obvious to the influence of wiring density, the existence of electroplate lead wire has had a strong impact on wiring density, thereby can't satisfy the frivolous and miniaturized requirement of circuit card.
Summary of the invention
The Method and circuits plate that the embodiment of the invention provides a kind of circuit board surface to carry out selective electroplating carries out the problem that electroplating surface is handled influences the circuit board surface wiring density in order to the mode that solves the employing electroplate lead wire that exists in the prior art to circuit card.
A kind of method of circuit board surface selective electroplating comprises:
Cover conductive layer at circuit board surface;
Electroless plating zone on the surface of said conductive layer covers the anti-plate resist; And do not electroplated by the plating area of anti-plate resist covering, obtain surface-treated electroplated metal layer for the first time;
Carry out the non-surface treatment first time, wherein, on the surface that last once surface treatment forms, at said non-surface-treated electroless plating zone covering first time anti-plate resist; And do not electroplating in the plating area that is covered by the anti-plate resist, obtain said non-first time of surface-treated electroplated metal layer;
Take off the anti-plate resist, and etch away the conductive layer that is not covered by electroplated metal layer.
A kind of circuit card of making through aforesaid method.
Beneficial effect of the present invention is following:
The circuit board surface that the embodiment of the invention provides carries out the Method and circuits plate of selective electroplating, covers conductive layer at circuit board surface; Electroless plating zone on the surface of said conductive layer covers the anti-plate resist; And do not electroplated by the plating area of anti-plate resist covering, obtain surface-treated electroplated metal layer for the first time; Carry out the non-surface treatment first time, wherein, on the surface that last once surface treatment forms, at said non-surface-treated electroless plating zone covering first time anti-plate resist; And do not electroplating in the plating area that is covered by the anti-plate resist, obtain said non-first time of surface-treated electroplated metal layer; Take off the anti-plate resist, and etch away the conductive layer that is not covered by electroplated metal layer.This method is through covering the zone that need not carry out electroplating processes on the circuit card; Realized only in the appointment plating area of circuit card, electroplating; This mode is removed the making of electroplate lead wire from; Practice thrift the required circuit board space that takies of electroplate lead wire, improved the wiring density of surface-treated layer.Simultaneously,, reduced the usage quantity of noble metal, practiced thrift the cost of manufacture of circuit board surface electroplating processes owing to can realize electroplating processes in the designated area accurately.
Description of drawings
Fig. 1 carries out the schema of the method for selective electroplating for circuit board surface in the embodiment of the invention one;
Fig. 2 carries out the schema of the method for selective electroplating for circuit board surface in the embodiment of the invention two;
Fig. 3 is the structural representation of the circuit card that electroplated is handled in the embodiment of the invention two;
Fig. 4 is the structural representation of the circuit card behind the splash conductive layer in the embodiment of the invention two;
Fig. 5 is the structural representation of the circuit card behind the pad pasting for the first time in the embodiment of the invention two;
Fig. 6 is the structural representation of the circuit card after the exposure for the first time in the embodiment of the invention two;
Fig. 7 is the structural representation of the circuit card after developing for the first time in the embodiment of the invention two;
Fig. 8 is the structural representation of the circuit card after electroplating for the first time in the embodiment of the invention two;
Fig. 9 is the structural representation of the circuit card behind the pad pasting for the second time in the embodiment of the invention two;
Figure 10 is a kind of structural representation of the circuit card after the exposure for the second time in the embodiment of the invention two;
Figure 11 is the another kind of structural representation of the circuit card after the exposure for the second time in the embodiment of the invention two;
Figure 12 is another structural representation of the circuit card after the exposure for the second time in the embodiment of the invention two;
Figure 13 is the structural representation behind the circuit card second development of Figure 10 in the embodiment of the invention two;
Figure 14 is the structural representation behind the circuit card second development of Figure 11 in the embodiment of the invention two;
Figure 15 is the structural representation behind the circuit card second development of Figure 12 in the embodiment of the invention two;
Figure 16 is the structural representation after the circuit card of Figure 13 in the embodiment of the invention two is electroplated for the second time;
Figure 17 is the structural representation after the circuit card of Figure 14 in the embodiment of the invention two is electroplated for the second time;
Figure 18 is the structural representation after the circuit card of Figure 15 in the embodiment of the invention two is electroplated for the second time;
Figure 19 is the structural representation after the circuit card of Figure 16 in the embodiment of the invention two moves back film;
Figure 20 is the structural representation after the circuit card of Figure 17 in the embodiment of the invention two moves back film;
Figure 21 is the structural representation after the circuit card of Figure 18 in the embodiment of the invention two moves back film;
Figure 22 is the structural representation after the circuit card etching of Figure 19 in the embodiment of the invention two;
Figure 23 is the structural representation after the circuit card etching of Figure 20 in the embodiment of the invention two;
Figure 24 is the structural representation after the circuit card etching of Figure 21 in the embodiment of the invention two.
Embodiment
Embodiment one
The method of the circuit board surface selective electroplating that the embodiment of the invention one provides through not needing galvanized zone to cover the anti-plate resist, realizes circuit board surface is needed the electroplating processes of galvanized graphics field, and its flow process is as shown in Figure 1, and performing step is following:
Step S11: cover conductive layer at circuit board surface.
Before the outermost layer circuit of semiconductor product is made, at first at the thin metal of base material (not carrying out the circuit card that electroplating surface is handled) surface coverage one deck of circuit card as conductive layer.This conductive layer can adopt the mode of splash, conducting metals such as splash copper, titanium.
Preferable, this conductive layer can not use the metal identical with the electroplating surface processing layer.That is to say, select the electroplated metal layer metal inequality of the one deck on surface with follow-up electroplated for use, obtain said conductive layer in the circuit board surface splash.Such as: when electroplating surface metal layer was the electronickelling gold, conductive layer can not be thought nickel and gold.That is to say, when electroplating multilayer, can only guarantee that conductive layer is different with the metal of last galvanized electroplated metal layer to get final product that certain conductive layer and each electroplated metal layer select for use metal all inequality also to be fine.
This conductive layer thickness is generally thinner, is about 0.2～1.5um, in order to avoid follow-up conductive layer etching is brought bad influence.Preferably this conductive layer thickness is 0.8-1.2 μ m, and more preferably this conductive layer thickness is 1.0 μ m.
Step S12: the surface at conductive layer covers anti-plate resist (the first anti-plate resist) in surface-treated electroless plating zone for the first time.
Need not carrying out for the first time on the surface of conductive layer, galvanized zone (also electroplating the one-tenth plating area first time or the first time graphics field) covering anti-plate resist is in order can only to be come out in the graphics field that needs electroplating surface.
Preferable, the effect when electroplating for the follow-up first time is preferable, and the thickness of the first anti-plate resist of covering generally needs more than the galvanized plated metal layer thickness 5 μ m greater than this.Preferably the first anti-plate protective layer thickness is 5-15 μ m, and more preferably the first anti-plate protective layer thickness is 5-8 μ m.
Preferable, the process that covers the first anti-plate resist can be earlier whole conductive layer to be covered the sensitization resist plating, through treating processess such as figure transfer exposure, figure transfer developments, is come out in the graphics field that needs electroplating surface again.
Step S13: the plating first time is carried out in the zone that does not cover the first anti-plate resist at the conductive layer upper surface, obtains first electroplated metal layer.
Promptly to the first time plating area electroplate, through after the electroplating processes for the first time, obtain surface-treated electroplated metal layer for the first time, at this moment, the circuit card upper surface is covered by the first sensitization resist plating layer and electroplated metal layer for the first time.
Step S14: on the circuit board surface that first time surface treatment forms, surface-treated electroless plating zone covers anti-plate resist (the second anti-plate resist) for the second time.
The circuit board surface that surface treatment for the first time forms is the upper surface of first electroplated metal layer and the first anti-plate resist, and surface-treated electroless plating zone is for electroplating for the second time the zone outside the graphics field for the second time.
The surface treatment for the second time of first electroplated metal layer and the first anti-plate resist upper surface need not carry out galvanized zone cover the second anti-plate resist be for can be only with needs for the second time galvanized zone (promptly electroplating the graphics field second time) come out.
Preferable, the effect when electroplating for the follow-up second time is preferable, and the thickness of anti-plate resist is generally also greater than more than the galvanized second plated metal layer thickness of the needs 5 μ m for the second time.Preferably the second anti-plate protective layer thickness is 5-15 μ m, and more preferably the second anti-plate protective layer thickness is 5-8 μ m.
Preferable; The process that covers the second anti-plate resist can be earlier with whole first electroplated metal layer and the resist plating of anti-plate resist upper surface covering sensitization for the first time; Through treating processess such as figure transfer exposure, figure transfer developments, come out in the graphics field that needs electroplating surface again.Specifically comprise following several kinds of situation:
When said non-first time surface treatment, the electroplated metal layer that forms when covering last surface treatment so that the sensitization resist plating is local is in order to form the electroplated metal layer of the local electroplated metal layer that forms when covering last surface treatment.
When said non-first time surface treatment, the electroplated metal layer that forms when covering last surface treatment fully, the electroplated metal layer of the electroplated metal layer that forms when covering last surface treatment fully in order to form with the sensitization resist plating.
When said non-first time surface treatment; The first part of the electroplated metal layer that forms when covering last surface treatment so that the sensitization resist plating is local is in order to the electroplated metal layer of the first part that forms the local electroplated metal layer that forms when covering last surface treatment; The second section of the electroplated metal layer that forms when covering last surface treatment fully with the sensitization resist plating, the electroplated metal layer of the second section of the electroplated metal layer that forms when covering last surface treatment fully in order to form.
Above-mentioned when non-first time surface treatment, the regional extent of the sensitization resist plating that the part is covered and/or covers is fully confirmed according to the aligning accuracy of exposure sources.
When handling, cover and all cover, specifically comprise (is example to cover the sensitization resist plating) to the part to above-mentioned several kinds of situation:
Situation one: when plating for the second time need be carried out the part covering to primary parcel plating zone; Develop through surface-treated figure transfer exposure for the second time and figure transfer; The surface treatment second time need on once galvanized parcel plating zone carry out the part when covering, the zone of removing the sensitization resist plating in this parcel plating zone less than on once remove the sensitization resist plating in this zone during surface treatment the zone.
Situation two: when plating for the second time need all cover primary parcel plating zone; Develop through surface-treated figure transfer exposure for the second time and figure transfer; The surface treatment second time need on once galvanized parcel plating zone when all covering, the zone of the removal sensitization resist plating in this parcel plating zone greater than on once remove the sensitization resist plating in this zone during surface treatment the zone.
Step S15: carry out the second time in the surface area that does not cover the second anti-plate resist and electroplate, obtain second electroplated metal layer.
This step the first anti-plate resist and the second anti-plate resist cover that the back exposed first time electroplated metal layer above carry out plating second time.After the process electroplating processes second time, the circuit card upper surface sometimes also possibly comprised the first anti-plate resist of exposed portions serve certainly by the second time electroplated metal layer and the second anti-plate resist.
Step S16: take off the second anti-plate resist and the first anti-plate resist.
This step makes second electroplated metal layer, first electroplated metal layer that is not covered by second electroplated metal layer and the conductive layer that do not covered by twice electroplated metal layer all comes out.
Step S17: etch away not by the conductive layer of first electroplated metal layer and the covering of second electroplated metal layer.
The conductive layer that this step adopts the mode fast-etching of chemical little erosion not to be capped keeps electroplated metal layer 5 and the electroplated metal layer second time for the first time, accomplishes the selective electroplating on semiconductor product surface and handles.
Preferable, the employed solution of chemical little erosion according to conductive layer, for the first time electroplated metal layer and for the second time the metal selected for use of electroplated metal layer select, generally can etch away the conductive layer that is not capped, electroplated metal layer is good and do not influence for the second time.
For example: conductive layer adopts the metallic copper splash, and electroplated metal layer difference electronickelling for the second time and gold then can adopt properly mixed ydrogen peroxide 50 and vitriolic mixing solutions to carry out etching, and the metallic copper that conductive layer is not capped etches away.
Preferable, such scheme can be not limited only to two-layer plating, can expand to multilayer.Then this moment first electroplated metal layer implementation procedure with above-mentioned step S11-S13, follow-up electroplated metal layer, performing step is with reference to step S14 and step S15.That is to say; When not being when electroplating for the first time; On the last circuit board surface that once electroplate to form, this galvanized electroless plating zone covers anti-plate resist, promptly covers the anti-plate resist in last once galvanized electroplated metal layer and the anti-plate resist upper surface that covers before this, zone outside this galvanized graphics field; And, obtain this electroplated metal layer not electroplated by anti-plate resist region covered.
Need carry out the part when covering and/or all covering to galvanized subregion of last time when this plating, also handle with for the first time galvanized processing mode with reference to electroplating for the second time among the step S14 relatively.
Embodiment two
The method of the circuit board surface selective electroplating that the embodiment of the invention two provides; Pass through twice pad pasting, exposure, development and electroplating process with a specific examples explanation; Realization is to the electroplating processes of the galvanized graphics field of circuit board surface needs, and the anti-plate resist with covering among this embodiment is that the sensitization resist plating once was that example describes.Its flow process is as shown in Figure 2, and performing step is following:
Step S21: the circuit board surface of handling at electroplated covers conductive layer.
The treating processes of this step repeats no more with above-mentioned step S11 here.
For example: the structure of the circuit card 1 that electroplated is handled is as shown in Figure 3.Structure on circuit card 1 after the splash conductive layer 2 is as shown in Figure 4.
Step S22: cover one deck sensitization resist plating at the conductive layer upper surface.
This step is the step of the pad pasting first time, covers one deck sensitization resist plating 3 and realizes that the board structure of circuit behind the pad pastings first time is as shown in Figure 5.
Cover one deck sensitization resist plating and specifically adopt one of following manner: manually pad pasting, pad pasting, vacuum pad pasting, silk screen printing, coating, spraying and roller coating automatically.Wherein, adopt manual pad pasting, when automatically the mode of pad pasting or vacuum pad pasting covers the sensitization resist plating, the mode that adopts dry film to make; When the mode of employing silk screen printing, coating, spraying or roller coating covers the sensitization resist plating, the mode that adopts wet film to make.
Step S23: the sensitization resist plating of plating area carries out the figure transfer exposure first time to being positioned at for the first time.
This step is the step of exposing first time.
For example: on this layer sensitization resist plating 3 that covers, carry out the figure transfer exposure first time.This layer sensitization resist plating adopts dry film, and build is selected with reference to electroplating the live width distance between centers of tracks that needs electroplated metal layer thickness and circuit board line layer for the first time.Preferable, more than the 5um of thickness greater than the first plated metal layer thickness of general requirement sensitization resist plating (dry film), this sensitization resist plating (dry film) can satisfy the requirement of the live width distance between centers of tracks of line layer simultaneously.The technical data that the relevant selected dry film of technical parameter reference supplier provides is selected according to actual needs.Structure after the exposure is as shown in Figure 6, has wherein pointed out to electroplate the first time after the exposure sensitization resist plating 3 of the zone correspondence outside the graphics field and has electroplated the corresponding sensitization resist plating 4 in graphics field the first time after the exposure.
Step S24: the sensitization resist plating to after the exposure for the first time carries out the figure transfer development treatment first time.
This step is the step of developing first time, and purpose is to remove the sensitization resist plating that cover on the galvanized graphics field first time, obtains covering the first sensitization resist plating layer in the zone outside the first time of the galvanized graphics field.
Continue to use the example of top, promptly remove electroplating the corresponding sensitization resist plating in graphics field 4 first time after the exposure on the circuit card shown in Figure 6 through the figure transfer development first time.Stay at conductive layer surface and for the first time to electroplate the sensitization resist plating 3 in the zone outside the graphics field, obtain the first above-mentioned sensitization resist plating layer.Board structure of circuit after developing for the first time is as shown in Figure 7, has wherein removed the sensitization resist plating 4 after the exposure, has only stayed the sensitization resist plating 3 after the exposure.
When carrying out the figure transfer development, relevant technical parameter is with reference to confirming according to selected sensitization resist plating.
Above-mentioned steps S22, step S23, step S24 are implemented in the for the first time galvanized electroless plating of conductive layer upper surface zone and cover the first sensitization resist plating layer.
Step S25: the plating first time is carried out in the zone that does not cover the first sensitization resist plating layer at the conductive layer upper surface.
Carry out electroplating the galvanized first time for the first time the conductive layer surface of graphics field at the needs that expose of for the first time developing and electroplate conductive metal level, obtain first electroplated metal layer through electroplating for the first time.
Continue to use top example, as shown in Figure 8, after electroplating for the first time, conductive layer 2 surfaces are main not to be developed the first sensitization resist plating, 3 coverings of removing by first electroplated metal layer 5 with having made public.
Step S26: electroplate the circuit board surface that forms first and cover one deck sensitization resist plating.
This step is the step of pad pasting for the second time, and is as shown in Figure 9, at first electroplated metal layer 5 be not developed the first sensitization resist plating layer, 3 upper surface covering one deck sensitization resist plating 6 of removing.
The mode that covers the sensitization resist plating repeats no more with step S22 here.
Step S27: the sensitization resist plating of plating area carries out the figure transfer exposure second time to being positioned at for the second time.
This step is the step of exposing second time; Figure transfer exposure is for the second time carried out to one deck sensitization resist plating 6 that covers; Its implementation and parameter are selected with reference to step S23, and different is, owing to be the plating of on the basis of first electroplated metal layer, carrying out second electroplated metal layer; Therefore need carry out contraposition when this carries out the figure transfer exposure, the galvanized graphs coincide first time that galvanized figure for the second time can be covered with needs.According to varying in size of first electroplated metal layer and second electroplated metal layer, can be divided into following three kinds of patterns:
Pattern one: plating for the second time need all cover the galvanized part graphics field first time.
Because the modes that all cover are adopted in the part graphics field that need to cover, the zone of the sensitization resist plating 4 that need remove in this zone when electroplating greater than the first time in the zone of the removal sensitization resist plating 7 of the part graphics field that platings for the second time need all cover.
The scope in the zone of the sensitization resist plating 4 that need remove in this zone when electroplated greater than the first time in the zone of the removal sensitization resist plating 7 of the part graphics field that the above-mentioned plating second time need all cover is confirmed according to the aligning accuracy of exposure sources.
Promptly need expose galvanized graphics field for the first time, electroplate for the second time in this graphics field and design than figure is big for the first time, this is because there is the problem of an aligning accuracy in exposure machine.Wherein, the standard that size exceeds is reference settings with the aligning accuracy, generally is higher than more than the aligning accuracy 5um.For example: when the aligning accuracy of exposure machine reached 20um, the monolateral size of removing sensitization resist plating 4 when the size of removal sensitization resist plating 7 was electroplated than the first time when requiring to electroplate for the second time went out more than the 25um greatly to be advisable.
Continue to use the example of top, shown in figure 10, the sensitization resist plating 7 among the figure after the exposure for the second time is needs the galvanized part graphics fields first time that all cover, the sensitization resist plating 4 that its area should the zone when making public be for the first time removed.
Pattern two: plating for the second time need be carried out the part to the galvanized part graphics field first time and cover.
Because the local mode that covers is adopted in the part graphics field that need to cover, the area of the sensitization resist plating 4 that need remove in this zone when the area that need carry out the removal sensitization resist plating of the local part graphics field that covers in platings was for the second time electroplated less than the first time.
Continue to use the example of top, shown in figure 11, the sensitization resist plating 7 among the figure after the exposure for the second time is needs the local galvanized part graphics field first time that covers.The sensitization resist plating 4 that its area should the zone when making public be for the first time removed.
Pattern three: comprise the combination of pattern one and 2 two kinds of situation of pattern.
Need need adopt the processing mode of above-mentioned pattern one and pattern two to handle respectively to electroplating the part graphics field of carrying out local covering for the first time to electroplating the part graphics field and the plating for the second time that all cover for the first time to plating for the second time.
Continue to use the example of top; Shown in figure 12; Sensitization resist plating 7 among the figure after the bag exposure for the second time comprises: should the galvanized electroplated metal layer 5 in zone when electroplated greater than the first time the galvanized subregions first time (being positioned at the zone of a sensitization resist plating 7 on the left side) that needs all cover, its area; And need the local galvanized subregion first time that covers (being positioned at sensitization resist plating 7 zones on the right), should the galvanized electroplated metal layer 5 in zone when its area was electroplated less than the first time.
Step S28: the sensitization resist plating to after the exposure for the second time carries out the figure transfer development treatment second time.
This step is the step of second development, and purpose is removed the sensitization resist plating that cover on the galvanized graphics field second time, obtains covering the second sensitization resist plating layer in the zone outside the second time of the galvanized graphics field.
Continue to use the example of top, this step is that the sensitization resist plating 7 that has made public among the step S27 is carried out the figure transfer development second time, and needs are carried out sensitization resist plating 7 removals of galvanized graphics field for the second time.Be respectively the structural representation that carries out the circuit card behind the second development to Figure 10, Figure 11, three kinds of patterns shown in Figure 12 among the step S27 like Figure 13, Figure 14, Figure 15.Behind second development, the surf zone that the electroplated that comes out after sensitization resist plating 6 stacks after the figure that stays on the circuit card is for develop for the first time sensitization resist plating 3 and second development is handled.
Above-mentioned steps S26, S27, S28 have realized on the circuit board surface of electroplating formation for the first time, this galvanized electroless plating zone covers second sensitization resist plating layer.
Step S29: carry out the second time in the surface area that does not cover the second sensitization resist plating layer and electroplate, obtain second electroplated metal layer.
The needs that expose at second development carry out electroplating the galvanized second time for the second time the conductive layer surface of graphics field and electroplate conductive metal level, obtain second electroplated metal layer 8 through electroplating for the second time.
Continue to use top example, be respectively the structural representation that carries out the circuit card after electroplate the second time to Figure 13, Figure 14, three kinds of patterns shown in Figure 15 among the step S28 like Figure 16, Figure 17, Figure 18.After electroplating for the second time, conductive layer surface is not developed the second sensitization resist plating, 6 coverings (shown in figure 17) of removing by second electroplated metal layer 8 with having made public; Or by second electroplated metal layer 8, make public to not being developed the first sensitization resist plating of removing 3 and having made public and be not developed the second sensitization resist plating of removing 6 and cover (like Figure 16 and shown in Figure 180).
Step S30: take off the second sensitization resist plating layer and the first sensitization resist plating layer.
Take off the not removed sensitization resist plating 3 when developing for the first time that made public and not removed sensitization resist plating 6 during at second development.
Continue to use top example, be respectively the structural representation that moves back the circuit card behind the film to Figure 16, Figure 17, three kinds of patterns shown in Figure 180 among the step S29 like Figure 19, Figure 20, Figure 21.The conductive layer 2 that makes second electroplated metal layer 8, first electroplated metal layer 5 that is not covered by second electroplated metal layer and do not covered by twice electroplated metal layer all comes out.
Step S31: etch away not by the conductive layer of first electroplated metal layer and the covering of second electroplated metal layer.
This step is the conductive layer 2 that is not capped for etching, obtains the circuit card after electroplating surface is handled.
Continue to use top example, be respectively the structural representation that carries out the circuit card after the etching to Figure 19, Figure 20, three kinds of patterns shown in Figure 21 among the step S30 like Figure 22, Figure 23, Figure 24.The conductive layer 2 that has only kept second electroplated metal layer 8, first electroplated metal layer 5 and be capped has been accomplished the selective electroplating treatment scheme on semiconductor product surface.
Wherein, circuit card shown in Figure 22, in the graphics field of the electroplated metal layer second time, second electroplated metal layer is big or small identical with first electroplated metal layer.Circuit card shown in Figure 23, in the graphics field of the electroplated metal layer second time, second electroplated metal layer is less than the size of first electroplated metal layer, and the surface-treated metal level remains in the first time of the galvanized graphics field.Circuit card shown in Figure 24 then is that second electroplated metal layer is less than the size of first electroplated metal layer in the part graphics field of the electroplated metal layer second time; In another part graphics field of the electroplated metal layer second time, second electroplated metal layer is big or small identical with first electroplated metal layer, is the mixing performance of preceding two kinds of situation.
The foregoing description two is the specific descriptions to circuit board surface electroplating processes process; Wherein specifically through covering sensitization resist plating layer and it being developed and the mode of making public forms the anti-plate resist; In fact the description of the embodiment of the invention one, the formation of anti-plate resist can be not limited to this mode, also is not limited to use the sensitization resist plating; Form the anti-plate resist as long as can meet, like employing silk-screen thermo-cured ink or pressing anti-plate glue in the galvanized zone of needs not.When using the sensitization resist plating to realize covering the anti-plate protection; Can be through the mode of figure transfer exposure, figure transfer development; Realization will need the sensitization resist plating of galvanized plating area to remove, and only stay the sensitization resist plating that does not need the electroless plating zone.
Carry out the first time and surface treatment for the second time though only describe among the above embodiment, but, also can carry out more times surface treatment if desired.For the first time with the non-first time (for example: for the second time, for the third time, the 4th time ...) when covering the anti-plate resist in the surface treatment, the mode of the covering anti-plate resist of employing can difference respectively during each time handled.
The embodiment of the invention also provides a kind of circuit card that adopts the above-mentioned circuit board surface electric plating method preparation that provides.
The method of the foregoing circuit plate electroplating surface that the embodiment of the invention provides; Through splash conductive layer, pad pasting, single exposure, once develop, graphic plating, secondary pad pasting, re-expose, second development, a secondary graphic plating, move back the processing of film, etched whole technological process; Realized the electroplating processes in the assignment graph zone of circuit board surface; This mode need not be arranged electroplate lead wire, has saved the making and the distribution of electroplate lead wire, has practiced thrift the required circuit board space that takies of electroplate lead wire; Thereby make circuit card can have more space to connect up, thereby improved the wiring density of circuit card.
In addition, this mode guarantees to realize accurately only in the galvanized graphics field of needs, to electroplate through to not needing galvanized zone to cover, thereby has reduced the usage quantity of noble metal, has practiced thrift the cost of manufacture of circuit board surface electroplating processes.Preferably, the circuit card among above-mentioned each embodiment is extraordinary circuit card, and preferred above-mentioned extraordinary circuit card is a base plate for packaging.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the method for selective electroplating is carried out on the surface of a circuit card, it is characterized in that, comprising:
Surface coverage conductive layer at circuit card;
Electroless plating zone on the surface of said conductive layer covers the anti-plate resist; And do not electroplated by the plating area of anti-plate resist covering, obtain surface-treated electroplated metal layer for the first time;
Carry out the non-surface treatment first time, wherein, on the surface that last once surface treatment forms, at said non-surface-treated electroless plating zone covering first time anti-plate resist; And do not electroplating in the plating area that is covered by the anti-plate resist, obtain said non-first time of surface-treated electroplated metal layer;
Take off the anti-plate resist, and etch away the conductive layer that is not covered by electroplated metal layer.
2. the method for claim 1 is characterized in that, the metal of said conductive layer is inequality with the metal of the electroplated metal layer that last surface treatment forms.
3. the method for claim 1 is characterized in that, the thickness of said conductive layer is 0.2～1.5 μ m, is preferably 0.8-1.2 μ m, more preferably is 1.0 μ m.
4. the method for claim 1 is characterized in that, more than the big 5 μ m of thickness of the thickness of said anti-plate resist than electroplated metal layer, is preferably 5-15 μ m, more preferably is 5-8 μ m.
5. like each described method in the aforementioned claim, it is characterized in that,
It is to cover sensitization anti-plate layer that the electroless plating zone on said surface at said conductive layer covers the anti-plate resist, specifically comprises:
Cover the sensitization resist plating at said conductive layer upper surface;
The said sensitization resist plating of plating area carries out the figure transfer exposure first time to being positioned at for the first time;
The said sensitization resist plating of plating area carries out the figure transfer development treatment first time to being positioned at for the first time after the figure transfer exposure first time; Removing the sensitization resist plating that covers on the plating area the said first time, thereby obtain covering the sensitization anti-plate layer in surface-treated electroless plating zone for the first time;
And/or
Said is to cover sensitization anti-plate layer on the surface that last once surface treatment forms, at said non-surface-treated electroless plating zone covering first time anti-plate resist, specifically comprises:
Surface coverage sensitization resist plating at last once surface treatment electroplated metal layer that forms and the sensitization resist plating layer that covers before;
The said sensitization anti-plate protective material that is positioned at the said non-first time of surface-treated plating area is carried out the figure transfer exposure;
The said sensitization resist plating that is positioned at the said non-first time of surface-treated plating area to after the figure transfer exposure carries out the figure transfer development treatment; Removing the sensitization anti-plate protective material that cover on the surface-treated plating area the said non-first time, thereby obtain covering the sensitization anti-plate layer in the said non-first time of surface-treated electroless plating zone.
6. like each described method in the aforementioned claim, it is characterized in that,
When said non-first time surface treatment, the electroplated metal layer that forms when covering last surface treatment so that the sensitization resist plating is local is in order to form the electroplated metal layer of the local electroplated metal layer that forms when covering last surface treatment;
Or
When said non-first time surface treatment, the electroplated metal layer that forms when covering last surface treatment fully, the electroplated metal layer of the electroplated metal layer that forms when covering last surface treatment fully in order to form with the sensitization resist plating;
Or
When said non-first time surface treatment; The first part of the electroplated metal layer that forms when covering last surface treatment so that the sensitization resist plating is local is in order to the electroplated metal layer of the first part that forms the local electroplated metal layer that forms when covering last surface treatment; The second section of the electroplated metal layer that forms when covering last surface treatment fully with the sensitization resist plating, the electroplated metal layer of the second section of the electroplated metal layer that forms when covering last surface treatment fully in order to form.
7. method as claimed in claim 6 is characterized in that, when said non-first time surface treatment, the regional extent of the sensitization resist plating that the part is covered and/or covers is fully confirmed according to the aligning accuracy of exposure sources.
8. like each described method in the aforementioned claim, it is characterized in that,
Above-mentioned covering anti-plate resist specifically adopts at least a in the following manner: manually pad pasting, pad pasting, vacuum pad pasting, silk screen printing, coating, spraying and roller coating automatically.
9. method as claimed in claim 8 is characterized in that, when the mode that adopts manual pad pasting, automatic pad pasting or vacuum pad pasting covers the anti-plate resist, and the mode that adopts dry film to make; When the mode that adopts silk screen printing, coating, spraying or roller coating covers the anti-plate resist, the mode that adopts wet film to make.
10. circuit card of making through the described method of aforementioned arbitrary claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102540928A CN102373492A (en) | 2010-08-13 | 2010-08-13 | Method for carrying out selective electroplating on surface of circuit board, and circuit board |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010102540928A CN102373492A (en) | 2010-08-13 | 2010-08-13 | Method for carrying out selective electroplating on surface of circuit board, and circuit board |
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| CN102373492A true CN102373492A (en) | 2012-03-14 |
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| CN2010102540928A Pending CN102373492A (en) | 2010-08-13 | 2010-08-13 | Method for carrying out selective electroplating on surface of circuit board, and circuit board |
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Application publication date: 20120314 |