CN102368499B - Tft阵列基板及液晶面板 - Google Patents

Tft阵列基板及液晶面板 Download PDF

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CN102368499B
CN102368499B CN201110331872.2A CN201110331872A CN102368499B CN 102368499 B CN102368499 B CN 102368499B CN 201110331872 A CN201110331872 A CN 201110331872A CN 102368499 B CN102368499 B CN 102368499B
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覃事建
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种TFT阵列基板，其包括多条数据线及多条栅极线，该多条数据线与该多条栅极线相互垂直设置并形成多个像素区域，该像素区域包括像素电极、薄膜晶体管及存储电容，所述像素电极设置在所述像素区域内，所述薄膜晶体管设置在数据线与栅极线的交界重叠处，存储电容设于所述栅极线上。本发明还提供了一种包括上述TFT阵列基板的液晶面板。本发明通过将薄膜晶体管设置于数据线与栅极线的交界重叠处，无须减少栅极线及数据线的布线而有效地提高了液晶显示器的开口率。而且，将存储电容设置在栅极线上，可以进一步提高开口率。

Description

TFT阵列基板及液晶面板
技术领域
本发明涉及液晶显示技术领域，特别涉及一种液晶面板及其TFT阵列基板。
背景技术
TFT(Thin Film Transistor，薄膜晶体管)液晶显示器以其体积小、功耗低、无辐射等特点而受到人们的广泛青睐，从而使其在当前的平板显示器的市场中占据了主导地位。一般TFT液晶显示器包括一TFT阵列基板、一彩色滤光膜阵列基板及一置于TFT阵列基板及彩色滤光膜阵列基板之间的液晶层。
TFT阵列基板是对液晶层进行驱动的电路基板，包括多条栅极线和数据线，相互垂直的多条栅极线和多条数据线形成了多个像素区域，且每个像素区域内设置有薄膜晶体管、像素电极及存储电容等。薄膜晶体管包括一栅电极连接至栅极线，源电极连接至数据线，漏电极连接至像素电极。当栅极线被驱动时，薄膜晶体管处于导通状态，对应的数据线送入灰阶电压信号并将其加载至像素电极，从而使得像素电极产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，因此可以实现不同的图像显示。
上述TFT阵列结构中，开口率问题一直困扰着人们。开口率是像素可透光部分的面积与像素总面积(包括不透光部分的面积)的比值。一个像素元中，不透光的部分主要为薄膜晶体管、栅极线、数据线、存储电容及黑矩阵材料等。为了提高开口率，现有技术中有减少栅极线及数据线的布线，虽然如此可以一定程度地提高开口率，但是相应地也带来了栅极线及数据线电阻增大、RC延迟增大等负面作用。
发明内容
本发明的主要目的为提供一种TFT阵列基板，在不需要减少栅极线及数据线的布线的情况下提高液晶显示器的开口率。
本发明提供了一种TFT阵列基板，其包括多条数据线及多条栅极线，多条数据线与多条栅极线相互垂直设置并形成多个像素区域，所述像素区域包括像素电极、薄膜晶体管及存储电容，所述像素电极设置在所述像素区域内，所述薄膜晶体管设置在所述数据线与所述栅极线的交界重叠处，所述存储电容设于所述栅极线上。
优选地，所述像素区域还包括一用于补偿所述数据线与所述栅极线交叠处产生的寄生电容的补偿电容，所述补偿电容设置于所述栅极线上。
优选地，所述补偿电容与所述存储电容位于所述栅极线上且设于相邻的两薄膜晶体管之间。
优选地，所述薄膜晶体管包括一栅电极、一源电极及一漏电极，所述栅电极连接所述栅极线，所述源电极连接所述数据线，所述漏电极连接所述像素电极，所述源电极与所述漏电极之间形成导电沟道，且所述导电沟道的长边平行于所述数据线方向。
优选地，所述栅极线上设置有薄膜晶体管的部分的宽度比所述栅极线上其他部分的宽度宽。
优选地，所述薄膜晶体管包括一栅电极、一源电极及一漏电极，所述栅电极连接所述栅极线，所述源电极连接所述数据线，所述漏电极连接所述像素电极，所述源电极与漏电极之间形成第一导电沟道及第二导电沟道，且第一导电沟道的长边平行于数据线方向，第二导电沟道的长边平行于栅极线方向，所述第一导电沟道与所述第二导电沟道相互连通且呈一“L”字形。
本发明还提供了一种液晶面板，包括TFT阵列基板，该阵列基板包括多条数据线及多条栅极线，多条数据线与多条栅极线相互垂直设置并形成多个像素区域，所述像素区域包括像素电极、薄膜晶体管及存储电容，所述像素电极设置在所述像素区域内，所述薄膜晶体管设置在所述数据线与所述栅极线的交界重叠处，所述存储电容设于所述栅极线上。
本发明TFT阵列基板通过将薄膜晶体管设置于数据线与栅极线的交界重叠处，无须减少栅极线及数据线的布线而有效地提高了开口率。另外，将存储电容设置在栅极线上，可以进一步提高开口率。
附图说明
图1为本发明TFT阵列基板第一实施例的结构示意图；
图2为图1中薄膜晶体管的放大结构示意图；
图3为本发明TFT阵列基板第二实施例的结构示意图；
图4为本发明TFT阵列基板第三实施例的结构示意图；
图5为图4中薄膜晶体管的放大结构示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
参照图1和图2，图1为本发明TFT阵列基板第一实施例的结构示意图，图2为图1中薄膜晶体管13a的放大结构示意图。该TFT阵列基板为薄膜晶体管液晶显示器的重要部件之一，是对液晶层进行驱动的电路基板。如图1所示，该TFT阵列基板包括多条相互平行设置的数据线(Date Line)及多条相互平行设置的栅极线(Gate Line)，且多条数据线与多条栅极线以绝缘方式相互垂直设置，每相邻两条数据线11a、11b与每相邻两条栅极线12a、12b限定一个像素区域，且每个像素区域内设置有一像素电极14。数据线11a、11b与栅极线12a、12b的交界重叠处分别设置有一薄膜晶体管13a、13b、13c、13d。以数据线11a及栅极线12a的交界重叠处设置的薄膜晶体管13a为例，薄膜晶体管13a对应于像素电极14，作为像素电极14的开关元件，该薄膜晶体管13a包括一栅电极131、一源电极132以及一漏电极133，其中栅电极131连接上述栅极线12a，源电极132连接上述数据线11a，漏电极133连接上述像素电极14。与栅极线12a连接的栅电极131作为薄膜晶体管13a的开关，漏电极133与源电极132之间则形成TFT导电沟道130，且该TFT导电沟道130的长边平行于数据线11a方向。
上述TFT阵列基板的工作原理是：通过扫描驱动器依序输出多个扫描信号至每一条栅极线，以栅极线12a为例，在扫描驱动器输出扫描信号至该栅极线12a时，与该行栅极线12a连接的薄膜晶体13a导通，同时，数据驱动器并行输出的灰阶电压通过数据线11a传输至对应的薄膜晶体管13a的源电极131，然后该灰阶电压经由薄膜晶体管13a的TFT导电沟道130的漏电极133加载至像素电极14，从而使得像素电极14产生相应的电场，液晶层中的液晶分子则在电场的作用下发生取向变化，进而实现不同的图像显示。
上述栅极线12a上还对应薄膜晶体管13a设置存储电容15及补偿电容16。该存储电容15是由像素电极14与栅极线12a部分交叠构成，该补偿电容16用于补偿数据线11a与栅极线12a之间形成的寄生电容，其直接设置于栅极线12a上。当薄膜晶体管13a导通时，存储电容15可以进行充电以储存一定的电压，而在薄膜晶体管13a截止时维持像素电极14上的灰阶电压，以使像素电极14上的灰阶电压保持至下一灰阶电压到来，从而保证了图像显示的连续性。由于在制作TFT阵列基板时，可能由于对位误差而造成TFT产生不同的寄生电容，因此需要补偿电容16对其进行电容补偿，即保证寄生电容与补偿电容16的总和为一个稳定值。因此通过补偿电容16的设置，可以改善薄膜晶体管13a的电特性。另外，上述存储电容15与补偿电容16均位于栅极线12a上，进一步提高了开口率。
本实施例TFT阵列基板通过将薄膜晶体管13a设置于数据线11a与栅极线12a的交界重叠处，则不需要减少栅极线12a及数据线11a的布线，有效地提高了像素电极14的开口率。而且存储电容15与补偿电容16均设置在栅极线12a上，从而进一步提高了开口率。
如图2所示，导电沟道130的与数据线11a平行的一边的长度为宽W，与栅极线12a平行的一边的长度为长L，由于薄膜晶体管13a的充电电流与薄膜晶体管13a的导电沟道130的宽长比W/L成正比，所以依据薄膜晶体管13a的电特性，设置薄膜晶体管13a的宽长比W/L，则栅极线12a上设置有薄膜晶体管13a的部分的宽度h2比栅极线12a上其他部分的宽度h1宽，即h2＞h1。
参见图3，为本发明TFT阵列基板第二实施例的结构示意图。如图3所示，与第一实施例不同的是，本发明TFT阵列基板第二实施例中，补偿电容16在栅极线12a的位置不同。以薄膜晶体管13a对应的补偿电容16为例，第一实施例中，补偿电容16位于两薄膜晶体管13a、13c之间，且位于邻近薄膜晶体管13a的栅极线12a上。而第二实施例中，补偿电容16位于两薄膜晶体管13a、13c之间，且位于邻近薄膜晶体管13c的栅极线12a上。在这里需要说明的是，在不影响寄生电容与补偿电容16的平衡要求的情况下，上述补偿电容16的位置还可以根据具体情况而变化。
参照图4和图5，图4为本发明TFT阵列基板第三实施例的结构示意图，图5为图4中薄膜晶体管13a的放大结构示意图。与上述实施例不同的是，以薄膜晶体管13a为例，该实施例中薄膜晶体管13a在数据线11a与栅极线12a交叠处的位置不同。该TFT阵列基板中薄膜晶体管13中漏电极133与源电极132之间形成第一导电沟道134及第二导电沟道135，且第一导电沟道134的长边平行于数据线11a方向，第二导电沟道135的长边平行于栅极线12a方向，第一导电沟道134与第二导电沟道135相互连通且呈一“L”字形。
如图5所示，薄膜晶体管13a的第一导电沟道134的与数据线11a平行的一边为宽W1，第一导电沟道134的与栅极线12a平行的一边为长L1；薄膜晶体管13a的第二导电沟道135的与数据线11a平行的一边为长L2，第二导电沟道135的与栅极线12a平行的一边为宽W2。所以依据薄膜晶体管13a的电特性而设置薄膜晶体管13a中第一导电沟道134宽长比W1/L1、第二导电沟道135宽长比W2/L2，不用加宽栅极线12a，而是通过增大第二导电沟道135的宽W2、减小第一导电沟道134的长L1即可达到目的。因此，由于无需加宽栅极线12a的高度，从而进一步提高了开口率。
本发明还提供了一种包括TFT阵列基板的液晶面板。如图1至图3所示，该TFT阵列基板包括多条平行设置的数据线(Date Line)及多条相互平行设置的栅极线(Gate Line)，且多条数据线与多条栅极线以绝缘方式相互垂直设置，每相邻两条数据线11a、11b与每相邻两条栅极线12a、12b限定一个像素区域，且每个像素区域内设置有一像素电极14。数据线11a、11b与栅极线12a、12b的交界重叠处分别设置有一薄膜晶体管13a、13b、13c、13d。以数据线11a及栅极线12a的交界重叠处设置的薄膜晶体管13a为例，该薄膜晶体管13a对应于像素电极14，作为像素电极14的开关元件，该薄膜晶体管13a包括一栅电极131、一源电极132以及一漏电极133，其中栅电极131连接一上述栅极线12a，源电极132连接一上述数据线11a，漏电极133连接一上述像素电极14。与栅极线12a连接的栅电极131作为薄膜晶体管13a的开关，漏电极133与源电极132之间则形成TFT导电沟道130，且该TFT导电沟道130的长边平行于数据线11a方向。
上述栅极线12a上还对应薄膜晶体管13a设置存储电容15及补偿电容16。该存储电容15是由像素电极14与栅极线12a部分交叠构成，该补偿电容16用于数据线11a与栅极线12a之间形成的寄生电容，其直接设置于栅极线12a上。当薄膜晶体管13a导通时，存储电容15可以进行充电以储存一定的电压，而在薄膜晶体管13a截止时维持像素电极14上的灰阶电压，以使像素电极14上的灰阶电压保持至下一灰阶电压到来，从而保证了图像显示的连续性。由于在制作TFT阵列基板时，可能由于对位误差而造成TFT产生不同的寄生电容，因此需要补偿电容16对其进行电容补偿，即保证寄生电容与补偿电容16的总和为一个稳定值。因此通过补偿电容16的设置，可以改善薄膜晶体管13a的电特性。另外，上述存储电容15与补偿电容16均位于栅极线12a上，从而进一步提高了开口率。
如图4至图5所示，与上述实施例不同的是，以薄膜晶体管13a为例，该实施例中薄膜晶体管13a在数据线11a与栅极线12a交叠处的位置不同。该TFT阵列基板中薄膜晶体管13a中漏电极133与源电极132形成第一导电沟道134及第二导电沟道135，且第一导电沟道134的长边平行于数据线11a方向，第二导电沟道135的长边平行于栅极线12a方向，第一导电沟道134与第二导电沟道135相互连通且呈一“L”字形。
本实施例TFT阵列基板通过将薄膜晶体管13a设置于数据线11a与栅极线12a的交界重叠处，则不需要减少栅极线12a及数据线11a的布线，有效地提高了像素电极14的开口率。而且将存储电容15与补偿电容16均设置在栅极线12a上，从而进一步提高了开口率。
以上所述仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (6)

1.一种薄膜晶体管TFT阵列基板，其包括多条数据线及多条栅极线，所述多条数据线与所述多条栅极线相互垂直设置并形成多个像素区域，所述像素区域包括像素电极、薄膜晶体管及存储电容，所述像素电极设置在所述像素区域内，其特征在于，所述薄膜晶体管设置在所述数据线与所述栅极线的交界重叠处，所述存储电容设于所述栅极线上，所述存储电容是由所述像素电极与所述栅极线部分交叠构成，所述像素区域还包括一用于补偿所述数据线与所述栅极线交叠处产生的寄生电容的补偿电容，所述补偿电容设置于所述栅极线上。
2.根据权利要求1所述的TFT阵列基板，其特征在于，所述补偿电容与所述存储电容位于所述栅极线上且设于相邻的两薄膜晶体管之间。
3.根据权利要求1至2中任一项所述的TFT阵列基板，其特征在于，所述薄膜晶体管包括一栅电极、一源电极及一漏电极，所述栅电极连接所述栅极线，所述源电极连接所述数据线，所述漏电极连接所述像素电极，所述源电极与所述漏电极之间形成导电沟道，且所述导电沟道的长边平行于所述数据线方向。
4.根据权利要求3所述的TFT阵列基板，其特征在于，所述栅极线上设置有所述薄膜晶体管的部分的宽度比所述栅极线上其他部分的宽度宽。
5.根据权利要求1至2中任一项所述的TFT阵列基板，其特征在于，所述薄膜晶体管包括一栅电极、一源电极及一漏电极，所述栅电极连接所述栅极线，所述源电极连接所述数据线，所述漏电极连接所述像素电极，所述源电极与所述漏电极之间形成第一导电沟道及第二导电沟道，且所述第一导电沟道平行于所述数据线方向，所述第二导电沟道平行于所述栅极线方向，所述第一导电沟道与所述第二导电沟道相互连通且呈一“L”字形。
6.一种液晶面板，其特征在于，包括如权利要求1至5中任一项所述的TFT阵列基板。
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