A kind of Schockley barrier MOS transistor and preparation method thereof
Technical field
The invention belongs to FET logic device and circuit field in the CMOS super large integrated circuit (ULSI), be specifically related to a kind of Schockley barrier MOS transistor in conjunction with ledge structure, annular grid structure and asymmetric source/drain structure and preparation method thereof.
Background technology
As far back as late 1960s, Lepselter and Sze have just proposed Schockley barrier MOS field-effect transistor (Schottky Barrier MOSFET) structure.Utilize metal or silicide to replace traditional doping the source leakage, utilize the direct Tunneling potential barrier of the charge carrier of source end to realize conducting.Along with the size of Metal-oxide-silicon field-effect transistor (MOSFET) is constantly dwindled, short-channel effect is increasing to the influence of device.For traditional MOS field-effect transistor, in order to suppress short-channel effect, the source/drain region that must adopt super shallow junction and abrupt change to mix.And Schottky-barrier source/drain region technology realizes super shallow junction and low dead resistance source-drain area owing to it can utilize simple low temperature technology, thereby becomes a kind of attractive substitute technology to highly doped source-drain area.And in the traditional handicraft the required temperature of activator impurity, realize that the required low temperature process of Schottky barrier source-drain area requires less heat budget, for the use of high K and metal gate material provides possible solution.
Yet traditional Schockley barrier MOS field-effect transistor (SB-MOSFET) also exists certain problem.At first, because the conducting electric current is mainly derived from the tunnelling of source end charge carrier, thereby has limited the size of ON state conducting electric current, less ON state current becomes the one of the main reasons that restriction SB-MOSFET uses; Secondly, there is more serious dipolar effect in SB-MOSFET, and promptly when grid added reverse biased, device also can produce bigger conducting electric current, thereby makes and all present bigger conducting electric current when grid adds certain forward, reverse biased.This is because when grid applies reverse biased (is that example describes with N type substrate), because grid bias is opposite with drain terminal bias voltage direction, bigger electrical potential difference can be fallen on the schottky junction between drain terminal raceway groove-leakage, thereby form very thin drain terminal potential barrier, impel channel electrons to be tunneling to drain terminal, produce the conducting electric current.
Summary of the invention
The present invention is a kind of Schockley barrier MOS field-effect transistor in conjunction with ledge structure, annular grid structure and asymmetric source/drain structure and preparation method thereof.With existing CMOS process compatible and kept under the condition of the various advantages of traditional SB-MOSFET, this structure is utilized ledge structure, annular grid structure to improve ON state current, has been simplified technological process, and utilizes asymmetric source/drain structure to suppress dipolar effect.
Technical scheme of the present invention is as follows:
A kind of Schockley barrier MOS transistor in conjunction with ledge structure, annular grid structure and asymmetric source/drain structure comprises an annular grid electrode, an annular grid dielectric layer, annular grid electrode side wall, the Semiconductor substrate that the projection ledge structure is arranged, a source region, a ring-type drain region.Described Semiconductor substrate has the raised step structure; The metal suicide source district is positioned on the higher plane of raised step, annular metal silicide drain region is around raised step and be positioned on the lower plane, gate dielectric layer and gate electrode are positioned at the corner of raised step and center on the step projection in the form of a ring, the gate electrode side wall is trapped among the gate electrode outside in the form of a ring and certain thickness is arranged, with as the underlap structure of sheltering the formation drain terminal.
Drain terminal underlap structure refers to grid and does not cover raceway groove fully and exposed a part of raceway groove and covering grid oxide layer thereon in the side near drain terminal.
Described source region (5) and drain region (6) can be the compound that any conductivity good metal or metal and backing material form.
The preparation method of MOS transistor of the present invention may further comprise the steps:
(1) on Semiconductor substrate, defines active area by shallow-trench isolation;
(2) photoetching and etch ledge structure;
(3) growth gate dielectric layer;
(4) deposit gate electrode layer then utilizes side wall technology to form annular grating electrode;
(5) deposit side wall layer then utilizes side wall technology to form annular side wall;
(6) float natural oxidizing layer, make source/drain region (being higher plane of step and step) expose backing material than the zone of not sheltered on the low degree by gate electrode and side wall, the sputter layer of metal, form metal and semi-conductive compound through process annealing, then remove unreacted metal, because the masking action of side wall layer can be formed self-aligned asymmetric Schottky source/drain region, i.e. drain terminal underlap structure;
(7) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
Among the above-mentioned preparation method, semiconductor substrate materials in the described step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, silicon (SOI) on the binary of III-V and IV-IV family or ternary semiconductor, the insulator or the germanium (GOI) on the insulator.
Among the above-mentioned preparation method, the gate dielectric layer material in the described step (3) is selected from silicon dioxide, hafnium oxide, hafnium nitride etc.
Among the above-mentioned preparation method, the method for the growth gate dielectric layer in the described step (3) is: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition or physical vapor deposition.
Among the above-mentioned preparation method, the gate electrode layer material in the described step (4) is selected from doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.
Among the above-mentioned preparation method, the side wall layer material in the described step (5) is selected from silicon dioxide, hafnium oxide, hafnium nitride etc.
Among the above-mentioned preparation method, the metal material in the described step (6) is selected from Pt, Er, Co, Ni and other can form the metal of compound with the substrate semiconductor material by annealing.
Advantage of the present invention and good effect:
(1) the present invention has inherited the advantage of traditional schottky barrier MOS transistor (SB-MOSFET), for example super shallow junction, low source-drain area dead resistance etc.
(2) the present invention adopts ledge structure, has eliminated among the conventional planar SB-MOSFET because the uncovered area between the source-raceway groove that brings by the distolateral wall in source, thereby has made that the potential barrier between source-raceway groove is thinner under the ON state, has increased tunnelling probability, has improved the conducting electric current.
(3) the present invention has adopted the annular grid electrode structure, has increased the contact area of source and raceway groove, thereby has increased the tunnelling area of source end, has improved ON state conducting electric current.
(4) the present invention has adopted asymmetric source/drain structure, it is drain terminal underlap structure, slowed down the electric field change at raceway groove-drain junction place, thereby increased the barrier width on raceway groove-drain junction, suppressed SB-MOSFET occurs in drain terminal when grid applies reverse biased tunnelling current, source end tunnelling conducting electric current when simultaneously this can't influence grid and applies forward bias, thus the dipolar effect of SB-MOSFET suppressed.
(5) because the formation of gate electrode is to have utilized side wall technology, and the formation that leak in the source also is to utilize the metallized process of autoregistration, has therefore reduced the photoetching number of times in the whole process flow, has simplified technical process.
Generally speaking, this device architecture has adopted ledge structure in conjunction with annular grid structure and asymmetric source/drain structure, on the basis of the advantage of inheriting tradition SB-MOSFET, has improved ON state conducting electric current, has suppressed dipolar effect, and has simplified technology.
Description of drawings
Fig. 1 (a) be photoetching and etch ledge structure after device along the profile of Fig. 1 (b) dotted line direction, Fig. 1 (b) is the corresponding devices vertical view;
Fig. 2 (a) be device behind growth gate dielectric layer and the deposit gate electrode layer along the profile of Fig. 2 (b) dotted line direction, Fig. 2 (b) is the corresponding devices vertical view;
Fig. 3 (a) utilizes side wall technology to form device after the annular grating electrode along the profile of Fig. 3 (b) dotted line direction, and Fig. 3 (b) is the corresponding devices vertical view;
Fig. 4 (a) be device behind the deposit side wall layer along the profile of Fig. 4 (b) dotted line direction, Fig. 4 (b) is the corresponding devices vertical view;
Fig. 5 (a) be utilize side wall technology to form annular side wall and cross the gate dielectric layer of carving perforated surface, source after device along the profile of Fig. 5 (b) dotted line direction, Fig. 5 (b) is corresponding vertical view;
Fig. 6 (a) is that splash-proofing sputtering metal annealing forms device behind the metal silicide along the profile of Fig. 6 (b) dotted line direction, and Fig. 6 (b) is the corresponding devices vertical view;
Fig. 6 (b) is the final vertical view of this structure devices, and Fig. 6 (a) is the profile of Fig. 6 (b) along the dotted line direction.
1-----------Semiconductor substrate 2-------------gate dielectric layer
3-----------gate electrode layer 4-------------side wall layer
6-------------Schottky drain region, 5-----------Schottky source region
Embodiment
Basic principle of the present invention is as follows: (describing with N type substrate)
When gate electrode and drain terminal apply forward bias SB-MOSFET are opened, the conduction band of channel region descends, thereby make being with of source-channel junction place severely more curved down, reduced source-raceway groove barrier width, when source end metal Fermi level was higher than at the bottom of the conduction band of channel region, source end electronics can tunnelling be crossed potential barrier and is entered in the channel region conduction band, and then has reduced in the drain terminal forward bias under the condition of raceway groove-drain junction place barrier height, to drain terminal, produce electric current by the conduction band heat emission.In this whole process, the barrier width of source end has directly determined the size of conducting electric current, and among traditional planar S B-MOSFET because side wall essential, making has a bit of raceway groove directly not covered (but being sheltered by side wall) by gate electrode near source-channel junction, this a bit of uncovering area can slow down the steepness of conduction band bending, thereby reduced the tunneling barrier width at source-channel junction place, the present invention has then adopted ledge structure, make the source metal end can directly contact trench edges (also promptly elimination) not by directly actuated that section uncovered area of gate electrode, so the tunneling barrier of source end will be thinner under the ON state, tunnelling probability increases, and the conducting electric current also is improved.In addition, when grid adds reverse biased, can make the valence band of raceway groove rise, adding that the forward bias that drain terminal applies makes the metal Fermi level of drain terminal descend, when drain terminal metal Fermi level is lower than the top of valence band of raceway groove, electronics in the raceway groove valence band can tunnelling to drain terminal, produce electric current, and because the electrical potential difference on raceway groove-drain junction is bigger, at this moment potential barrier will be very thin, so tunnelling current will be bigger, can the compare conducting electric current of ON state current size of generation, this is the dipolar effect of SB-MOSFET just.If can increase the width of the potential barrier on raceway groove-drain junction, the conducting electric current in the time of just can suppressing to add reverse biased effectively.The present invention has adopted the underlap structure (description technique scheme place is seen in the structure explanation) of drain terminal, thereby can slow down the steepness that raceway groove changes by near the valence band drain terminal effectively, thereby increase corresponding tunneling barrier width, the conducting electric current when suppressing to add reverse biased.
Be specific embodiments of the invention below:
Embodiment 1:
Adopt following method to prepare MOS transistor of the present invention:
(1) be to adopt shallow-trench isolation fabrication techniques active area isolation layer on the body silicon silicon chip silicon substrate 1 of (100) in the crystal orientation, substrate doping is a N type light dope; Make step cutting pattern then by lithography, etch ledge structure, the high about 500nm of step is shown in Fig. 1 (a), 1 (b);
(2) heat growth gate dielectric layer, deposit gate electrode layer then, gate dielectric layer is SiO
2, thickness is 1-5nm, and gate electrode layer is the highly doped polysilicon layer, and thickness is about 200nm, as Fig. 2 (a), shown in 2 (b);
(3) utilize side wall technology to form annular grating electrode 3, gate electrode thickness is about 200nm, shown in Fig. 3 (a), 3 (b);
(4) deposit side wall layer, side wall layer are Si
3N
4, thickness is about 100nm, as Fig. 4 (a), shown in 4 (b);
(5) utilize side wall technology to form side wall 4, the thickness of side wall is about 100nm, shown in Fig. 5 (a), 5 (b);
(6) float natural oxidizing layer, expose the source-drain area backing material, sputter layer of metal layer Ni, through the low temperature thermal annealing, with the Schottky source/drain region of the self aligned formation metal silicide of silicon as device, because the masking action of side wall layer, source/drain region is asymmetric, be that drain terminal forms the underlap structure, shown in Fig. 6 (a), 6 (b);
(7) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described Schockley barrier MOS field-effect transistor in conjunction with ledge structure, annular grid structure and asymmetric source/drain structure.
Embodiment 2:
As embodiment 1, difference is:
● shoulder height is about 200nm in the step (1);
● gate electrode thickness is about 100nm in step (2), (3);
● side wall thicknesses is about 50nm in step (4), (5);
● splash-proofing sputtering metal is the less metal of hole Schottky barrier in the step (6), as Pt.
Embodiment 3:
As embodiment 1, difference is:
● substrate is doped to P type light dope in the step (1);
● splash-proofing sputtering metal is the less metal of electronics Schottky barrier in the step (6), as rare earth metal Er or Yb.