JPH04186636A - Schottky gate field-effect transistor - Google Patents
Schottky gate field-effect transistorInfo
- Publication number
- JPH04186636A JPH04186636A JP31175090A JP31175090A JPH04186636A JP H04186636 A JPH04186636 A JP H04186636A JP 31175090 A JP31175090 A JP 31175090A JP 31175090 A JP31175090 A JP 31175090A JP H04186636 A JPH04186636 A JP H04186636A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- semi
- gaas
- substrate
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電界効果トランジス久 特にＧａＡｓ基板を用
いたショットキーゲート電界効果トランジスタに関する
ものであａ
従来の技術
従来から電界効果トランジスタを用いた集積回路 特に
ＧａＡｓ基板上に形成されたシヨ・ソトキーゲート電界
効果トランジスタ（以下、ＭＥＳＦＥＴと略称する）を
用いた集積回路で４＆ ゲート電極を挟んでソース電
極とドレイン電極が対向する構造をもったＭＥＳＦＥＴ
が用いられていｆ。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to field effect transistors, particularly Schottky gate field effect transistors using a GaAs substrate. A MESFET is an integrated circuit using a Sotky gate field effect transistor (hereinafter abbreviated as MESFET) formed on a GaAs substrate and has a structure in which a source electrode and a drain electrode face each other with a gate electrode in between.
is used f.
第２図（ａ）、（ｂ）ｌ；Ｌ 従来のＭＥ Ｓ Ｆ
ＥＴの構造を説明するための平面図ならびにその断面図
である。Figure 2 (a), (b) l;L Conventional ME S F
FIG. 2 is a plan view and a cross-sectional view for explaining the structure of ET.
同図において、 １は半絶縁性ＧａＡｓ基板、 ２はＧ
ａＡｓ基板上にレジストをマスクとしてシリコンを選択
イオン注入し 熱処理をおこない導入された不純物を活
性化して形成したｎ形動作凰 ３は前記ｎ形動作層に対
してショットキー接合となる金属を用いたゲート電極
４および５はそれぞれオーミック接合となる金属を用い
たソース電極またはドレイン電極である。In the figure, 1 is a semi-insulating GaAs substrate, 2 is a G
An n-type active layer was formed by selectively implanting silicon ions onto an aAs substrate using a resist as a mask, and performing heat treatment to activate the introduced impurities. 3 used a metal that would form a Schottky junction for the n-type active layer. gate electrode
Reference numerals 4 and 5 are source electrodes or drain electrodes made of metal that form ohmic junctions, respectively.
発明が解決しようとする課題
しかしながらこの様な構造をもつＭＥＳＦＥＴで（戴
ゲート端部ならびにゲート電極引き出し部をｎ形動作層
からはみ出すように形成しなければならず、ゲート電極
がＧａＡｓ半絶縁性基板に接触しているために 隣接す
る素子からの影響を受けＭＥＳＦＥＴの特性が変化する
という問題点（サイドゲート効果）を有しており、集積
回路の高密度化の妨げになっていた
本発明、ほかかる点に鑑ベ ゲート電極がＧａＡｓ半絶
縁性基板に接触せず隣接する素子から影響を受けず高密
度化に適したＭＥＳＦＥＴを提供することを目的とする
。Problems to be Solved by the Invention However, with MESFETs having such a structure,
The gate end and the gate electrode extension must be formed so as to protrude from the n-type active layer, and since the gate electrode is in contact with the GaAs semi-insulating substrate, the characteristics of the MESFET are affected by adjacent elements. In view of this, the present invention has the problem that the gate electrode changes (side gate effect), which has been an obstacle to increasing the density of integrated circuits. It is an object of the present invention to provide a MESFET that is not affected by adjacent elements and is suitable for high density.
課題を解決するための手段
上記の問題点に対し本発明（よ 半絶縁性ＧａＡｓ基板
上にｎ形動外層を形成し その内部に環状のゲート電極
およびソースならびにドレイン電極を形成する構造とす
ることにより、ゲート電極をＧａＡｓ半絶縁性基板上に
接触させることなく Ｍ Ｅ Ｓ Ｆ ＥＴを構成改
良好な素子間分離をおこなうことにより集積回路の高密
度化を可能とするものである。Means for Solving the Problems To solve the above problems, the present invention has a structure in which an n-type outer layer is formed on a semi-insulating GaAs substrate, and annular gate electrodes, source and drain electrodes are formed inside the n-type outer layer. As a result, the MES FET structure can be modified without bringing the gate electrode into contact with the GaAs semi-insulating substrate.
By providing good isolation between elements, it is possible to increase the density of integrated circuits.
作用
このようにして、ゲート電極をＧａＡＳ半絶縁性基板上
に接触させることなくＭＥＳＦＥＴを構成することによ
り、ゲート電極と集積回路を構成する他の素子の電極と
の間に正の電圧がかかった場合にＧａＡｓ半絶縁性基板
からゲート金属への電子の流入がおこることを防ぐ事が
できも その結果 隣接する素子からの影響を大幅に
低減することができも
実施例
第１図（ａ）、 （ｂ）は本発明の一実施例を説明する
ための図で、ＭＥＳＦＥＴの平面図ならびにその断面図
を示す。Effect: By configuring the MESFET in this manner without having the gate electrode contact the GaAS semi-insulating substrate, a positive voltage is applied between the gate electrode and the electrodes of other elements constituting the integrated circuit. In this case, the inflow of electrons from the GaAs semi-insulating substrate to the gate metal can be prevented, and as a result, the influence from adjacent elements can be significantly reduced. (b) is a diagram for explaining one embodiment of the present invention, showing a plan view of a MESFET and a sectional view thereof.
同図において、１１は半絶縁性ＧａＡｓ基板、 ２はＧ
ａＡｓ基板上にレジストをマスクとしてシリコンを選択
イオン注入し 熱処理をおこない導入された不純物を活
性化して形成したｎ形動外販 ３はＴｉＦ’ｔＡｕやＷ
Ｓｉなど、前記ｎ形動外層に対してショットキー接合と
なる金属を用いたゲート電極 ４および５はそれぞれＡ
ｕＧｅ／Ｎｉなどオーミック接合となる金属を用いたソ
ース電極またはドレイン電極である。In the same figure, 11 is a semi-insulating GaAs substrate, 2 is a G
Silicon is selectively ion-implanted onto the aAs substrate using a resist as a mask, and the introduced impurities are activated by heat treatment.
A gate electrode using a metal such as Si that forms a Schottky junction with the n-type outer layer 4 and 5 are A
The source electrode or drain electrode is made of a metal that forms an ohmic contact, such as uGe/Ni.
発明の詳細
な説明したように本発明によればゲート電極をＧａＡｓ
半絶縁性基板上に接触させることなくＭＥＳＦＥＴを構
成することができも その結果 隣接する素子からの影
響を大幅に低減することができるだけでな（、集積回路
を構成する素子間の分離が良好となり、集積回路の高密
度化が可能となム
また 従来からおこなわれている１１Ｂ゛や１６０＋な
どの素子間分離を目的とするイオン注入をおこなう必要
がなく、ＧａＡｓ集積回路の製造工程を簡素化すること
ができもAs described in detail, according to the present invention, the gate electrode is made of GaAs.
Although it is possible to construct MESFETs on semi-insulating substrates without contact, this not only greatly reduces the influence from adjacent elements (but also provides better isolation between the elements that make up the integrated circuit). , it is possible to increase the density of integrated circuits, and there is no need for conventional ion implantation for isolation between elements such as 11B and 160+, which simplifies the manufacturing process of GaAs integrated circuits. Even if you can
第１図（ａ）、 （ｂ）は本発明の一実施例を説明する
ための平面図ならびにその断面図 第２図（ａ）、（ｂ
、）は従来のＭＥＳＦＥＴの構造を説明するための平面
図ならびにその断面図であも
１・・・・半絶縁性ＧａＡｓ基板、 ２・・・・ｎ形動
外販３・・・・ゲート電機 ４・・・・ソース電ｔ ５
・・・・ドレイン電極
代理人の氏名 弁理士 小鍜治 明 ほか２名第１図
μ）
２ ／FIGS. 1(a) and (b) are a plan view and a cross-sectional view for explaining one embodiment of the present invention. FIGS. 2(a) and (b)
, ) are a plan view and a cross-sectional view for explaining the structure of a conventional MESFET. 1... Semi-insulating GaAs substrate, 2... N-type external sales 3... Gate electrical machinery 4 ...Source electric t 5
...Name of drain electrode representative Patent attorney Akira Okaji and two others Figure 1 μ) 2 /
Claims (1)
形動作層と、前記ｎ形動作層の領域内に形成されたショ
ットキー接合となる環状のゲート電極と、前記ｎ形動作
層の領域内で前記ゲート電極の内側に形成されたドレイ
ンまたはソース電極と、前記ｎ形動作層の領域内で前記
ゲート電極の外側に環状に形成されたソースまたはドレ
イン電極とを有するショットキーゲート電界効果トラン
ジスタ。n formed by selective ion implantation on a GaAs substrate.
a ring-shaped gate electrode forming a Schottky junction formed in the region of the n-type active layer, and a drain or source electrode formed inside the gate electrode in the region of the n-type active layer. and a source or drain electrode formed in an annular shape outside the gate electrode within the region of the n-type active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31175090A JPH04186636A (en) | 1990-11-16 | 1990-11-16 | Schottky gate field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31175090A JPH04186636A (en) | 1990-11-16 | 1990-11-16 | Schottky gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04186636A true JPH04186636A (en) | 1992-07-03 |
Family
ID=18021028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31175090A Pending JPH04186636A (en) | 1990-11-16 | 1990-11-16 | Schottky gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04186636A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102324434A (en) * | 2011-10-17 | 2012-01-18 | 北京大学 | Schottky barrier metal oxide semiconductor (MOS) transistor and preparation method thereof |
-
1990
- 1990-11-16 JP JP31175090A patent/JPH04186636A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102324434A (en) * | 2011-10-17 | 2012-01-18 | 北京大学 | Schottky barrier metal oxide semiconductor (MOS) transistor and preparation method thereof |
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