CN102244032B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN102244032B
CN102244032B CN201010250743.6A CN201010250743A CN102244032B CN 102244032 B CN102244032 B CN 102244032B CN 201010250743 A CN201010250743 A CN 201010250743A CN 102244032 B CN102244032 B CN 102244032B
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substrate
dielectric sheet
conductive pattern
hole
printing forme
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CN102244032A (zh
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柯俊成
谢棋君
侯上勇
邱文智
郑心圃
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭示一种半导体装置及其制造方法。该方法包括如下步骤：在一介电板上印制多个导电图案，以形成一预制墨印板，且将预制墨印板接合至一基底的一侧。导电特征部件包括一基底通孔电极自基底的一第一侧延伸至基底的一第二侧，其相对于第一侧。涂覆一导电材料，以将导电图案电性耦接至基底的导电特征部件。本发明的半导体装置的晶片及芯片内不会因形成内连线结构而产生热致应力。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种集成电路结构，尤其涉及一种使用预制墨印板(pre-ink-printed sheet)的集成电路的内连线结构的制造。
背景技术
为了降低集成电路尺寸及降低电路的时间延迟(RC delay)，通常会采用三维集成电路(three-dimensional integrated circuit，3DIC)及芯片堆叠，因而在三维集成电路及芯片堆叠中使用硅通孔电极(through-silicon via，TSV)。在这种情形下，硅通孔电极时常用以将芯片上的集成电路连接至芯片的背侧。另外，硅通孔电极也用于提供较短的接地路径，以透过芯片背侧(其可覆盖一接地金属层)将集成电路接地。
硅通孔电极的连接时常需要在晶片背侧形成重布局线(redistribution line，RDL)来连接硅通孔电极。公知背侧硅通孔电极连接的制造方法使用了诸如化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physicalvapor deposition，PVD)、微影工艺及蚀刻工艺等等。这些方法需要高制造成本。再者，这些方法时常需要对晶片进行高温处理，通常为200℃至400℃。因此，晶片及芯片会产生热致应力(thermally-induced stress)而导致晶片/芯片弯曲变形。再者，也可能在晶片/芯片中发生介电层破损及层离(delamination)。
发明内容
为克服上述现有技术的缺陷，在本发明一实施例中，一种半导体装置的制造方法，包括：提供一基底，其包括一导电特征部件，其中导电特征部件包括一基底通孔电极自基底的一第一侧延伸至基底的一第二侧，其相对于第一侧；提供一介电板；在介电板上印制多个导电图案，以形成一预制墨印板；将预制墨印板接合至基底的第一侧上；以及涂覆一导电材料，以将导电图案电性耦接至基底的导电特征部件。
本发明另一实施例中，一种半导体装置的制造方法，包括：提供一基底，其包括一基底通孔电极自基底的一第一侧延伸至基底的一第二侧，其相对于第一侧；形成一预制墨印板，其包括：一介电板以及位于介电板上方并与其接触的多个导电图案；将预制墨印板接合至基底的第一侧上，其中基底通孔电极的一顶部延伸进入介电板内的一通孔；以及涂覆一导电材料，以填入通孔的剩余空间，且将导电图案的其中之一电性耦接至基底通孔电极。
本发明又一实施例中，一种半导体装置的制造方法，包括：形成一第一预制墨印板，包括：提供一第一介电板以及于第一介电板上方印制一导电浆料以形成一第一导电图案；形成一第二预制墨印板，包括：提供一第二介电板以及于第二介电板上方印制导电浆料以形成一第二导电图案；将第一预制墨印板接合至一基底，基底内包括一基底通孔电极；将第一导电图案电性耦接至基底通孔电极；将第二预制墨印板接合至第一预制墨印上；以及涂覆一额外的导电浆料，以将第一导电图案电性耦接至第二导电图案。
本发明又一实施例中，一种半导体装置，包括：一基底，包括一基底通孔电极自基底的一第一侧延伸至基底的一第二侧，其相对于第一侧；一介电板，位于基底上；以及一重布局线，位于介电板上方，其中重布局线由墨水所构成，且透过介电板内的一通孔而电性耦接至基底通孔电极。
本发明的半导体装置及其制造犯法可省去高成本工艺。此外，晶片及芯片内实质上不会因形成内连线结构而产生热致应力。
附图说明
图1至图9绘示出根据一实施例的具有预加墨印重布局线的内连线结构中间工艺阶段的剖面及平面示意图。
图10绘示出根据另一实施例的中介板剖面示意图，其中位于中介板二相对侧的内连线结构具有预加墨印重布局线。
其中，附图标记说明如下：
2～晶片；
9～金属线；
10～基底；
10a～前表面；
10b～背表面；
11、38、48～介层连接窗；
12～内连线结构；
14～区块；
15～金属凸块；
16～承载板；
17～内层介电层；
18～粘胶；
20～基底通孔电极；
20A～基底通孔电极凸块；
22～隔离层；
24～背侧绝缘层；
30、40、50～预制墨印板；
32、42、52～介电板；
34、44～通孔；
36、46、56～重布局线；
39、49～导电浆料；
52～间隙；
54～填洞导电材料；
60～凸块；
T1、T2、T3～厚度；
W～宽度。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所揭示的特定实施例仅仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
以下提供根据本发明实施例的一种新的内连线结构(其可连接至基底通孔电极(through-substrate via，TSV))及其制造方法，且图示说明了本实施例的中间工艺阶段及实施例的变化，其中不同实施例中相同的部件使用相同的标号。
请参照图1，提供一晶片2，其包括一基底10及位于其中的一集成电路(注：图1未标示“4”，故建议删除该标号)。在不同的实施例中，晶片2可为一装置晶片，其包括有源(active)集成电路装置，例如晶体管。基底10可为半导体基底，例如硅块材(bulk)基底，然其可为其他半导体材料，例如锗化硅、碳化硅、或砷化镓。半导体装置，例如晶体管(以区块14表示之)，可形成于基底10的前表面10a上。内连线结构12形成于基底10上方，其包括金属线9以及介层连接窗(via)11，而金属线9以及介层连接窗11电性耦接至半导体装置14。金属线9以及介层连接窗11可由铜金属或铜合金所构成，且可透过公知的镶嵌工艺来制作。内连线结构12可包括公知的内层介电(inter-layer dielectric，ILD层及金属层间介电(inter-metaldielectric，IMD)层。金属凸块(bump)15形成于晶片2的前侧(图1中向上侧)，其可为焊料凸块或铜凸块，且突出于晶片2的前表面。
在另一实施例中，晶片2为一中介(interposer)晶片，且其内实质上不具有包含有源装置(例如，晶体管及二极管)的集成电路装置。基底10可由半导体材料所构成或由介电材料所构成，例如氧化硅。再者，中介晶片2可具有或不具有无源(passive)装置，例如电容、电阻、电感、变容器(varactor)等等。
基底通孔电极20形成于基底10内。如图1所示，在本实施例中，基底通孔电极20的制作可采用先钻孔(via-first)法，且可在形成内连线结构12之前形成。因此，基底通孔电极20延伸进入内连线结构12内的金属层间介电层，且可延伸进入或不延伸进入用以覆盖半导体装置的内层介电层17。在另一实施例(未绘示出)中，基底通孔电极20的制作可采用后钻孔(via-last)法，且可在形成内连线结构12之后形成。因此，基底通孔电极20贯穿内连线结构12。隔离层22形成于基底通孔电极20的侧壁且使基底通孔电极20与基底10电性绝缘。隔离层22可由一般所使用的介电材料所构成，例如氮化硅、氧化硅(例如，四乙基硅酸盐(tetra-ethyl-ortho-silicate，TEOS)氧化物)等等。
请参照图2，晶片2透过粘胶18而接合至承载板16上，且进行背侧研磨以去除基底10的多余部分。举例来说，对基底10的背侧进行化学机械研磨(chemical mechanical polishing，CMP)而露出基底通孔电极20。形成背侧绝缘层24，以覆盖基底10的背侧。在一实施例中，背侧绝缘层24的制作包括回蚀刻基底10的背表面10b、毯覆性(blanket)形成背侧绝缘层24，以及进行化学机械研磨，以去除位于基底通孔电极20正上方的背侧绝缘层24。因此，基底通孔电极20自背侧绝缘层24露出。在另一实施例中，背侧绝缘层24中通过露出的基底通孔电极20的开口是透过蚀刻而形成的。在形成的结构中，基底通孔电极20包括基底通孔电极凸块20A，其为基底通孔电极20突出晶片2背表面的部分。
请参照图3A及图3B，其为预制墨印板30的平面示意图及剖面示意图，其中图3B为图3A中沿3B-3B线的剖面示意图。预制墨印板30的一制作实施例中，首先提供了一介电板32。介电板32的尺寸与晶片2的尺寸相称。介电板32的厚度T1(如图3B所示)约在1微米(μm)至100微米的范围。然而，可以理解的是说明书中所述的外观尺寸仅为范例说明而可以更动。在一实施例中，介电板32可由聚酰亚胺(polyimide)所构成。然而，也可采用其他介电材料，例如苯环丁烯(bis-benzocyclobutenes，BCB)、酚(phenol)、环氧化物等等。在介电板32所需位置形成通孔34，其自介电板32的一侧延伸至相对侧。虽然所绘示出的通孔34为圆形，然而其也可为其他形状，例如为方形、六边形等等。通孔34的尺寸略大于基底通孔电极凸块20A(图2)的尺寸。
导线(以下也称作重布局线(RDL))36利用墨印法(ink-printing)而印制于介电板32上，其中墨水可为导电浆料，例如银浆料、铜浆料等等。举例来说，可使用纳米银墨印机(nano silver ink printer)来进行墨印。一些重布局线36延伸至通孔34的边缘。在一实施例中，重布局线36的宽度W大于10微米，甚至大于14微米，而重布局线36的厚度T2小于2微米。也可采用不同的厚度及宽度，取决于墨印机的性能。若需要较厚的重布局线36，可进行重复印刷，而每次的印刷可增加重布局线36的厚度T2。
除了重布局线36之外，也可形成介层连接窗38。在本文中，重布局线及介层连接窗也称作导电图案。在一实施例中，介层连接窗38也可透过墨印而形成。请参照图3B，介层连接窗38的制作包括在重布局线36上进行导电浆料的重复印刷，直至介层连接窗38的厚度T3达到所需值。举例来说，大于1微米。在另一实施例中，并无形成介层连接窗38。重布局线36及介层连接窗38的制作可在同一印刷步骤中进行。
请参照图4，在形成预制墨印板30之后，预制墨印板30层压接合于晶片2的背侧。介电板32可透过薄粘胶层(未绘示出)而层压接合于晶片2的背侧，或透过加热晶片2而使介电板32(例如，聚酰亚胺板)贴附于晶片2。进行对准，使基底通孔电极凸块20A延伸进入通孔34。接着，请参照图5，在通孔34内填入导电浆料39，其也可为银浆料、铜浆料等等，以将基底通孔电极20电性耦接至重布局线36。
图6至图8绘示出预制墨印板40的制作与层压接合。请参照图6，举例来说，利用实质上相同于制作预制墨印板30的方法来预先形成预制墨印板40。预制墨印板40包括介电板42，其上具有利用墨印而形成的重布局线46及介层连接窗48。预制墨印板40中通孔44、重布局线46及介层连接窗48的图案可分别不同于通孔34、重布局线36及介层连接窗38。再者，通孔44的位置对应于介层连接窗38的位置，且通孔44的尺寸略大于介层连接窗38的尺寸，使介层连接窗38可安装于通孔44内。
请参照图7，预制墨印板40放置于预制墨印板30上，并于其对准与层压接合。介层连接窗38延伸进入通孔44。接着，请参照图8，将导电浆料49填入通孔44剩余的空间，且将介层连接窗38电性耦接至重布局线46。在预制墨印板30内未形成介层连接窗38的实施例中，导电浆料49填入整个通孔44内，以将重布局线36电性耦接至重布局线46。
在图7中，间隙52存在于预制墨印板30与预制墨印板40之间。请参照图8，间隙52可填入填洞介电材料54，其可为环氧化物。在另一实施例中，填洞介电材料54可在形成图5的结构之后且在预制墨印板40层压接合于预制墨印板30之前，形成于预制墨印板30上。
在接合预制墨印板40之后，可进行额外的预制墨印板接合，以形成多层重布局线。请参照图9，预先形成预制墨印板50，其包括额外的重布局线56。接着接合至预制墨印板40上。可接着形成凸块60。凸块60可为焊料凸块、铜凸块(其可涂覆镍层、金层等等)。
图1至图8绘示出用于具有基底通孔电极的装置晶片的背侧内连线结构。在其他实施例中，本文所教示可轻易地实施于中介晶片一侧的内连线制作或是中介晶片两侧的内连线制作，其中中介晶元内不具有有源装置，例如晶体管。图10绘示出一实施例的剖面示意图。可以观察到其利用预制墨印板而在中介晶片2的二侧形成内连线结构。
在本实施例中，利用预制墨印板形成内连线结构及各自的重布局线。因此，可省去高成本工艺，诸如诸如化学气相沉积(CVD)、物理气相沉积(PVD)、微影工艺及蚀刻工艺等等。再者，上述实施例所使用的工艺实质上不具有高温工艺，因而晶片及芯片内实质上不会因形成内连线结构而产生热致应力。
虽然本发明已以优选实施例揭示如上，然而其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作更动、替代与润饰。再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何本领域技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此，本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。另外，每一申请专利范围构成个别的实施例，且本发明的保护范围也包括各个权利要求及实施例的组合。

Claims (8)

1.一种半导体装置的制造方法，包括：
提供一基底，其包括一导电特征部件，其中该导电特征部件包括一基底通孔电极自该基底的一第一侧延伸至该基底的一第二侧，其中该第二侧相对于该第一侧；
提供一第一介电板；
在该第一介电板内形成一通孔；
在该第一介电板上印制多个第一导电图案，以形成一第一预制墨印板；
将该第一预制墨印板接合至该基底的该第一侧上，使该导电特征部件延伸进入该通孔内；以及
涂覆一导电材料，使该导电材料填入该通孔内，以将所述多个第一导电图案电性耦接至该基底的该导电特征部件。
2.如权利要求1所述的半导体装置的制造方法，还包括：
提供一第二介电板；
在该第二介电板上印制多个第二导电图案，以形成一第二预制墨印板；
将该第二预制墨印板接合至该第一预制墨印板上；以及
涂覆一额外的导电材料，以将所述多个第二导电图案电性耦接至所述多个第一导电图案。
3.如权利要求1所述的半导体装置的制造方法，还包括：
提供一第二介电板；
在该第二介电板上印制多个第二导电图案，以形成一第二预制墨印板；
将该第二预制墨印板接合至该基底中相对于该第一侧的该第二侧上；以及
涂覆一额外的导电材料，以将所述多个第二导电图案电性耦接至该基底的该导电特征部件。
4.如权利要求1所述的半导体装置的制造方法，其中该印制方法包括利用导电浆料作为墨水的墨印法。
5.如权利要求1所述的半导体装置的制造方法，其中印制所述多个第一导电图案的步骤包括：
在该介电板的局部上进行印制，以形成多个重布局线；以及
在所述多个重布局线的局部进行印制，以在其正上方形成介层连接窗而与所述多个重布局线的局部接触。
6.一种半导体装置的制造方法，包括：
形成一第一预制墨印板，包括：
提供一第一介电板；
在该第一介电板内形成一第一通孔；以及
于该第一介电板上方印制一第一导电浆料以形成一第一导电图案；形成一第二预制墨印板，包括：
提供一第二介电板；以及
于该第二介电板上方印制该第一导电浆料以形成一第二导电图案；
将该第一预制墨印板接合至一基底，该基底内包括一基底通孔电极，该基底通孔电极延伸进入该第一通孔内；
将一第二导电浆料填入该第一通孔内，使该第一导电图案电性耦接至该基底通孔电极；
将该第二预制墨印板接合至该第一预制墨印上；以及
涂覆一额外的导电浆料，以将该第一导电图案电性耦接至该第二导电图案。
7.如权利要求6所述的半导体装置的制造方法，其中导电浆料包括银浆料，其中该第二介电板包括一第二通孔，且其中该额外的导电浆料填入该第二通孔，以将该第一导电图案电性耦接至该第二导电图案，其中第一导电图案还包括一介层连接窗，且其中在将该第二预制墨印板接合至该第一预制墨印上之后，该介层连接窗延伸进入该第二通孔。
8.一种半导体装置，包括：
一基底，包括一基底通孔电极自该基底的一第一侧延伸至该基底的一第二侧，其中该第二侧相对于该第一侧；
一介电板，位于该基底上，包括一通孔，该基底通孔电极的一部分延伸进入该通孔；
一导电浆料，填入该通孔的一剩余部分；以及
一重布局线，位于该介电板上方，其中该重布局线由墨水构成，且透过填入该通孔的该导电浆料而电性耦接至该基底通孔电极。
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JP5902102B2 (ja) * 2010-02-22 2016-04-13 インターポーザーズ ゲーエムベーハー 半導体モジュールを製造するための方法およびシステム
GB2518363A (en) * 2013-09-18 2015-03-25 Novalia Ltd Circuit board assembly
DE102014213978A1 (de) 2014-07-17 2016-01-21 Belectric Opv Gmbh Verfahren zur Herstellung eines organischen Halbleiterbauteils und organisches Halbleiterbauteil
CN106206409B (zh) 2015-05-08 2019-05-07 华邦电子股份有限公司 堆叠电子装置及其制造方法
US9595510B1 (en) * 2015-10-13 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method for chip package
CN107172808A (zh) * 2016-03-08 2017-09-15 讯芯电子科技（中山）有限公司 双面直接镀铜陶瓷电路板及其制造方法
US9799617B1 (en) 2016-07-27 2017-10-24 Nxp Usa, Inc. Methods for repackaging copper wire-bonded microelectronic die
US10763230B2 (en) * 2018-12-21 2020-09-01 Texas Instruments Incorporated Integrated circuit backside metallization
US11309254B2 (en) * 2020-02-18 2022-04-19 Nanya Technology Corporation Semiconductor device having through silicon vias and method of manufacturing the same
US11950378B2 (en) * 2021-08-13 2024-04-02 Harbor Electronics, Inc. Via bond attachment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117069A (en) * 1988-03-28 1992-05-26 Prime Computer, Inc. Circuit board fabrication
US5497545A (en) * 1992-03-19 1996-03-12 Hitachi, Ltd. Method of making electrical connections in the manufacture of wiring sheet assemblies
US6384344B1 (en) * 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts

Family Cites Families (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727633A (en) * 1985-08-08 1988-03-01 Tektronix, Inc. Method of securing metallic members together
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5227588A (en) * 1991-03-25 1993-07-13 Hughes Aircraft Company Interconnection of opposite sides of a circuit board
CN1044762C (zh) * 1993-09-22 1999-08-18 松下电器产业株式会社 印刷电路板及其制造方法
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6353540B1 (en) * 1995-01-10 2002-03-05 Hitachi, Ltd. Low-EMI electronic apparatus, low-EMI circuit board, and method of manufacturing the low-EMI circuit board.
KR0155877B1 (ko) * 1995-09-12 1998-12-15 이대원 다층 회로기판 및 그 제조방법
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
WO1998056220A1 (fr) * 1997-06-06 1998-12-10 Ibiden Co., Ltd. Plaquette de circuit simple face et procede de fabrication de ladite plaquette
US6139777A (en) * 1998-05-08 2000-10-31 Matsushita Electric Industrial Co., Ltd. Conductive paste for filling via-hole, double-sided and multilayer printed circuit boards using the same, and method for producing the same
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
WO2001005994A2 (en) 1999-07-21 2001-01-25 Immunoporation Ltd. Method for introducing a substance into a cell
JP4405024B2 (ja) * 2000-01-18 2010-01-27 株式会社ルネサステクノロジ 半導体装置
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
JP2002190521A (ja) * 2000-10-12 2002-07-05 Oki Electric Ind Co Ltd 半導体装置の製造方法
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6831236B2 (en) * 2001-03-23 2004-12-14 Fujikura Ltd. Multilayer wiring board assembly, multilayer wiring board assembly component and method of manufacture thereof
CN1383197A (zh) * 2001-04-25 2002-12-04 松下电器产业株式会社 半导体装置的制造方法及半导体装置
US6885260B2 (en) * 2001-05-11 2005-04-26 Ube Industries, Ltd. Filter using film bulk acoustic resonator and transmission/reception switch
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
JP4070470B2 (ja) * 2002-01-24 2008-04-02 新光電気工業株式会社 半導体装置用多層回路基板及びその製造方法並びに半導体装置
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
JP4191678B2 (ja) * 2002-05-31 2008-12-03 タツタ電線株式会社 導電性ペースト、これを用いた多層基板及びその製造方法
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
JP3887337B2 (ja) * 2003-03-25 2007-02-28 株式会社東芝 配線部材およびその製造方法
JP4203435B2 (ja) * 2003-05-16 2009-01-07 日本特殊陶業株式会社 多層樹脂配線基板
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005159074A (ja) 2003-11-27 2005-06-16 Matsushita Electric Works Ltd 内層側に凸出部のあるビアホール接続用の電極
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7786567B2 (en) * 2004-11-10 2010-08-31 Chung-Cheng Wang Substrate for electrical device and methods for making the same
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US20070138644A1 (en) * 2005-12-15 2007-06-21 Tessera, Inc. Structure and method of making capped chip having discrete article assembled into vertical interconnect
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
JP5018226B2 (ja) 2006-06-30 2012-09-05 旭硝子株式会社 導電膜形成用インク
KR100857165B1 (ko) * 2007-04-13 2008-09-05 삼성전기주식회사 회로기판 제조방법
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US20080303154A1 (en) 2007-06-11 2008-12-11 Hon-Lin Huang Through-silicon via interconnection formed with a cap layer
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
CN101911847B (zh) * 2007-12-25 2012-07-18 株式会社村田制作所 多层配线基板的制造方法
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117069A (en) * 1988-03-28 1992-05-26 Prime Computer, Inc. Circuit board fabrication
US5497545A (en) * 1992-03-19 1996-03-12 Hitachi, Ltd. Method of making electrical connections in the manufacture of wiring sheet assemblies
US6384344B1 (en) * 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts

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