CN102237296A - Through hole etching method - Google Patents
Through hole etching method Download PDFInfo
- Publication number
- CN102237296A CN102237296A CN2010101642638A CN201010164263A CN102237296A CN 102237296 A CN102237296 A CN 102237296A CN 2010101642638 A CN2010101642638 A CN 2010101642638A CN 201010164263 A CN201010164263 A CN 201010164263A CN 102237296 A CN102237296 A CN 102237296A
- Authority
- CN
- China
- Prior art keywords
- hole
- dielectric layer
- forming
- etching
- etching method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a through hole etching method. The method comprises the following steps: providing a semiconductor substrate, wherein a metal interconnect, a barrier layer and a dielectric layer are formed on the semiconductor substrate in sequence; forming a light resistant layer with a though hole pattern on the dielectric layer; with the light resistant layer with the though hole pattern as a mask, etching a part of the dielectric layer to form an opening; removing the light resistant layer with the though hole pattern by utilizing an oxygen plasma ashing process; continuously etching the remaining dielectric layer in the opening and the barrier layer until the metal interconnect is exposed so as to form a through hole. According to the invention, when the light resistant layer with the through hole pattern is used as the mask for etching, only a part of the dielectric layer is etched while the remaining dielectric layer and the whole entire barrier layer are reserved for preventing copper from contacting oxygen to generate oxidizing reaction and preventing the formation of pinholes on the surface of the metal interconnect, thus the reliability of a semiconductor can be improved.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of etching method for forming through hole.
Background technology
Along with integrated circuit develops to the deep-submicron size, the dense degree of semiconductor device and the complexity of technology constantly increase, and the strictness of technical process is controlled become even more important.Wherein, through hole is as the passage that is connected between the active area of multiple layer metal interconnection line and semiconductor device and the external circuitry, have important function in semiconductor device structure is formed, the improvement of via etch process always is subjected to those skilled in the art's great attention.
Detailed, please refer to Figure 1A to Fig. 1 F, it is the generalized section of each step corresponding construction of existing etching method for forming through hole.
With reference to Figure 1A, the semiconductor-based end 100, at first be provided, be formed with metal interconnecting wires 110 at described the semiconductor-based end 100 and be positioned at barrier layer 120 and dielectric layer 130 on the described metal interconnecting wires 110 successively.
Along with the characteristic size of semiconductor device is further dwindled, the RC of interconnection line postpones to become the principal contradiction that influences circuit speed gradually, for improving this point, begins to adopt the process of being made metal interconnected line structure by metallic copper.Because copper interconnecting line can reduce interconnected impedance, reduce power consumption and cost, improve integrated level, device density and the clock frequency of chip, therefore, generally adopt copper interconnecting line at present as metal interconnecting wires.
Wherein, the material on barrier layer 120 can be a silicon nitride, and the material of dielectric layer 130 can be a silica.The thickness on barrier layer 120 can for
The thickness of dielectric layer 130 can for
With reference to Figure 1B, then on described dielectric layer 130, form photoresist layer 140 with via hole image, the thickness of described photoresist layer 140 with via hole image can for
With reference to figure 1C, be mask with described photoresist layer 140 with via hole image, described dielectric layer 130 of etching and part barrier layer 120 are to form opening 121.In this step, the thickness on the remaining barrier layer 120 of opening 121 lower zones only is
With reference to figure 1D, can utilize the oxygen plasma cineration technics to remove described photoresist layer 140 with via hole image, general, the temperature that the oxygen plasma ashing is adopted is generally 275 ℃.Yet, find that in actual production because the thickness on described remaining barrier layer 120 is less, and the diffusivity of copper is stronger, and oxidation reaction very easily takes place in copper in the oxygen atmosphere, and then very easily generates the oxide 111 of copper.
With reference to figure 1E, the described semiconductor-based end 100 of wet-cleaned, described wet clean process can be removed residual photoresistor, and the etching gas and for example various organic polymers of other residue that may exist (polymer) of dielectric layer 130 and remaining barrier layer 120 remained on surface after the removal etching, the chemical reagent that described cleaning adopted can comprise sulfuric acid and hydrogen peroxide.
Simultaneously, although copper is difficult for the chemical reagent reaction adopted with wet-cleaned, the oxide 111 of copper but can react with chemical reagent such as sulfuric acid, therefore in this step, the oxide 111 of copper also can be cleaned, and then forms depression 112 on metal interconnecting wires 110 surfaces.
Continue the remaining barrier layer 120 of the described opening of dry etching 121 belows, to form the through hole 122 shown in Fig. 1 F.Yet when forming through hole 122, the surface on barrier layer 120 has also formed pin hole 113, and described pin hole 113 can influence the electric property of semiconductor device, when serious, even causes component failure.
Summary of the invention
The invention provides a kind of etching method for forming through hole, after forming through hole, wipe the problem that produces pin hole, mentioned the reliability of semiconductor device to solve the metal interconnecting wires surface.
For solving the problems of the technologies described above, the invention provides a kind of etching method for forming through hole, comprising: the semiconductor-based end is provided, is formed with metal interconnecting wires, barrier layer and dielectric layer successively at described the semiconductor-based end; On described dielectric layer, form photoresist layer with via hole image; With described photoresist layer with via hole image is mask, and the described dielectric layer of etched portions is to form opening; Utilize the oxygen plasma cineration technics to remove described photoresist layer with via hole image; Continue remaining dielectric layer and described barrier layer in the described opening of etching, until exposing described metal interconnecting wires, to form through hole.
Optionally, described metal interconnecting wires is a copper interconnecting line.
Optionally, utilize the oxygen plasma cineration technics to remove after the described photoresist layer with via hole image, also comprise: the step of being carried out hydrogen treat technology the described semiconductor-based end.
Optionally, the temperature of described hydrogen treat technology is 10～30 ℃.
Optionally, the temperature of described oxygen plasma cineration technics is 10～30 ℃.
Optionally, after described semiconductor-based end execution hydrogen treat technology, also comprise: the step of cleaning the described semiconductor-based end.
Optionally, clean the chemical reagent that adopts at the described semiconductor-based end and comprise sulfuric acid and hydrogen peroxide.
Optionally, the material on described barrier layer is a silicon nitride, and the material of described dielectric layer is a silica.
Optionally, the etching gas that adopts during the described dielectric layer of etched portions comprises carbon tetrafluoride, fluoroform and argon gas.
Optionally, the etching gas that adopts when remaining dielectric layer and described barrier layer in the described through hole area of etching comprises carbon tetrafluoride and nitrogen.
Compared with prior art, etching method for forming through hole provided by the invention has the following advantages:
1, this lithographic method is being that mask is when carrying out etching with the photoresist layer with via hole image, only etch away a part of dielectric layer and keep the dielectric layer of another part and whole barrier layers, oxidation reaction takes place to stop that copper contacts with oxygen, and then avoid generating the oxide of copper, prevent to form pin hole, improved the reliability of semiconductor device on the metal interconnecting wires surface.
2, utilizing after the oxygen plasma cineration technics removes described photoresist layer with via hole image, this lithographic method also comprises the step of being carried out hydrogen treat technology the described semiconductor-based end, in case described metal interconnecting wires surface has formed the oxide of copper, described hydrogen treat technology also can be reduced to copper with the oxide of copper, further guarantees can not form pin hole on affiliated metal interconnecting wires surface.
Description of drawings
Figure 1A～1F is the generalized section of each step corresponding construction of existing etching method for forming through hole;
Fig. 2 is the flow chart of the etching method for forming through hole that the embodiment of the invention provided;
Fig. 3 A～3E is the generalized section of each step corresponding construction of the etching method for forming through hole that the embodiment of the invention provided.
Embodiment
Core concept of the present invention is, a kind of etching method for forming through hole is provided, this lithographic method is being that mask is when carrying out etching with the photoresist layer with via hole image, only etch away the part dielectric layer and keep a part of dielectric layer and whole barrier layer, oxidation reaction takes place to stop that copper contacts with oxygen, and then avoid generating the oxide of copper, and prevent to form pin hole on the metal interconnecting wires surface, improved the yield of product.
Please refer to Fig. 2, it is the flow chart of the etching method for forming through hole that the embodiment of the invention provided, and in conjunction with this figure, the method comprising the steps of:
Step S20 provides the semiconductor-based end, is formed with metal interconnecting wires, barrier layer and dielectric layer successively at described the semiconductor-based end;
Step S21 forms the photoresist layer with via hole image on described dielectric layer;
Step S22 is a mask with described photoresist layer with via hole image, and the described dielectric layer of etched portions is to form opening;
Step S23 utilizes the oxygen plasma cineration technics to remove described photoresist layer with via hole image;
Step S24 continues remaining dielectric layer and described barrier layer in the described opening of etching, until exposing described metal interconnecting wires, to form through hole.
The etching method for forming through hole that the embodiment of the invention provided is being that mask is when carrying out etching with the photoresist layer with via hole image, only etch away a part of dielectric layer and keep the dielectric layer of another part and whole barrier layers, can copper diffusion barrier come out in thicker dielectric layer and barrier layer, avoid copper to contact oxidation reaction takes place with oxygen, prevent to generate the oxide of copper, and then prevent that the metal interconnecting wires surface forms pin hole when forming through hole, improved the reliability of semiconductor device.
Below in conjunction with generalized section etching method for forming through hole of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
With reference to figure 3A, the semiconductor-based end 300, at first be provided, be formed with metal interconnecting wires 310 on this semiconductor-based end 300 and be positioned at barrier layer 320 and dielectric layer 330 on the described metal interconnecting wires 310 successively.
Preferably, described metal interconnecting wires is a copper interconnecting line.Compare with traditional aluminum interconnecting, the advantage of copper interconnecting line is that its resistivity is lower, and conductivity is better, by its connecting lead wire of making can keep on an equal basis in addition more do forr a short time under the situation of heavy current bearing capacity, more intensive.In addition, copper interconnecting line also has bigger advantage than aluminum interconnecting at aspects such as electromigration, RC delay, reliability and life-spans.
In a specific embodiment of the present invention, only show the layer of metal interconnecting construction, but it is apparent, etching method for forming through hole provided by the present invention goes for the metal interconnecting wires of any one deck, especially in practice, multilayer interconnect structure obtains application more and more widely, i.e. metal interconnecting wires shown in the present invention does not limit is that individual layer still is the metal interconnected line structure of multilayer.
In addition, the concrete semiconductor device structure (for example, concrete capacitor or transistor arrangement) under the metal interconnecting wires is not shown among Fig. 3 A, the present invention does not relate to the improvement of this part, and therefore, the embodiment of the invention repeats no more this.
Wherein, but barrier layer 320 copper diffusion barrier, and can improve the dielectric layer of follow-up formation and the adhesiveness on metal interconnecting wires 310 surfaces.The material on described barrier layer 320 can be a silicon nitride.Certainly, the material on described barrier layer 320 can also be silicon oxynitride, carborundum or silicon oxide carbide etc.The deposition process on described barrier layer can adopt traditional chemical vapour deposition (CVD) mode to form.Wherein, the thickness on described barrier layer 320 can for
With reference to figure 3B, then on described dielectric layer 330, apply photoresistance, and utilize existing photoetching technique to form photoresist layer 340 with via hole image, described via hole image is in order to the definition through hole.Wherein, the thickness of photoresist layer 340 can for
With reference to figure 3C, next, be mask with described photoresist layer 340 with via hole image, etched portions dielectric layer 330 is to form opening 321.
Preferable, the thickness of the remaining dielectric layer 330 in opening 321 belows can for
Described remaining dielectric layer 330 can prevent that copper from contacting the generation oxidation reaction with oxygen, and then avoid the appearance of pin hole with the barrier layer of barrier layer 320 as copper.
In a specific embodiment of the present invention, what adopt during the described dielectric layer 330 of etched portions is dry etching, and etching gas can comprise carbon tetrafluoride, fluoroform and argon gas.Utilize carbon tetrafluoride, fluoroform and argon gas mist to come etching dielectric layer 330, higher selection ratio and etching homogeneity can be provided, make that the dielectric layer 330 of a part can very fast being removed, and keep another part dielectric layer 330 and whole barrier layers 320.
Certainly, the present invention does not limit concrete etching temperature and etching gas flow, and those skilled in the art can obtain empirical value by test.
With reference to figure 3D, can utilize the oxygen plasma cineration technics to remove photoresist layer 340 with via hole image.
Preferable, the temperature of described oxygen plasma cineration technics is 10～30 ℃.Described lower temperature can advance to reduce the activity of copper atom, avoids the oxygen generation oxidation reaction that is adopted in copper atom and the oxygen plasma cineration technics.
In another specific embodiment of the present invention, utilize the oxygen plasma cineration technics to remove after the described photoresist layer 340 with via hole image, can also comprise the step of being carried out the hydrogen treat technologies the described semiconductor-based end 300.In case described metal interconnecting wires 310 surfaces have formed the oxide of copper, described hydrogen treat technology also can be reduced to copper with the oxide of copper, further guarantees can not form pin hole on affiliated metal interconnecting wires 310 surfaces.The temperature of described hydrogen treat technology is 10～30 ℃.Described hydrogen treat technology can utilize same reaction chamber to finish with described oxygen plasma cineration technics.
In another specific embodiment of the present invention, after the step to described semiconductor-based end execution hydrogen treat technology, also can comprise the step of cleaning the described semiconductor-based end 300.Described wet clean process can be removed residual photoresistor, and the etching gas and for example various organic polymers of other residue that may exist of dielectric layer 330 remained on surface after the removal etching, the chemical reagent that described cleaning adopted can comprise sulfuric acid and hydrogen peroxide.Certainly, the cleaning agent that described cleaning adopted can also be a DSP solution, and described DSP solution is meant the mixed solution that contains sulfuric acid, hydrogen peroxide and hydrofluoric acid.
With reference to figure 3E, last, utilize dielectric layer 330 as the hard mask of etching, continue the remaining dielectric layer 330 in the described opening 321 of etching, and continue downward etching barrier layer 320, until the metal interconnecting wires 310 that exposes lower floor, to form through hole 321.
In a specific embodiment of the present invention, what adopt when described opening 321 interior remaining dielectric layers 330 of etching and described barrier layer 320 is dry etching, and etching gas can comprise carbon tetrafluoride and nitrogen.Certainly, the present invention does not limit concrete etching temperature and etching gas flow, and those skilled in the art can obtain empirical value by test.
In sum, the invention provides a kind of etching method for forming through hole, this method comprises: the semiconductor-based end is provided, is formed with metal interconnecting wires at described the semiconductor-based end and is positioned at barrier layer and dielectric layer on the described metal interconnecting wires successively; On described dielectric layer, form photoresist layer with via hole image; With described photoresist layer with via hole image is mask, and the described dielectric layer of etched portions is to form opening; Utilize the oxygen plasma cineration technics to remove described photoresist layer with via hole image; Continue remaining dielectric layer and described barrier layer in the described opening of etching, to form through hole.The present invention is being that mask is when carrying out etching with the photoresist layer with via hole image, only etch away the part dielectric layer and keep a part of dielectric layer and whole barrier layer, oxidation reaction takes place to stop that copper contacts with oxygen, and then avoid generating the oxide of copper, prevent to form pin hole, improved the reliability of semiconductor device on the metal interconnecting wires surface.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (11)
1. etching method for forming through hole comprises:
The semiconductor-based end, be provided, be formed with metal interconnecting wires, barrier layer and dielectric layer successively at described the semiconductor-based end;
On described dielectric layer, form photoresist layer with via hole image;
With described photoresist layer with via hole image is mask, and the described dielectric layer of etched portions is to form opening;
Utilize the oxygen plasma cineration technics to remove described photoresist layer with via hole image;
Continue remaining dielectric layer and described barrier layer in the described opening of etching, until exposing described metal interconnecting wires, to form through hole.
2. etching method for forming through hole as claimed in claim 1 is characterized in that described metal interconnecting wires is a copper interconnecting line.
3. etching method for forming through hole as claimed in claim 1 or 2 is characterized in that, utilizes the oxygen plasma cineration technics to remove after the described photoresist layer with via hole image, also comprises: the step of being carried out hydrogen treat technology the described semiconductor-based end.
4. etching method for forming through hole as claimed in claim 3 is characterized in that, the temperature of described hydrogen treat technology is 10～30 ℃.
5. etching method for forming through hole as claimed in claim 4 is characterized in that, the temperature of described oxygen plasma cineration technics is 10～30 ℃.
6. etching method for forming through hole as claimed in claim 5 is characterized in that, after described semiconductor-based end execution hydrogen treat technology, also comprises: the step of cleaning the described semiconductor-based end.
7. etching method for forming through hole as claimed in claim 6 is characterized in that, cleans the chemical reagent that adopts at the described semiconductor-based end and comprises sulfuric acid and hydrogen peroxide.
8. as any described etching method for forming through hole in the claim 1 to 7, it is characterized in that the material on described barrier layer is a silicon nitride.
9. etching method for forming through hole as claimed in claim 8 is characterized in that the material of described dielectric layer is a silica.
10. etching method for forming through hole as claimed in claim 9 is characterized in that, the etching gas that adopts during the described dielectric layer of etched portions comprises carbon tetrafluoride, fluoroform and argon gas.
11. etching method for forming through hole as claimed in claim 10 is characterized in that, the etching gas that adopts when interior remaining dielectric layer of the described through hole area of etching and described barrier layer comprises carbon tetrafluoride and nitrogen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101642638A CN102237296A (en) | 2010-04-29 | 2010-04-29 | Through hole etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101642638A CN102237296A (en) | 2010-04-29 | 2010-04-29 | Through hole etching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102237296A true CN102237296A (en) | 2011-11-09 |
Family
ID=44887818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101642638A Pending CN102237296A (en) | 2010-04-29 | 2010-04-29 | Through hole etching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102237296A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103869638A (en) * | 2014-03-21 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Photoetching alignment method implemented by penetrating through wafer |
| CN104701242A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Contact hole etching method |
| CN105087184A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Cleaning reagent, method for cleaning etching residues in semiconductor device and making method for metal interconnection layer |
| CN105513949A (en) * | 2015-12-30 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | Method for forming carbon substrate connection layer |
| CN106298644A (en) * | 2016-10-12 | 2017-01-04 | 武汉新芯集成电路制造有限公司 | The preparation method of semiconductor device |
| CN108305827A (en) * | 2017-01-11 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A method of removal etching procedure residual polyalcohol |
| CN108751123A (en) * | 2018-05-21 | 2018-11-06 | 赛莱克斯微***科技（北京）有限公司 | A kind of forming method of contact hole |
| CN109817572A (en) * | 2019-01-22 | 2019-05-28 | 上海华虹宏力半导体制造有限公司 | A kind of production method of lithographic method and damascene structure |
| CN109941957A (en) * | 2017-12-21 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004096080A (en) * | 2002-06-05 | 2004-03-25 | Samsung Electronics Co Ltd | Method for forming pattern of inter-metal insulating film |
| US20040163246A1 (en) * | 2003-02-21 | 2004-08-26 | Renesas Technology Corp. | Electronic device manufacturing method |
| JP2006049798A (en) * | 2004-07-02 | 2006-02-16 | Tokyo Electron Ltd | Manufacturing method of semiconductor device having groove wiring or connecting hole |
| CN1797718A (en) * | 2004-11-22 | 2006-07-05 | 南亚科技股份有限公司 | Process for removing a residue from a metal structure on a semiconductor substrate |
| CN101114607A (en) * | 2006-07-27 | 2008-01-30 | 上海宏力半导体制造有限公司 | Method for preventing copper dual-mosaic structure from producing defect in flattening technique |
| CN101312150A (en) * | 2007-05-21 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Dual mosaic structure forming method |
| CN101364565A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2010
- 2010-04-29 CN CN2010101642638A patent/CN102237296A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004096080A (en) * | 2002-06-05 | 2004-03-25 | Samsung Electronics Co Ltd | Method for forming pattern of inter-metal insulating film |
| US20040163246A1 (en) * | 2003-02-21 | 2004-08-26 | Renesas Technology Corp. | Electronic device manufacturing method |
| JP2006049798A (en) * | 2004-07-02 | 2006-02-16 | Tokyo Electron Ltd | Manufacturing method of semiconductor device having groove wiring or connecting hole |
| CN1797718A (en) * | 2004-11-22 | 2006-07-05 | 南亚科技股份有限公司 | Process for removing a residue from a metal structure on a semiconductor substrate |
| CN101114607A (en) * | 2006-07-27 | 2008-01-30 | 上海宏力半导体制造有限公司 | Method for preventing copper dual-mosaic structure from producing defect in flattening technique |
| CN101312150A (en) * | 2007-05-21 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Dual mosaic structure forming method |
| CN101364565A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701242B (en) * | 2013-12-05 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | The lithographic method of contact hole |
| CN104701242A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Contact hole etching method |
| CN103869638B (en) * | 2014-03-21 | 2016-01-20 | 武汉新芯集成电路制造有限公司 | A kind of lithography alignment method penetrating wafer |
| CN103869638A (en) * | 2014-03-21 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Photoetching alignment method implemented by penetrating through wafer |
| CN105087184A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Cleaning reagent, method for cleaning etching residues in semiconductor device and making method for metal interconnection layer |
| CN105513949B (en) * | 2015-12-30 | 2019-03-12 | 上海华虹宏力半导体制造有限公司 | The method for forming carbon substrate articulamentum |
| CN105513949A (en) * | 2015-12-30 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | Method for forming carbon substrate connection layer |
| CN106298644A (en) * | 2016-10-12 | 2017-01-04 | 武汉新芯集成电路制造有限公司 | The preparation method of semiconductor device |
| CN106298644B (en) * | 2016-10-12 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | The preparation method of semiconductor devices |
| CN108305827A (en) * | 2017-01-11 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A method of removal etching procedure residual polyalcohol |
| CN109941957A (en) * | 2017-12-21 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN109941957B (en) * | 2017-12-21 | 2021-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN108751123A (en) * | 2018-05-21 | 2018-11-06 | 赛莱克斯微***科技（北京）有限公司 | A kind of forming method of contact hole |
| CN108751123B (en) * | 2018-05-21 | 2022-05-20 | 赛莱克斯微***科技（北京）有限公司 | Method for forming contact window |
| CN109817572A (en) * | 2019-01-22 | 2019-05-28 | 上海华虹宏力半导体制造有限公司 | A kind of production method of lithographic method and damascene structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102237296A (en) | Through hole etching method | |
| CN100353520C (en) | Method for making dual inlay structure and removing its remnant polymer | |
| JP2002353308A (en) | Semiconductor device and its manufacturing method | |
| TW415022B (en) | Semiconductor device and method of manufacturing the same capable of reducing deterioration of low dielectric constant film | |
| CN104681403A (en) | Semiconductor and forming method thereof | |
| CN101364565A (en) | Method for manufacturing semiconductor device | |
| US7037822B2 (en) | Method of forming metal line in semiconductor device | |
| JP2004225159A (en) | Method for forming conductive copper structure | |
| CN110890315A (en) | Semiconductor structure with Damascus structure and preparation method thereof | |
| CN100570852C (en) | Form the method for the dual-damascene structure of no-etch stop layer | |
| US6635565B2 (en) | Method of cleaning a dual damascene structure | |
| KR100641506B1 (en) | Method for cleaning semiconductor device with dual damascene structure | |
| CN102054754A (en) | Manufacturing method for metal interconnection line | |
| KR20030056204A (en) | cleaning method of metal line for semiconductor device | |
| JP4963815B2 (en) | Cleaning method and semiconductor device manufacturing method | |
| CN102044481A (en) | Method for preventing corrosion of tungsten plug | |
| KR100436288B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100707589B1 (en) | Cleaning method after forming copper line | |
| US6881670B2 (en) | Interconnect process and method for removing metal silicide | |
| JP2004363447A (en) | Semiconductor device and method of manufacturing the same | |
| CN106033719A (en) | Formation method of semiconductor structure | |
| KR100317894B1 (en) | Method of manufacturing semiconductor device | |
| CN101908474A (en) | Method for manufacturing gate on wafer | |
| KR100640947B1 (en) | Method for Forming Line In Semiconductor Device | |
| TWI305945B (en) | Method of fabricating dual damascene structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20111109 |