CN102236065B

CN102236065B - Method for rapidly debugging and locating chip functional fault and debugging circuit

Info

Publication number: CN102236065B
Application number: CN201010155025.0A
Authority: CN
Inventors: 舒海军
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2010-04-22
Filing date: 2010-04-22
Publication date: 2015-07-01
Anticipated expiration: 2030-04-22
Also published as: CN102236065A

Abstract

The invention discloses a method for realizing rapid debugging and locating of a chip functional fault. The method is characterized by comprising the following steps: embedding a debugging circuit in a chip circuit, inputting a predefined signal by virtue of one or more pins of the chip to ensure the chip to enter into a debugging mode when the chip has the functional fault and selecting the internal signals to be observed of the chip according to the input predefined signal; outputting the selected internal signals of the chip by virtue of one predefined pin of the chip; and realizing the debugging and locating of the functional fault by observing the waveforms of certain internal signals in the working process of the chip and comparing the waveforms with the expected waveforms of the signals during design. The invention also discloses the debugging circuit used in the method. By adopting the method, the debugging and locating of the chip fault can be rapidly realized at low cost after the chip has the functional fault.

Description

The method of chip functions fault fast debugging location and debug circuit

Technical field

The present invention relates to chip design field, particularly relate to a kind of method that can realize chip functions fault fast debugging location.The present invention relates to the debug circuit in the method.

Background technology

The development of semiconductor process technology makes the further raising of integrated circuit (IC) integrated level become possibility.Electronics industry has strided forward the VLSI (very large scale integrated circuit) epoch from the large scale integrated circuit epoch.Along with the maturation of deep submicron process technology, chip design industry is faced with severe problem: due to the development of demand of chip functions and performance, chip-scale is increasing, operating rate is more and more higher, construction cycle is more and more longer, and design cost is more and more higher, and designing quality is more and more restive, the design occurred after chip production and production problem probability increasing, the time of looking up the fault and human cost and complexity also increasing.Before 10 years when design 3 layers of metal level, as fruit chip has problem, metal level directly can be studied to check circuit.Now for 9 layers of metal level and the even less intermetallic distance of 0.13mm, problem is not just so simple.When chip goes wrong, in order to the reason that locates errors, may need to observe some key signal of chip internal; Usual way utilizes focused ion beam (FIB) to be insinuated into chip internal.The method not only cost is high, and the time is long, and is easy to destroy chip or introduce other problems in so little intermetallic distance.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of method realizing chip functions fault fast debugging location, after there is functional fault in chip, and can the debugging that failure of chip be realized of fast and low-cost and location; For this reason, the present invention also will provide a kind of debug circuit realized in described method.

For solving the problems of the technologies described above, the method for chip functions fault fast debugging location of the present invention adopts following technical scheme to realize:

A debug circuit is embedded at chip circuit, when there is functional fault in chip, the signal inputting one section of predefine good by one or more pins of this chip makes chip enter debugging mode, and the signal good according to the predefine of described input is selected internal chip enable signal to be seen; The internal chip enable signal chosen is exported by the pin that a predefine of chip is good; By observing the waveform of some internal signal in chip operation process, and compared with the expectation waveform of this signal during design, the debugging of practical function fault and location.

The present invention's debug circuit realized in described method refers to the description of embodiment part.

Adopt method of the present invention, the little debug circuit of a fritter area can be embedded in when chip design at chip.After chip production completes, when needing to debug if there is functional fault, can when not destroying chip and doing focused ion beam (FIB) engineering, some key signal of chip internal just can be observed by operating the external terminal of chip, thus can the debugging that failure of chip be realized of fast and low-cost and location.Make people just can control and observe the signal of chip internal in chip exterior, and do not exceed intended target on cost and time budget.

Accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:

Fig. 1 is each signal waveforms of one embodiment of the invention;

Fig. 2 is the debug circuit one example structure figure being embedded in chip internal.

Embodiment

The method of described chip functions fault fast debugging location embeds one piece of debug circuit therein in one embodiment.When functional fault appears in chip, the signal inputting one section of predefine good by one or more pins of this chip makes chip enter debugging mode; And the signal good according to the predefine of described input is selected internal chip enable signal to be seen; The internal chip enable signal chosen is exported by the pin that a predefine of chip is good; By observing the waveform of some internal signal in chip operation process, and compared with the expectation waveform of this signal during design, the debugging of practical function fault and location.

Shown in Figure 1, such as, from the IO0 pin input high level signal of chip, from IO1 pin input clock signal, from the signal that IO2, IO3, IO4 pin input predefine is good; Wherein, from the input of IO4 pin is serial data, after conversion, become parallel data; Front 8 data inputted from IO4 pin are that " A5 " (certainly, front 8 data of input may also be other data, such as " 9A "; If object be in the debug circuit be embedded at chip setting be A5, so only have when front 8 data inputted from IO4 pin are for " A5 ", namely both have matched, just can enter debugging mode one, internal chip enable signal to be seen is outputted to, otherwise internal chip enable signal debug function can not be realized), and make chip enter debugging mode together with the signal inputted from IO0, IO1, IO2, IO3, IO4 pin.The selection signal of internal chip enable signal to be seen is produced, for selecting internal chip enable signal to be seen from rear 6 data of IO4 pin input.The internal chip enable signal that will observe selected is exported from IO5 pin.

Whether method of the present invention has CPU all applicable to chip internal, particularly more applicable when chip internal does not have CPU or CPU cisco unity malfunction.As fruit chip power on after cisco unity malfunction, the duty of watching internal chip enable signal can be gone by operating the pin of chip exterior, making it possible to the location of mistake carrying out functional fault fast; And do not need chip internal to have CPU or CPU be able to normally work.

Shown in composition graphs 2, in one embodiment, described debug circuit comprises:

Debugging mode generation module, for generation of debugging mode signal, makes chip enter debugging mode.The signal that debugging mode signal is good according to one section of predefine of the one or more pin inputs from chip produces.

Serioparallel exchange module, converts the serial data inputted from chip one pin to parallel data, namely for making chip enter debugging mode, again for generation of the selection signal selected internal signal to be seen; Wherein, front 8 data of serial input are used for participation makes chip enter debugging mode, and after entering debugging mode, rear 6 data of serial input are for selecting internal signal to be seen.

Internal signal module to be seen, for generation of multiple internal chip enable signal to be seen; The signal that function debugging is played a crucial role is picked out from several thousand internal signals of chip.Chip complexity is higher, and the internal signal to be seen that need select is also more, and certain cost can increase; Only have selected 64 keys internal signal to be seen in an embodiment of the present invention.

Observation signal selector switch, is connected with serioparallel exchange module with internal signal module to be seen, under the control selecting signal, select internal signal to be seen accordingly to export as observation signal.

Observation signal o controller, is connected with observation signal selector switch with debugging mode generation module, under the control of debugging mode signal, selects the normal function signal exporting observation signal or chip.

When chip is in debugging mode, chip can export selected internal signal according to selection signal by the some pins pre-defined.As shown in Figure 1, 2, observation signal (internal signal namely to be seen) is exported by the pin IO5 of chip.

Shown in composition graphs 1,2, in one embodiment, described method have employed six pins of chip, be respectively IO0, IO1, IO2, IO3, IO4, IO5, these six pins except when there is functional fault for except debugging, also may be used for the normal input/output function of chip, realize debugging and pin multiplexing when normally using.

After chip design completes and produces, when finding that this chip has a functional fault in testing, some internal signal of chip can be observed by above-mentioned six pins handling this chip, detailed process is, from pin IO0 input high level, pin IO1 input clock sequence, from pin IO2 input high level signal, from pin IO3 input low level signal, input particular serial 0,1 sequence signal from pin IO4.When the debug circuit in chip detects that the signal of pin IO0, IO2 is high level simultaneously, the signal of pin IO3 is low level, and 0,1 sequence that pin IO4 inputs is sexadecimal number " A5 " through serioparallel exchange, then enter pre-designed debugging mode.

Once chip enters debugging mode, then 6 serial data signals of pin IO4 input, through serioparallel exchange module, produce the selection signal selected internal signal to be seen, as selection signal " 010001 " (binary number) in Fig. 1.Select signal selector to select the selection signal " 010001 " that produced by serioparallel exchange module, then observation signal selector switch selects predefined 18th internal signal of debugging mode from 64 internal signal modules to be seen, outputs to outside chip through pin IO5.By observing the waveform of this output signal, just can infer the duty of other signals of chip internal, thus realize debugging and the location of failure of chip.

Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. the method for a chip functions fault fast debugging location, it is characterized in that: be embedded in a debug circuit at chip circuit, when there is functional fault in chip, the signal inputting one section of predefine good by one or more pins of this chip makes chip enter debugging mode, and the signal good according to the predefine of described input is selected internal chip enable signal to be seen; The internal chip enable signal chosen is exported by the pin that a predefine of chip is good; By observing the waveform of some internal signal in chip operation process, and compared with the expectation waveform of this signal during design, the debugging of practical function fault and location.

2. the method for claim 1, is characterized in that: when high level signal or the low level signal of a certain pin input of chip, and the good signal of the predefine coordinating other pin to input makes chip enter debugging mode.

3. realize the debug circuit in method described in claim 1, it is characterized in that, described debug circuit is embedded in chip circuit, when there is functional fault in chip, the signal inputting one section of predefine good by one or more pins of this chip makes chip enter debugging mode, and the signal good according to the predefine of described input is selected internal chip enable signal to be seen; The internal chip enable signal chosen is exported by the pin that a predefine of chip is good; It comprises:

Debugging mode generation module, for generation of debugging mode signal, makes chip enter debugging mode;

Serioparallel exchange module, converts the serial data inputted from chip one pin to parallel data, namely for making chip enter debugging mode, again for generation of the selection signal selected internal signal to be seen; Wherein, front 8 data of serial input are used for participation makes chip enter debugging mode, and after entering debugging mode, rear 6 data of serial input are for selecting internal signal to be seen;

Internal signal module to be seen, for generation of multiple internal chip enable signal to be seen;

Observation signal selector switch, is connected with serioparallel exchange module with internal signal module to be seen, under the control selecting signal, select internal signal to be seen accordingly to export as observation signal;