WO2024065693A1 - Method and device for generating compression test pattern - Google Patents

Method and device for generating compression test pattern Download PDF

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Publication number
WO2024065693A1
WO2024065693A1 PCT/CN2022/123320 CN2022123320W WO2024065693A1 WO 2024065693 A1 WO2024065693 A1 WO 2024065693A1 CN 2022123320 W CN2022123320 W CN 2022123320W WO 2024065693 A1 WO2024065693 A1 WO 2024065693A1
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column vector
interval
maximally
vector
matrix
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PCT/CN2022/123320
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French (fr)
Chinese (zh)
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王泽中
王幸
王乃行
黄宇
张威威
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华为技术有限公司
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Priority to PCT/CN2022/123320 priority Critical patent/WO2024065693A1/en
Publication of WO2024065693A1 publication Critical patent/WO2024065693A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

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  • Embodiments of the present application relate to the field of integrated circuits, and more specifically, to a method and apparatus for generating a compressed test vector.
  • test vectors are needed to test the chip.
  • a technology for generating compressed test vectors namely test compression technology, has been derived.
  • test compression technology in the test vector generation process will bring many additional software solution power consumption and automatic test pattern generation (ATPG) tool performance issues.
  • vector compaction technology is usually basically used, that is, the ATPG tool first generates fault detection stimuli and then uses the compressed increment solution solution.
  • the implicit values in the compressor increase, which will lead to a decrease in the success rate of vector compaction and a large number of test vectors; at the same time, the unsuccessful fault detection stimuli need to be regenerated in the subsequent vector compaction process, which also introduces a lot of software power consumption.
  • the commonly used Gaussian elimination technology calculates the compressed implicit values on the irrelevant bits and updates them to the background of vector compaction to improve the success rate of vector compaction.
  • the Gaussian elimination technology consumes a lot of power, resulting in a low efficiency in the process of generating compressed test vectors.
  • the embodiments of the present application provide a method and device for generating compressed test vectors, which can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors while increasing the success rate of test vector merging.
  • a method for generating a compressed test vector comprising: obtaining a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; filling a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generating a compressed test vector according to the second background vector.
  • the above method generates a compressed test vector after filling the first background vector with an implicit value, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined. While increasing the success rate of test vector merging, it can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors.
  • filling the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being the second linear correlation matrix; and filling the first target bit with an implicit value according to the first target bit information to obtain a second background vector.
  • the linear correlation matrix By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.
  • the first target bit information indicating the first target bit is determined based on the first linear correlation matrix and the first maximally irrelevant group
  • the first target bit information is a second linear correlation matrix, including: according to the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; according to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  • the linear correlation matrix By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix and the background vector that needs to be filled, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.
  • filling the first target bit with an implicit value based on the first target bit information includes: determining the position of the first target bit based on whether the elements in the second linear correlation matrix are 1, the irrelevant bits in the first target bit corresponding one-to-one to the elements in the second linear correlation matrix; and filling the implicit value into the determined position of the first target bit based on the decompression matrix and the first background vector.
  • filling an implicit value into the first target bit in the first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.
  • the background vector is updated, and subsequent partial conflict problems are avoided. While taking into account the software power consumption, the efficiency of generating compressed test vectors is improved.
  • the first background vector includes at least one column vector
  • the first maximally irrelevant group corresponds one-to-one to the column vector
  • determining the first target bit information indicating the first target bit based on the first maximally irrelevant group includes: determining the target column vector interval based on the ranks of multiple of the first maximally irrelevant groups, the target column vector interval including at least one continuous column vector.
  • determining the target column vector interval based on the ranks of multiple first maximal independent groups includes: obtaining at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equations of the first background vector, and the second linear equation group corresponding one-to-one to continuous column vector intervals in the first background vector; determining at least one first column vector interval based on the at least one second linear equation group, the number of linear independent equations of the second linear equation group corresponding to the first column vector interval being greater than a first threshold; determining a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determining the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.
  • determining the target column vector interval based on the second column vector interval includes: determining that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; judging whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; updating the second column vector interval to a third column vector interval based on the judgment result; determining that the rank of at least one of the first maximally irrelevant groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; and determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.
  • updating the second column vector interval to a third column vector interval based on the judgment result includes: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determining the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
  • filling the first target bit with an implicit value based on the first target bit information includes: calculating the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and filling the implicit value into the first target bit.
  • the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.
  • a device for generating a compressed test vector comprising a processing module, the processing module being used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; fill a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, the first target bit including all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.
  • the processing module is specifically used to: determine first target bit information indicating a first target bit based on the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being a second linear correlation matrix; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.
  • the processing unit is further specifically used to: obtain a second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector according to the decompression matrix, the first linear equation group including the decompression equation corresponding to the first background vector; add the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group according to the first maximally irrelevant group to obtain a third maximally irrelevant group; determine the second linear correlation matrix according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  • the processing unit is further specifically used to: determine the position of the first target bit according to whether the elements in the second linear correlation matrix are 1, and the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix; fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.
  • the processing unit is specifically used to: determine first target bit information indicating a first target bit based on the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.
  • the first background vector includes at least one column vector
  • the first maximally irrelevant group corresponds one-to-one to the column vector
  • the processing unit is further specifically used to: determine the target column vector interval based on the ranks of multiple first maximally irrelevant groups, and the target column vector interval includes at least one continuous column vector.
  • the processing unit is further specifically used to: obtain at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equation of the first background vector, and the second linear equation group corresponding one-to-one to the continuous column vector interval in the first background vector; determine at least one first column vector interval based on the at least one second linear equation group, the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; determine a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determine the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.
  • the processing unit is further specifically used to: determine that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; based on the judgment result, update the second column vector interval to the third column vector interval; determine that the rank of at least one of the first maximally irrelevant groups corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determine that the target column vector interval is the union of the third column vector interval and the fourth column vector interval.
  • the processing unit is also used to: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determine the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
  • the processing unit is also used to: calculate the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and fill the implicit value into the first target bit.
  • the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.
  • a computer program product which includes instructions. When the instructions are executed on a computer, the computer executes the method described in the first aspect or any implementation of the first aspect.
  • a device for generating a compressed test vector comprising a processor and a memory, wherein the memory is used to store a program, and the processor is used to call and run the program from the memory to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.
  • a computer-readable storage medium comprising a computer program, which, when executed on a computer, enables the computer to execute the method for testing control software in the first aspect or any possible implementation of the first aspect.
  • FIG. 1 is a schematic block diagram of a chip design and manufacturing process applicable to an embodiment of the present application.
  • FIG. 2 is a schematic block diagram of a process for generating a compressed test vector applicable to an embodiment of the present application.
  • FIG3 is a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.
  • FIG. 6 is a schematic block diagram of an apparatus for generating a compressed test vector according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the hardware structure of an apparatus for compressing test vectors according to an embodiment of the present application.
  • Chips which can also be called integrated circuits (ICs), or can be understood as the carrier of integrated circuits, are usually a way to miniaturize circuits and are often manufactured on the surface of semiconductor wafers.
  • the process 100 of chip design and manufacturing can usually be divided into three parts: design part 101, manufacturing part 102, and packaging and testing part 103.
  • design part 101 design part 101
  • manufacturing part 102 manufacturing part 102
  • packaging and testing part 103 packaging and testing part 103.
  • DFT design for testability
  • the specific chip testing process mainly includes: first, generate test patterns through automatic test pattern generation (ATPG) tools; then input the test patterns into the chip under test through automatic test equipment (ATE); finally, compare the test response of the chip under test with the expected response to see if it is consistent, to know whether the chip has defects.
  • ATG automatic test pattern generation
  • ATE automatic test equipment
  • test compression technology is used in the packaging test part of the chip.
  • the generation process of the compressed test vector can be: (1)
  • the ATPG tool models the possible faults of the chip (such as the faults in the fault list) and generates a fault detection stimulus.
  • the fault detection stimulus includes one or more bits, which include fixed bits and don't care bits.
  • the value filled with the fixed bit is a valid value (specified bit), and the value filled with the don't care bit is a don't care value (don't care bit).
  • the valid value can be understood as a fixed value in the fault detection stimulus, which is used to detect the corresponding fault.
  • the don't care value can be understood as a value that can be arbitrarily set in the fault detection stimulus, for example, it can be any value between 0 and 1.
  • n fault detection stimuli ( a1 , a2 , ..., an ) are generated, wherein each box represents a bit, and a box filled with a pattern indicates that the bit is a fixed bit, and a box without a pattern fill indicates that the bit is a don't care bit.
  • each fault detection stimulus shown in FIG2 includes only 10 bits. In the actual generated fault detection stimulus, the bits included can be in the millions, and the data scale is relatively large. It should be understood that one fault detection stimulus corresponds to one fault;
  • n fault detection stimuli (a 1 , a 2 , ..., a n ) are merged and compressed one by one, that is, two fault detection stimuli in the n fault detection stimuli are merged to obtain a background vector (background merged cube), and then compressed to obtain a compressed background vector, ensuring that the merged fault detection stimuli can be compressed successfully, and then adding another fault detection stimuli to the background vector obtained by merging the two fault detection stimuli, that is, merging and compressing the three fault detection stimuli, and so on.
  • the n fault detection stimuli can finally be merged to obtain a background vector A, and then the background vector is compressed to obtain a compressed background vector A'.
  • the number of elements included in the background vector A is the same as the number of elements included in a fault detection stimuli, and the number of elements included in the compressed background vector A' is less than the number of elements included in the background vector A.
  • merging is to merge multiple fault detection stimuli into one, that is, merging is to reduce the number of fault detection stimuli, and compression is to shorten the length of the fault detection stimuli, that is, compression is to reduce the number of elements in the fault detection stimuli, and the merging process is accompanied by compression, or it can be called incremental compression during the merging process, that is, each time a fault detection stimulus is merged, it is necessary to check whether incremental compression can be successfully performed to ensure that the merged state can be compressed successfully;
  • a fault detection stimulus is generated, and then the generated fault detection stimulus increments are merged and compressed into the compressed background vector to generate a compressed test pattern. For example, as shown in FIG2 , based on the background vector A, a fault detection stimulus b1 is generated, and then A and b1 are merged and compressed. After the compression is successful, a fault detection stimulus b2 is generated based on the background vector generated by merging A and b1 . Then the background vector generated by merging A and b1 and b2 are merged and compressed. After the compression is successful, a fault detection stimulus b3 is generated based on the background vector generated by merging b2 .
  • a background vector B is obtained by merging A and m fault detection stimuli ( b1 , b2 , ..., bm ).
  • a compressed test vector B' is obtained.
  • the compressed test vector may be stored in ATE. After ATE injects the compressed test vector into the chip under test, the compressed test vector is decompressed by a decompression circuit on the chip under test and then input into the circuit under test in the chip under test.
  • the compressed test vector B' may be injected into the chip under test and then input into the circuit under test through a decompression circuit to be restored to a merged vector of the n fault detection stimuli ( a1 , a2 , ..., an ) and the m fault detection stimuli ( b1 , b2 , ..., bm ), that is, a merged background vector B.
  • the compressed test vector may also be referred to as a compressed seed. It should also be understood that the generation process of the compressed test vector may be performed by an ATPG tool. It should also be understood that in the generation process of the compressed test vector, the vector obtained by merging the fault detection stimulus may be referred to as a background vector, and after further compression, the vector obtained may be referred to as a compressed background vector, and the vector finally obtained may be referred to as a compressed test vector, that is, after merging the compressed background vector and compressing the last fault detection stimulus, the vector obtained may be referred to as a compressed test vector.
  • the fixed bits in the fault detection stimulus generated by the ATPG tool correspond to the don't care bits before the background vector is compressed, that is, they correspond to the don't care bits of the background vector obtained by merging the fault detection stimulus.
  • the fill value of the don't care bits before the background vector is compressed may be determined due to the compression operation.
  • the fill value of the don't care bits before the background vector is compressed can be called an implied value.
  • the fault detection stimulus generated by the ATPG tool may not satisfy the compression operation and therefore cannot be incrementally merged into the background vector, thereby causing a conflict and increasing the power consumption of dynamic compaction.
  • the background vector B restored in the above-mentioned circuit under test corresponds to a scan chain in the circuit under test.
  • a scan chain includes at least one scan cell.
  • the value of each scan cell is a value in the background vector B, that is, an element in the vector.
  • the vector input to the circuit under test is the compressed test vector B'. If each compressed value in the compressed test vector B' is regarded as a free variable, each value in the background vector B can be linearly represented by part of the compressed value or all of the compressed value in the compressed test vector B' due to the compression operation, that is, the value of each scan cell can be linearly represented by the input free variable, and the number of scan cells is much larger than the number of free variables. Therefore, there are a lot of linear correlations between the multiple equations corresponding to the multiple scan cells, that is, the values on many scan cells can be linearly represented by the values on other scan cells.
  • an embodiment of the present application proposes a method for generating test vectors, which can greatly reduce the power consumption of test vector generation while increasing the success rate of test vector merging.
  • Matrix A set of complex or real numbers arranged in a rectangular array. For example, a table of m ⁇ n numbers with m rows and n columns is called a matrix of m rows and n columns, or m ⁇ n matrix for short. A matrix with n rows and columns is called an n-order matrix, or an n-order square matrix. In the embodiments of the present application, when the test vectors involved are represented by matrices, the matrix elements mainly include 0 and 1.
  • Vector group A set of column vectors or row vectors of the same dimension.
  • a matrix can be understood as consisting of vector groups.
  • Maximal independent group generally refers to the maximal linearly independent group, which is the linearly independent vector group with the largest number of vectors in the linear space. For example, its definition can be: suppose there is a vector group A: ⁇ 1, ⁇ 2, ⁇ 3, ..., ⁇ s, if r vectors ⁇ 1, ⁇ 2, ..., ⁇ r can be selected from A, satisfying the vector group A0: ⁇ 1, ⁇ 2, ..., ⁇ r are linearly independent, and any vector in the vector group A can be linearly represented by several vectors in the vector group A0, then the vector group A0 is called a maximal linearly independent group of the vector group A, abbreviated as the maximal independent group.
  • the rank of a matrix is the highest order of its non-zero minors
  • the rank of a vector group is the number of vectors contained in its maximal independent group.
  • the matrix is said to be full rank.
  • the vector group when the number of vectors contained in the maximal independent group is equal to the number of vector groups, the vector group is said to be full rank.
  • FIG3 shows a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application.
  • the method 300 includes:
  • the chip under test is a chip for testing with compressed test vectors
  • the chip under test includes a decompression circuit, which can decompress the compressed test vectors.
  • the above step S301 can be performed by an ATPG tool, which can obtain the decompression circuit structure of the chip under test, and then model according to the decompression circuit structure to extract the decompression matrix.
  • the decompression circuit structure is the decompression circuit structure of the test circuit of the chip to be tested. Therefore, when the ATPG tool generates fault detection stimuli, and merges and compresses the fault detection stimuli, the fault detection stimuli are merged and compressed according to the relevant characteristics of the decompression circuit structure, so that the decompression circuit can subsequently completely decompress the merged and compressed fault detection stimuli, thereby improving the test efficiency of the chip.
  • the decompression circuit structure is a linear-based decompression circuit structure.
  • the decompression circuit structure includes a ring generator and a phase shifter, so that a decompression matrix can be constructed according to the mapping relationship between the ring generator and the phase shifter.
  • the ring generator includes a plurality of shift registers, and the mapping relationship corresponding to the ring generator can be expressed by the following formula (1):
  • r t represents the value of the shift register at time t
  • R f represents the linear matrix corresponding to the feedback connection structure of the shift register itself
  • r t-1 represents the value of the shift register in the ring generator at time t-1
  • R v represents the linear matrix corresponding to the connection structure between the input pin and the shift register
  • x t represents the compressed value injected by the tth tap
  • the linear matrix corresponding to the phase shifter is P
  • the shift value of the shift register included in the ring generator at time t can be expressed by the following formula (2):
  • b ts represents the shift value of the shift register, or b ts represents the background vector obtained after the combined fault detection stimulus, r ts represents the value of the shift register at time ts, s represents the number of initialization taps when the compressed test vector (i.e., compressed solution) is input into the decompression circuit beat by beat, or s represents the number of initialization taps before the effective tap when the compressed test vector is input into the decompression circuit.
  • the following formula decompression mapping formula (3) can be obtained.
  • the first matrix on the right side of the formula (3) is the decompression matrix.
  • the corresponding relationship between the matrix b and the matrix x can be obtained, that is, the corresponding relationship between the value in the background vector and the compressed value of the background vector can be obtained.
  • the decompression matrix E can be defined as the following formula (4):
  • the decompressed matrix can be decomposed into a first linear correlation matrix and a first maximally independent group.
  • the first linear correlation matrix and the first maximally independent group can be hierarchically constructed.
  • the first linear correlation matrix can also be called a first linear correlation table.
  • the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the matrix block row of the decompressed matrix. It should be understood that the product of the two corresponding to the matrix block row of the decompressed matrix may mean that the product is the same as the matrix block row, or that the deviation of the product from the matrix block row is within a preset range, or that the product is the same as the matrix block row after being multiplied by a certain coefficient, and the present application does not limit this.
  • a matrix block row of a decompressed matrix corresponds to a column vector of a background vector, such as bi , and a column vector can also be called a test cycle. That is, the maximally irrelevant group and the linear correlation matrix within a test cycle can be obtained.
  • the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the decompression matrix.
  • the product of the two corresponding to the decompression matrix may mean that the product is the same as the decompression matrix, or that the deviation between the product and the decompression matrix is within a preset range, or that the product is the same as the decompression matrix after being multiplied by a certain coefficient, and the present application does not limit this.
  • the maximally irrelevant group of the test cycle set that is, the first maximally irrelevant group
  • the maximally irrelevant group M is calculated for ⁇ i ⁇ 1 ⁇ i ⁇ m
  • the linear correlation matrix of the test cycle set that is, the first linear correlation matrix, such as D
  • the first background vector may be any background vector in Fig. 2.
  • the first background vector may be any background vector in a static compaction process and a dynamic compaction process.
  • the first background vector may be a background vector obtained after the ATPG tool merges at least one fault detection stimulus.
  • the first background vector includes fixed bits and irrelevant bits, and the irrelevant bits include irrelevant bits determined by the compression operation, that is, when the first background vector is compressed, some or all of the irrelevant bits in the first background vector will be determined.
  • the positions and determined values of some or all of the irrelevant bits that have been determined, that is, implicit values it is necessary to determine the positions and determined values of some or all of the irrelevant bits that have been determined, that is, implicit values, and then fill the implicit values into the first target bit.
  • the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally independent group to obtain the second background vector may be any one of the following ways 1 and 2.
  • way 1 can be called a dynamic filling algorithm
  • way 2 can be called a static filling algorithm.
  • multiple background vectors will be generated.
  • way 1 and way 2 can be used alone.
  • the embodiment of the present application does not limit the number of times way 1 or way 2 is used; way 1 and way 2 can also be used in combination.
  • the embodiment of the present application does not limit the order of their use and the number of times they are used.
  • S304 Determine first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally independent group, where the first target bit information is the second linear correlation matrix.
  • the first target bit information can be used to indicate the first target bit, or in other words, the first target bit information can be used to indicate the position of the first target bit, that is, the first target bit information can be used to indicate which irrelevant bits need to be filled with implicit values.
  • the first target bit information is a matrix, namely, a second linear correlation matrix.
  • the second linear correlation matrix can also be called a second linear correlation table.
  • the method for determining the first target bit information may be, that is, the method for determining the second linear correlation matrix may be, based on the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; based on the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; and determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  • the second linear correlation matrix can be called the updated first linear correlation matrix, which is not limited in this application.
  • the second background vector is a vector obtained by updating the first background vector, that is, a background vector obtained by filling the irrelevant bits of the first background vector with implicit values.
  • a fault detection stimulus can be generated according to the updated first background vector, and the generated fault detection stimulus can avoid conflicts when merging and compressing.
  • the first target bit information is the second linear correlation matrix.
  • the position of the first target bit can be determined based on whether the elements in the second linear correlation matrix are 1, and then the implicit value is filled into the determined position of the first target bit based on the decompression matrix and the first background vector, wherein the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix.
  • each row vector in the updated decompressed matrix linear correlation table corresponds to a bit in the first background vector, and each row vector includes one or more elements, and the value of the element can be 0 or 1.
  • the element is 1, it means that the corresponding bit can be linearly represented by the linear independent equation group in the second maximal independent group. Therefore, the position of the first target bit can be determined according to the value of the element in the updated decompressed matrix linear correlation table. After determining the position of the first target bit, the value determined on the independent bit, that is, the implicit value, is determined by calculation.
  • Method 2 includes steps S306-S307:
  • S306 Determine first target bit information indicating a first target bit according to the first maximally irrelevant group, where the first target bit information is a target column vector interval in the first background vector.
  • the first background vector includes at least one column vector.
  • bi in the above formula (3) represents a column vector.
  • a column vector can be called a test cycle.
  • the first maximally irrelevant group may be a maximally irrelevant group within a test cycle, such as C i in the above step S301.
  • the first maximally irrelevant group corresponds to a test cycle, that is, the first maximally irrelevant group corresponds to the column vector of the first background vector one-to-one
  • the target column vector interval may be determined according to the ranks of the plurality of first maximally irrelevant groups, and the target column vector interval includes at least one column vector.
  • the target column vector interval is determined according to the ranks of multiple first maximal independent groups as follows: at least one second linear equation group is obtained according to the decompression matrix and the first background vector, the second linear equation group includes the decompression equation of the first background vector, and the second linear equation group corresponds one-to-one to the continuous column vector intervals in the first background vector; at least one first column vector interval is determined according to at least one second linear equation group, and the number of linear independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; a second column vector interval is determined according to at least one first column vector interval, and the second column vector interval is the column vector interval with the largest number of column vectors included in at least one first column vector interval; a target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.
  • the first threshold may be determined in the following manner: in the process of generating each test vector, the first threshold may adopt different artificial experience values, or may be dynamically adjusted through learning;
  • a method for determining a target column vector interval based on the second column vector interval may be: determining that the rank of at least one first maximally irrelevant group corresponding to the second column vector interval is a first numerical value; determining whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first numerical value; based on the judgment result, updating the second column vector interval to a third column vector interval; determining that the rank of at least one first maximally irrelevant group corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.
  • the method of updating the second column vector interval to the third column vector interval can be: when the number of linearly independent equations corresponding to the second column vector interval is not equal to the first value, determine the value of some constant terms in the linearly independent equations, so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linearly independent equation group corresponding to the third column vector interval is equal to the first value.
  • the second column vector interval includes the same number of column vectors as the third column vector interval, and the difference is that the values on some irrelevant bits in the third column vector interval are determined, that is, the value of the constant term is determined.
  • the above method of determining the value of the constant term may be to randomly assign the value according to the probability of occurrence of the value of the constant term.
  • a specific method for determining a target column vector interval may be: 1) obtaining, according to the decompression matrix, a linear equation of the irrelevant value in each column vector in the first background vector with respect to the compressed value, that is, a linear equation of the element in each test cycle with respect to the compressed value; 2) then calculating the linearly independent equations in each test cycle; 3) then obtaining a test cycle region in which the number of linearly independent equations in the test cycle region is greater than a first threshold, or in other words, obtaining a column vector interval greater than or equal to the first threshold; 4) selecting a first test cycle region from the obtained test cycle region, the first test cycle region being the region with the largest length in the obtained test cycle region, that is, the first column vector interval including the most column vectors, for example (b i , b j ); 5) randomly filling values into irrelevant bits in the first test cycle region so that the first test cycle region is full rank, that is, the number of linearly independent equations in the first column
  • full rank means that the number of linearly independent equations in the decompression equation group of a certain column vector interval in the background vector is equal to the rank of the maximal independent group of the decompression matrix corresponding to the column vector interval, or in other words, the number of vectors included in the maximal independent group of the decompression matrix corresponding to the column vector interval is equal.
  • the implicit value of the irrelevant bit in the target column vector interval can be calculated according to the target column vector interval and the decompression matrix; the implicit value is filled into the first target bit to obtain the second background vector.
  • the second background vector can be obtained by determining part of the value in the first background vector, that is, updating the first background vector, so that after the first background vector is updated, the subsequent conflict problem caused by the partially determined irrelevant bit can be avoided, and the efficiency of generating the compressed test vector can be improved.
  • the second background vector can be directly compressed to generate a compressed test vector, or a fault detection stimulus can be generated based on the second background vector.
  • a compressed test vector is generated.
  • a compressed test vector can be generated after repeating one or more operations similar to the above steps S301-S302. The present application does not limit this.
  • the above method fills the first background vector with implicit values, generates the second background vector, and then generates the compressed test vector, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined, thereby improving the efficiency of generating compressed test vectors.
  • FIG4 is a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application. Specifically, the method 400 includes:
  • the first background vector may be a background vector obtained after a static compaction process, or may be a background vector obtained during a dynamic compaction process, and the present application does not impose any limitation on this.
  • the maximal independent group B1 is a maximal independent group of the coefficient matrix of the linear equation group corresponding to the first background vector, and the linear equation group includes the compression equation of the first background vector.
  • the linear correlation matrix of the decompressed matrix is updated from D to Q.
  • FIG5 shows a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application.
  • the method 500 includes:
  • the first background vector may be a background vector obtained after a static compaction process, or may be a background vector obtained during a dynamic compaction process, and the present application does not impose any limitation on this.
  • the linear equation group corresponding to multiple column vector intervals includes the decompression equation of the background vector, and the rank of the linear equation group corresponding to each column vector interval in the multiple column vector intervals can be called the interval rank, that is, the above step S502 is to obtain multiple interval ranks.
  • S503 Determine whether the rank is greater than a first threshold.
  • S504 Fill in the rank of a column vector interval with the largest number of consecutive column vectors among multiple column vector intervals whose ranks are greater than a first threshold, to be full rank.
  • the full rank interval is updated to be the set of the full rank interval determined in step S504 and its adjacent intervals.
  • the implicit value of the updated full rank interval is calculated and filled into the first background vector to obtain the second background vector.
  • Fig. 6 shows a schematic block diagram of an apparatus 600 for generating a compressed test vector according to an embodiment of the present application.
  • the apparatus 600 can execute the method for generating a compressed test vector according to the embodiment of the present application.
  • the device includes a processing module 601 .
  • the processing module 601 is used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to the decompression matrix corresponding to the chip under test, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test; fill an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.
  • FIG7 is a schematic diagram of the hardware structure of a device for compressing test vectors according to an embodiment of the present application.
  • the device 700 for compressing test vectors shown in FIG7 includes a memory 701, a processor 702, a communication interface 703, and a bus 704.
  • the memory 701, the processor 702, and the communication interface 703 are connected to each other through the bus 704.
  • the memory 701 may be a read-only memory (ROM), a static storage device, and a random access memory (RAM).
  • the memory 701 may store a program. When the program stored in the memory 701 is executed by the processor 702, the processor 702 and the communication interface 703 are used to execute the various steps of the method for compressing the test vector of the embodiment of the present application.
  • Processor 702 can adopt a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits to execute relevant programs to implement the functions required to be performed by the units in the device for compressing the test vector of the embodiment of the present application, or to execute the method for compressing the test vector of the embodiment of the present application.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • GPU graphics processing unit
  • the processor 702 may also be an integrated circuit chip with signal processing capability.
  • each step of the method for compressing test vectors in the embodiment of the present application may be completed by hardware integrated logic circuits in the processor 702 or software instructions.
  • the processor 702 may also be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components.
  • DSP digital signal processor
  • FPGA field programmable gate array
  • the methods, steps, and logic diagrams disclosed in the embodiments of the present application may be implemented or executed.
  • the general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.
  • the software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc.
  • the storage medium is located in the memory 701, and the processor 702 reads the information in the memory 701, and combines its hardware to complete the functions required to be performed by the units included in the device for compressing the test vector of the embodiment of the present application, or executes the method for compressing the test vector of the embodiment of the present application.
  • the communication interface 703 uses a transceiver such as, but not limited to, a transceiver to implement communication between the device 700 and other devices or a communication network. For example, the traffic data of an unknown device can be obtained through the communication interface 703.
  • a transceiver such as, but not limited to, a transceiver to implement communication between the device 700 and other devices or a communication network. For example, the traffic data of an unknown device can be obtained through the communication interface 703.
  • the bus 704 may include a path for transmitting information between various components of the device 700 (eg, the memory 701 , the processor 702 , and the communication interface 703 ).
  • the device 700 may also include other devices necessary for normal operation. At the same time, according to specific needs, those skilled in the art should understand that the device 700 may also include hardware devices for implementing other additional functions. In addition, those skilled in the art should understand that the device 700 may also only include the devices necessary for implementing the embodiments of the present application, and does not necessarily include all the devices shown in FIG. 7.
  • An embodiment of the present application also provides a computer-readable storage medium that stores program code for execution by a device, wherein the program code includes instructions for executing the steps in the above-mentioned method for compressing test vectors.
  • An embodiment of the present application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions.
  • the program instructions When the program instructions are executed by a computer, the computer executes the above-mentioned method of compressing test vectors.
  • the computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art.
  • the computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

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Abstract

A method for generating a compression test pattern, comprising: according to a decompression matrix corresponding to a chip under test, acquiring a first linear correlation matrix and a first maximal linearly independent system, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of said chip (S301); according to the first linear correlation matrix and/or the first maximal linearly independent system, filling first target bits in a first background pattern with an implicit value to obtain a second background pattern, the first target bits comprising all or some of independent bits in the first background pattern (S302); and generating a compression test pattern according to the second background pattern (S303).

Description

一种生成压缩测试向量的方法和装置A method and device for generating compressed test vectors 技术领域Technical Field
本申请实施例涉及集成电路领域，并且更具体地，涉及一种生成压缩测试向量的方法和装置。Embodiments of the present application relate to the field of integrated circuits, and more specifically, to a method and apparatus for generating a compressed test vector.
背景技术Background technique
在芯片测试过程中，需要采用测试向量对芯片进行测试，随着芯片集成度和复杂度的不断提高，衍生出了一种生成压缩测试向量的技术，即测试压缩技术。During the chip testing process, test vectors are needed to test the chip. With the continuous improvement of chip integration and complexity, a technology for generating compressed test vectors, namely test compression technology, has been derived.
然而，在测试向量生成流程中采用测试压缩技术会带来很多额外的软件求解功耗及自动测试向量生成(automatic test pattern generation，ATPG)工具的性能问题。在测试向量生成过程中，通常基本采用向量压实技术，即首先ATPG工具生成故障检测激励然后使用压缩增量求解的方案。对于线性压缩-解压缩器，随着向量压实的进行，根据线性相关性，压缩器中的隐含值越来越多，这会导致向量压实成功率降低，导致较多的测试向量数；同时求解不成功的故障检测激励需要在之后的向量压实过程中重新生成，这也引入大量的软件功耗。通常采用的高斯消元技术会计算无关位上的压缩隐含值，并更新到向量压实的背景中，提升向量压实成功率。但是高斯消元技术计算功耗较大，导致生成压缩测试向量的流程的效率是较低的。However, the use of test compression technology in the test vector generation process will bring many additional software solution power consumption and automatic test pattern generation (ATPG) tool performance issues. In the test vector generation process, vector compaction technology is usually basically used, that is, the ATPG tool first generates fault detection stimuli and then uses the compressed increment solution solution. For a linear compressor-decompressor, as the vector compaction proceeds, according to the linear correlation, the implicit values in the compressor increase, which will lead to a decrease in the success rate of vector compaction and a large number of test vectors; at the same time, the unsuccessful fault detection stimuli need to be regenerated in the subsequent vector compaction process, which also introduces a lot of software power consumption. The commonly used Gaussian elimination technology calculates the compressed implicit values on the irrelevant bits and updates them to the background of vector compaction to improve the success rate of vector compaction. However, the Gaussian elimination technology consumes a lot of power, resulting in a low efficiency in the process of generating compressed test vectors.
发明内容Summary of the invention
本申请实施例提供一种生成压缩测试向量的方法和装置，能够在增加测试向量的合并成功率的同时，极大地降低测试向量生成功耗，提升生成压缩测试向量的效率。The embodiments of the present application provide a method and device for generating compressed test vectors, which can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors while increasing the success rate of test vector merging.
第一方面，提供了一种生成压缩测试向量的方法，包括：根据待测芯片对应的解压缩矩阵，获取第一线性相关矩阵和第一极大无关组，其中，所述解压缩矩阵为所述待测芯片的解压缩电路结构对应的矩阵；根据所述第一线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，所述第一目标位包括所述第一背景向量中的全部或部分无关位；根据所述第二背景向量，生成压缩测试向量。In a first aspect, a method for generating a compressed test vector is provided, comprising: obtaining a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; filling a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generating a compressed test vector according to the second background vector.
上述方法通过对第一背景向量填充隐含值，生成第二背景向量后，再生成压缩测试向量，即对第一背景向量进行了更新，从而避免了由于第一背景向量中由于压缩运算应该确定的值未被确定，导致的后续合并、压缩的冲突的问题，能够在增加测试向量的合并成功率的同时，极大地降低测试向量生成功耗，提升了生成压缩测试向量的效率。The above method generates a compressed test vector after filling the first background vector with an implicit value, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined. While increasing the success rate of test vector merging, it can greatly reduce the power consumption of test vector generation and improve the efficiency of generating compressed test vectors.
结合第一方面，在第一方面的某些实现方式中，所述根据第一线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，包括：根据所述第一线性相关矩阵和所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为第二线性相关矩阵；根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。In combination with the first aspect, in certain implementations of the first aspect, filling the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being the second linear correlation matrix; and filling the first target bit with an implicit value according to the first target bit information to obtain a second background vector.
通过使用线性相关矩阵来确定哪些无关位上需要填充隐含值，而线性相关矩阵可以根据解压缩矩阵的原始线性相关矩阵进行更新，可以灵活地实现动态地隐含值的填充，提升了生成压缩测试向量的效率。By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.
结合第一方面，在第一方面的某些实现方式中，所述根据所述第一线性相关矩阵和所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为第二线性相关矩阵，包括：根据所述解压缩矩阵，获取所述第一背景向量对应的第一线性方程组的系数矩阵的第二极大无关组，所述第一线性方程组包括所述第一背景向量对应的解压缩方程；根据所述第一极大无关组，向所述第二极大无关组中添加所述第二极大无关组的正交补，以获取第三极大无关组；根据所述第三极大无关组、所述第一极大无关组和所述第一线性相关矩阵，确定所述第二线性相关矩阵。In combination with the first aspect, in certain implementations of the first aspect, the first target bit information indicating the first target bit is determined based on the first linear correlation matrix and the first maximally irrelevant group, and the first target bit information is a second linear correlation matrix, including: according to the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; according to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
通过使用线性相关矩阵来确定哪些无关位上需要填充隐含值，而线性相关矩阵可以根据解压缩矩阵的原始线性相关矩阵以及需要填充的背景向量进行更新，可以灵活地实现动态地隐含值的填充，提升了生成压缩测试向量的效率。By using a linear correlation matrix to determine which irrelevant bits need to be filled with implicit values, and the linear correlation matrix can be updated according to the original linear correlation matrix of the decompressed matrix and the background vector that needs to be filled, the filling of implicit values can be flexibly implemented dynamically, thereby improving the efficiency of generating compressed test vectors.
结合第一方面，在第一方面的某些实现方式中，所述根据所述第一目标位信息，在所述第一目标位中填充隐含值，包括：根据所述第二线性相关矩阵中的元素是否为1，确定所述第一目标位的位置，所述第一目标位中的所述无关位与所述第二线性相关矩阵中的所述元素一一对应；根据解压缩矩阵和所述第一背景向量，向确定的所述第一目标位的位置中填充隐含值。In combination with the first aspect, in certain implementations of the first aspect, filling the first target bit with an implicit value based on the first target bit information includes: determining the position of the first target bit based on whether the elements in the second linear correlation matrix are 1, the irrelevant bits in the first target bit corresponding one-to-one to the elements in the second linear correlation matrix; and filling the implicit value into the determined position of the first target bit based on the decompression matrix and the first background vector.
结合第一方面，在第一方面的某些实现方式中，所述根据第一所述线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，包括：根据所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为所述第一背景向量中的目标列向量区间；根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。In combination with the first aspect, in certain implementations of the first aspect, filling an implicit value into the first target bit in the first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector includes: determining first target bit information indicating the first target bit according to the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.
通过确定目标列向量区间，对背景向量中的部分列向量进行填充，实现了背景向量的更新，避免了后续部分冲突问题，在兼顾软件功耗的同时，提升了生成压缩测试向量的效率。By determining the target column vector interval and filling some column vectors in the background vector, the background vector is updated, and subsequent partial conflict problems are avoided. While taking into account the software power consumption, the efficiency of generating compressed test vectors is improved.
结合第一方面，在第一方面的某些实现方式中，所述第一背景向量包括至少一个列向量，所述第一极大无关组与所述列向量一一对应，所述根据所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，包括：根据多个所述第一极大无关组的秩，确定所述目标列向量区间，所述目标列向量区间包括连续的至少一个列向量。In combination with the first aspect, in certain implementations of the first aspect, the first background vector includes at least one column vector, the first maximally irrelevant group corresponds one-to-one to the column vector, and determining the first target bit information indicating the first target bit based on the first maximally irrelevant group includes: determining the target column vector interval based on the ranks of multiple of the first maximally irrelevant groups, the target column vector interval including at least one continuous column vector.
结合第一方面，在第一方面的某些实现方式中，所述根据多个所述第一极大无关组的秩，确定所述目标列向量区间，包括：根据所述解压缩矩阵和所述第一背景向量，获取至少一个第二线性方程组，所述第二线性方程组包括所述第一背景向量的解压缩方程，所述第二线性方程组与所述第一背景向量中的连续列向量区间一一对应；根据所述至少一个第二线性方程组，确定至少一个第一列向量区间，所述第一列向量区间对应的第二线性方程组的线性无关方程的个数大于第一阈值；根据所述至少一个第一列向量区间，确定第二列向量区间，所述第二列向量区间为所述至少一个第一列向量区间中包括的列向量数量最多的列向量区间；根据所述第二列向量区间，确定所述目标列向量区间，所述目标列向量区间包括所述第二列向量区间。In combination with the first aspect, in certain implementations of the first aspect, determining the target column vector interval based on the ranks of multiple first maximal independent groups includes: obtaining at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equations of the first background vector, and the second linear equation group corresponding one-to-one to continuous column vector intervals in the first background vector; determining at least one first column vector interval based on the at least one second linear equation group, the number of linear independent equations of the second linear equation group corresponding to the first column vector interval being greater than a first threshold; determining a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determining the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.
通过选取对应的线性无关方程的个数较多的列向量空间，能够尽可能的填充多的隐含值，避免了大规模的冲突问题，提升了生成压缩测试向量效率。By selecting a column vector space with a large number of corresponding linearly independent equations, as many implicit values as possible can be filled, avoiding large-scale conflict problems and improving the efficiency of generating compressed test vectors.
结合第一方面，在第一方面的某些实现方式中，所述根据所述第二列向量区间，确定所述目标列向量区间，包括：确定所述第二列向量区间对应的至少一个所述第一极大无关组的秩为第一数值；判断所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数是否等于所述第一数值；根据判断结果，更新所述第二列向量区间为第三列向量区间；确定第四列向量区间对应的至少一个所述第一极大无关组的秩与所述第四列向量区间对应的所述第二线性方程组的线性无关方程的个数相等，所述第四列向量区间为所述第三列向量区间的邻近列向量区间；确定所述目标列向量区间为所述第三列向量区间和所述第四列向量区间的合集。In combination with the first aspect, in certain implementations of the first aspect, determining the target column vector interval based on the second column vector interval includes: determining that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; judging whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; updating the second column vector interval to a third column vector interval based on the judgment result; determining that the rank of at least one of the first maximally irrelevant groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; and determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.
结合第一方面，在第一方面的某些实现方式中，所述根据判断结果，更新所述第二列向量区间为第三列向量区间，包括：当所述判断结果为所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数不等于所述第一数值时，确定所述线性无关方程中部分常数项的值，以使得所述第二列向量区间更新为所述第三列向量区间，所述第三列向量区间对应的所述第二线性方程组的线性无关方程的个数等于所述第一数值。In combination with the first aspect, in certain implementations of the first aspect, updating the second column vector interval to a third column vector interval based on the judgment result includes: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determining the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
结合第一方面，在第一方面的某些实现方式中，所述根据所述第一目标位信息，在所述第一目标位中填充隐含值，包括：根据所述目标列向量区间和所述解压缩矩阵，计算所述目标列向量区间中的无关位的隐含值；将所述隐含值填充至所述第一目标位中。In combination with the first aspect, in certain implementations of the first aspect, filling the first target bit with an implicit value based on the first target bit information includes: calculating the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and filling the implicit value into the first target bit.
结合第一方面，在第一方面的某些实现方式中，所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵的矩阵块行相对应；或者，所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵相对应。In combination with the first aspect, in certain implementations of the first aspect, the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.
第二方面，提供了一种生成压缩测试向量的装置，所述装置包括处理模块，所述处理模块用于：根据待测芯片对应的解压缩矩阵，获取第一线性相关矩阵和第一极大无关组，其中，所述解压缩矩阵为所述待测芯片的解压缩电路结构对应的矩阵；根据所述第一线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，所述第一目标位包括所述第一背景向量中的全部或部分无关位；根据所述第二背景向量，生成压缩测试向量。In a second aspect, a device for generating a compressed test vector is provided, the device comprising a processing module, the processing module being used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to a decompression matrix corresponding to a chip under test, wherein the decompression matrix is a matrix corresponding to a decompression circuit structure of the chip under test; fill a first target bit in a first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, the first target bit including all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.
结合第二方面，在第二方面的某些实现方式中，所述处理模块具体用于：根据所述第一线性相关矩阵和所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为第二线性相关矩阵；根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。In combination with the second aspect, in certain implementations of the second aspect, the processing module is specifically used to: determine first target bit information indicating a first target bit based on the first linear correlation matrix and the first maximally irrelevant group, the first target bit information being a second linear correlation matrix; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.
结合第二方面，在第二方面的某些实现方式中，所述处理单元还具体用于：根据所述解压缩矩阵，获取所述第一背景向量对应的第一线性方程组的系数矩阵的第二极大无关组，所述第一线性方程组包括所述第一背景向量对应的解压缩方程；根据所述第一极大无关组，向所述第二极大无关组中添加所述第二极大无关组的正交补，以获取第三极大无关组；根据所述第三极大无关组、所述第一极大无关组和所述第一线性相关矩阵，确定所述第二线性相关矩阵。In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: obtain a second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector according to the decompression matrix, the first linear equation group including the decompression equation corresponding to the first background vector; add the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group according to the first maximally irrelevant group to obtain a third maximally irrelevant group; determine the second linear correlation matrix according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
结合第二方面，在第二方面的某些实现方式中，所述处理单元还具体用于：根据所述第二线性相关矩阵中的元素是否为1，确定所述第一目标位的位置，所述第一目标位中的 所述无关位与所述第二线性相关矩阵中的所述元素一一对应；根据解压缩矩阵和所述第一背景向量，向确定的所述第一目标位的位置中填充隐含值。In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: determine the position of the first target bit according to whether the elements in the second linear correlation matrix are 1, and the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix; fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.
结合第二方面，在第二方面的某些实现方式中，所述处理单元具体用于：根据所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为所述第一背景向量中的目标列向量区间；根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。In combination with the second aspect, in certain implementations of the second aspect, the processing unit is specifically used to: determine first target bit information indicating a first target bit based on the first maximally irrelevant group, the first target bit information being a target column vector interval in the first background vector; and fill an implicit value in the first target bit based on the first target bit information to obtain a second background vector.
结合第二方面，在第二方面的某些实现方式中，所述第一背景向量包括至少一个列向量，所述第一极大无关组与所述列向量一一对应，所述处理单元还具体用于：根据多个所述第一极大无关组的秩，确定所述目标列向量区间，所述目标列向量区间包括连续的至少一个列向量。In combination with the second aspect, in certain implementations of the second aspect, the first background vector includes at least one column vector, the first maximally irrelevant group corresponds one-to-one to the column vector, and the processing unit is further specifically used to: determine the target column vector interval based on the ranks of multiple first maximally irrelevant groups, and the target column vector interval includes at least one continuous column vector.
结合第二方面，在第二方面的某些实现方式中，所述处理单元还具体用于：根据所述解压缩矩阵和所述第一背景向量，获取至少一个第二线性方程组，所述第二线性方程组包括所述第一背景向量的解压缩方程，所述第二线性方程组与所述第一背景向量中的连续列向量区间一一对应；根据所述至少一个第二线性方程组，确定至少一个第一列向量区间，所述第一列向量区间对应的第二线性方程组的线性无关方程的个数大于第一阈值；根据所述至少一个第一列向量区间，确定第二列向量区间，所述第二列向量区间为所述至少一个第一列向量区间中包括的列向量数量最多的列向量区间；根据所述第二列向量区间，确定所述目标列向量区间，所述目标列向量区间包括所述第二列向量区间。In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: obtain at least one second linear equation group based on the decompression matrix and the first background vector, the second linear equation group including the decompression equation of the first background vector, and the second linear equation group corresponding one-to-one to the continuous column vector interval in the first background vector; determine at least one first column vector interval based on the at least one second linear equation group, the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; determine a second column vector interval based on the at least one first column vector interval, the second column vector interval being the column vector interval with the largest number of column vectors included in the at least one first column vector interval; determine the target column vector interval based on the second column vector interval, the target column vector interval including the second column vector interval.
结合第二方面，在第二方面的某些实现方式中，所述处理单元还具体用于：确定所述第二列向量区间对应的至少一个所述第一极大无关组的秩为第一数值；判断所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数是否等于所述第一数值；根据判断结果，更新所述第二列向量区间为第三列向量区间；确定第四列向量区间对应的至少一个所述第一极大无关组的秩与所述第四列向量区间对应的所述第二线性方程组的线性无关方程的个数相等，所述第四列向量区间为所述第三列向量区间的邻近列向量区间；确定所述目标列向量区间为所述第三列向量区间和所述第四列向量区间的合集。In combination with the second aspect, in certain implementations of the second aspect, the processing unit is further specifically used to: determine that the rank of at least one of the first maximally irrelevant groups corresponding to the second column vector interval is a first value; determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value; based on the judgment result, update the second column vector interval to the third column vector interval; determine that the rank of at least one of the first maximally irrelevant groups corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determine that the target column vector interval is the union of the third column vector interval and the fourth column vector interval.
结合第二方面，在第二方面的某些实现方式中，所述处理单元还用于：当所述判断结果为所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数不等于所述第一数值时，确定所述线性无关方程中部分常数项的值，以使得所述第二列向量区间更新为所述第三列向量区间，所述第三列向量区间对应的所述第二线性方程组的线性无关方程的个数等于所述第一数值。In combination with the second aspect, in certain implementations of the second aspect, the processing unit is also used to: when the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, determine the values of some constant terms in the linearly independent equations so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
结合第二方面，在第二方面的某些实现方式中，所述处理单元还用于：根据所述目标列向量区间和所述解压缩矩阵，计算所述目标列向量区间中的无关位的隐含值；将所述隐含值填充至所述第一目标位中。In combination with the second aspect, in certain implementations of the second aspect, the processing unit is also used to: calculate the implicit value of the irrelevant bits in the target column vector interval based on the target column vector interval and the decompression matrix; and fill the implicit value into the first target bit.
结合第二方面，在第二方面的某些实现方式中，所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵的矩阵块行相对应；或者，所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵相对应。In combination with the second aspect, in certain implementations of the second aspect, the product of the first linear correlation matrix and the first maximally independent group corresponds to a matrix block row of the decompressed matrix; or, the product of the first linear correlation matrix and the first maximally independent group corresponds to the decompressed matrix.
第三方面，提供了一种计算机程序产品，该计算机程序产品包括指令，当该指令在计算机上执行时，使得计算机执行上述第一方面或第一方面中任一实现方式中所述的方法。In a third aspect, a computer program product is provided, which includes instructions. When the instructions are executed on a computer, the computer executes the method described in the first aspect or any implementation of the first aspect.
第四方面，提供了一种生成压缩测试向量的装置，包括处理器和存储器，所述存储器 用于存储程序，所述处理器用于从所述存储器中调用并运行所述程序，以执行上述第一方面或第一方面的任一可能的实施方式中的方法。In a fourth aspect, a device for generating a compressed test vector is provided, comprising a processor and a memory, wherein the memory is used to store a program, and the processor is used to call and run the program from the memory to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.
第五方面，提供了一种计算机可读存储介质，包括计算机程序，当所述计算机程序在计算机上运行时，使得所述计算机执行上述第一方面或第一方面的任一可能的实施方式中的测试控制软件的方法。In a fifth aspect, a computer-readable storage medium is provided, comprising a computer program, which, when executed on a computer, enables the computer to execute the method for testing control software in the first aspect or any possible implementation of the first aspect.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是适用于本申请实施例的芯片设计与制造的过程的示意性框图。FIG. 1 is a schematic block diagram of a chip design and manufacturing process applicable to an embodiment of the present application.
图2是适用于本申请实施例的一种压缩测试向量的生成流程的示意性框图。FIG. 2 is a schematic block diagram of a process for generating a compressed test vector applicable to an embodiment of the present application.
图3是本申请实施例提供的一种生成压缩测试向量的方法示意图。FIG3 is a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application.
图4是本申请实施例提供的另一种生成压缩测试向量的示例性方法示意图。FIG. 4 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.
图5是本申请实施例提供的另一种生成压缩测试向量的示例性方法示意图。FIG. 5 is a schematic diagram of another exemplary method for generating a compressed test vector provided in an embodiment of the present application.
图6是本申请提供的一个实施例的生成压缩测试向量的装置的示意性框图。FIG. 6 is a schematic block diagram of an apparatus for generating a compressed test vector according to an embodiment of the present application.
图7是本申请提供的一个实施例的压缩测试向量的装置的硬件结构示意图。FIG. 7 is a schematic diagram of the hardware structure of an apparatus for compressing test vectors according to an embodiment of the present application.
具体实施方式Detailed ways
下面将结合附图，对本申请实施例中的技术方案进行描述。The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.
芯片，又可以称为集成电路(integrated circuit，IC)，或者可以理解为集成电路的载体，通常是一种将电路小型化的方式，并时常制造在半导体晶圆表面。如图1所示，芯片设计与制造的过程100通常可以分为设计部分101、制造部分102、封装测试部分103三个部分。其中，在芯片的设计、制造和封装过程中不可避免的会因为各种原因(例如工艺、材料等)导致芯片存在缺陷，这种缺陷会导致芯片无法正常工作。此时，就需要进行芯片测试。Chips, which can also be called integrated circuits (ICs), or can be understood as the carrier of integrated circuits, are usually a way to miniaturize circuits and are often manufactured on the surface of semiconductor wafers. As shown in FIG1 , the process 100 of chip design and manufacturing can usually be divided into three parts: design part 101, manufacturing part 102, and packaging and testing part 103. Among them, in the process of chip design, manufacturing and packaging, it is inevitable that the chip will have defects due to various reasons (such as process, materials, etc.), and such defects will cause the chip to fail to work properly. At this time, chip testing is required.
芯片测试的主要任务就是挑选出有缺陷的芯片。通常，可以在芯片中添加可测试性设计(design for testability，DFT)结构，如扫描链(scan chain)等等。可以理解为将一些特殊结构在设计阶段植入电路，以便设计完成后进行测试，通过添加扫描链，芯片的内部时序单元可以更方便的由外部控制。The main task of chip testing is to pick out defective chips. Usually, design for testability (DFT) structures can be added to the chip, such as scan chains, etc. It can be understood as implanting some special structures into the circuit during the design stage so that testing can be performed after the design is completed. By adding scan chains, the internal timing units of the chip can be more conveniently controlled by the outside.
具体芯片测试的流程主要包括：首先，通过自动测试向量生成(automatic test pattern generation，ATPG)工具生成测试向量(test patterns)；然后通过自动测试设备(automatic test equipment，ATE)将测试向量输入至被测芯片中；最后，对比被测芯片的测试响应(test response)于预期响应是否一致，即可获知芯片是否存在缺陷。The specific chip testing process mainly includes: first, generate test patterns through automatic test pattern generation (ATPG) tools; then input the test patterns into the chip under test through automatic test equipment (ATE); finally, compare the test response of the chip under test with the expected response to see if it is consistent, to know whether the chip has defects.
然而，随着芯片集成度和复杂度的不断提高，所需的测试向量的数据规模也随之快速增长，导致芯片测试的时间快速增加，成本也快速增加。为了降低芯片测试成本，减少芯片测试时间，可以对测试向量进行压缩，即测试压缩技术，如图1所示，测试压缩技术用于芯片的封装测试部分。However, as the integration and complexity of chips continue to increase, the data size of the required test vectors also grows rapidly, resulting in a rapid increase in chip testing time and cost. In order to reduce chip testing costs and reduce chip testing time, the test vectors can be compressed, that is, test compression technology. As shown in Figure 1, test compression technology is used in the packaging test part of the chip.
在测试压缩技术中，压缩测试向量的生成流程可以是：(1)ATPG工具基于芯片可能出现的故障(如故障列表(fault list)中的故障)进行建模，生成故障检测激励，故障检测激励中包括一个或多个比特位，该比特位包括固定位和无关位，固定位填充的数值为有效值(specified bit)，无关位填充的数值为无关值(don’t care bit)，其中有效值可以 理解为故障检测激励中的固定数值，用于检测对应的故障，无关值可以理解为故障检测激励中可以任意设定的值，例如可以是0和1中的任意值。例如，如图2所示，首先在步骤S201中生成n个故障检测激励(a 1，a 2，……，a n)，其中每一个方框表示一个比特位，有图案填充的表示该比特位为固定位，无图案填充的表示该比特位为无关位。为便于理解，在图2所示的每个故障检测激励中，仅包括10个比特位，在实际生成的故障检测激励中，包括的比特位可以是百万量级的，数据规模较大。应理解，一个故障检测激励对应于一个故障； In the test compression technology, the generation process of the compressed test vector can be: (1) The ATPG tool models the possible faults of the chip (such as the faults in the fault list) and generates a fault detection stimulus. The fault detection stimulus includes one or more bits, which include fixed bits and don't care bits. The value filled with the fixed bit is a valid value (specified bit), and the value filled with the don't care bit is a don't care value (don't care bit). The valid value can be understood as a fixed value in the fault detection stimulus, which is used to detect the corresponding fault. The don't care value can be understood as a value that can be arbitrarily set in the fault detection stimulus, for example, it can be any value between 0 and 1. For example, as shown in FIG2, first, in step S201, n fault detection stimuli ( a1 , a2 , ..., an ) are generated, wherein each box represents a bit, and a box filled with a pattern indicates that the bit is a fixed bit, and a box without a pattern fill indicates that the bit is a don't care bit. For ease of understanding, each fault detection stimulus shown in FIG2 includes only 10 bits. In the actual generated fault detection stimulus, the bits included can be in the millions, and the data scale is relatively large. It should be understood that one fault detection stimulus corresponds to one fault;
(2)进行静态压实(static compaction)流程：在生成一定数量的故障检测激励后，将该一定数量的故障检测激励中全部或部分故障检测激励进行合并、压缩，以获得一个压缩背景向量，例如，如图2所示，在步骤S202中，将n个故障检测激励(a 1，a 2，……，a n)逐次进行合并、压缩，即将n个故障检测激励中的两个故障检测激励进行合并，获得一个背景向量(background merged cube)，然后进行压缩，获得一个压缩背景向量，确保合并后的故障检测激励可以压缩成功，接着再向合并两个故障检测激励获得的背景向量中再增加一个故障检测激励，即将三个故障检测激励进行合并、压缩，以此类推，经过多次合并、压缩，最终可以将n个故障检测激励进行合并，获得一个背景向量A，然后将该背景向量压缩，获得一个压缩背景向量A’。应理解，背景向量A包括的元素数量与一个故障检测激励中包括的元素数量相同，压缩背景向量A’中包括的元素数量小于背景向量A中包括的元素数量。还应理解，合并是将多个故障检测激励并为一个，即合并是减少故障检测激励的个数，压缩是将故障检测激励的长度缩短，即压缩是减少故障检测激励中元素的个数，并且在合并的过程中同时伴随着压缩，或者可以称为合并的过程中同时进行增量压缩，即每多合并一个故障检测激励，就要检查是否可以成功的进行增量压缩，以确保合并后的状态可以压缩成功； (2) Performing a static compaction process: After generating a certain number of fault detection stimuli, all or part of the fault detection stimuli in the certain number of fault detection stimuli are merged and compressed to obtain a compressed background vector. For example, as shown in FIG2 , in step S202 , n fault detection stimuli (a 1 , a 2 , ..., a n ) are merged and compressed one by one, that is, two fault detection stimuli in the n fault detection stimuli are merged to obtain a background vector (background merged cube), and then compressed to obtain a compressed background vector, ensuring that the merged fault detection stimuli can be compressed successfully, and then adding another fault detection stimuli to the background vector obtained by merging the two fault detection stimuli, that is, merging and compressing the three fault detection stimuli, and so on. After multiple merging and compression, the n fault detection stimuli can finally be merged to obtain a background vector A, and then the background vector is compressed to obtain a compressed background vector A'. It should be understood that the number of elements included in the background vector A is the same as the number of elements included in a fault detection stimuli, and the number of elements included in the compressed background vector A' is less than the number of elements included in the background vector A. It should also be understood that merging is to merge multiple fault detection stimuli into one, that is, merging is to reduce the number of fault detection stimuli, and compression is to shorten the length of the fault detection stimuli, that is, compression is to reduce the number of elements in the fault detection stimuli, and the merging process is accompanied by compression, or it can be called incremental compression during the merging process, that is, each time a fault detection stimulus is merged, it is necessary to check whether incremental compression can be successfully performed to ensure that the merged state can be compressed successfully;
(3)进行动态压实(dynamic compaction)流程：基于压缩背景向量，生成故障检测激励，再将生成的故障检测激励增量合并、压缩至压缩背景向量中，生成一条压缩测试向量(compressed test pattern)，例如，如图2所示，基于背景向量A，生成故障检测激励b 1，然后将A和b 1合并、压缩，压缩成功后，再基于A和b 1合并生成的背景向量生成故障检测激励b 2，然后将该A和b 1合并生成的背景向量和b 2合并、压缩，压缩成功后，再基于合并b 2后生成的背景向量生成故障检测激励b 3，以此类推，直至生成故障检测激励bm，并最终获得A和m个故障检测激励(b 1，b 2，……，b m)合并后的背景向量B，背景向量B压缩后获得压缩测试向量B’。后续，可以将压缩测试向量存储在ATE中，ATE将压缩测试向量注入被测芯片后，压缩测试向量经过被测芯片上的解压缩电路进行解压缩后，再输入被测芯片中的被测电路，例如可以将上述压缩测试向量B’注入被测芯片中，然后经过解压缩电路，输入被测电路中的即可还原为上述n个故障检测激励(a 1，a 2，……，a n)以及上述m个故障检测激励(b 1，b 2，……，b m)的合并向量，即合并后的背景向量B。 (3) Performing a dynamic compaction process: Based on the compressed background vector, a fault detection stimulus is generated, and then the generated fault detection stimulus increments are merged and compressed into the compressed background vector to generate a compressed test pattern. For example, as shown in FIG2 , based on the background vector A, a fault detection stimulus b1 is generated, and then A and b1 are merged and compressed. After the compression is successful, a fault detection stimulus b2 is generated based on the background vector generated by merging A and b1 . Then the background vector generated by merging A and b1 and b2 are merged and compressed. After the compression is successful, a fault detection stimulus b3 is generated based on the background vector generated by merging b2 . This process is repeated until a fault detection stimulus bm is generated. Finally, a background vector B is obtained by merging A and m fault detection stimuli ( b1 , b2 , ..., bm ). After the background vector B is compressed, a compressed test vector B' is obtained. Subsequently, the compressed test vector may be stored in ATE. After ATE injects the compressed test vector into the chip under test, the compressed test vector is decompressed by a decompression circuit on the chip under test and then input into the circuit under test in the chip under test. For example, the compressed test vector B' may be injected into the chip under test and then input into the circuit under test through a decompression circuit to be restored to a merged vector of the n fault detection stimuli ( a1 , a2 , ..., an ) and the m fault detection stimuli ( b1 , b2 , ..., bm ), that is, a merged background vector B.
应理解，压缩测试向量也可以称为压缩解(compressed seed)。还应理解，上述压缩测试向量的生成流程可以由ATPG工具进行。还应理解，在上述压缩测试向量生成流程中，故障检测激励合并获得的向量可以称为背景向量，在进行进一步压缩后，获得的向量可以称为压缩背景向量，最终获得向量可以称为压缩测试向量，即压缩背景向量合并、压缩最 后一个故障检测激励后，获得的向量可以称为压缩测试向量。It should be understood that the compressed test vector may also be referred to as a compressed seed. It should also be understood that the generation process of the compressed test vector may be performed by an ATPG tool. It should also be understood that in the generation process of the compressed test vector, the vector obtained by merging the fault detection stimulus may be referred to as a background vector, and after further compression, the vector obtained may be referred to as a compressed background vector, and the vector finally obtained may be referred to as a compressed test vector, that is, after merging the compressed background vector and compressing the last fault detection stimulus, the vector obtained may be referred to as a compressed test vector.
值得注意的是，在上述步骤(2)和(3)的静态压实流程和动态压实流程中，生成的故障检测激励在合并、压缩生成压缩背景向量或压缩测试向量时，可能会由于压缩运算，导致用于合并、压缩的故障检测激励需要满足压缩条件，否则生成的故障检测激励无法合并、压缩至背景向量中。It is worth noting that in the static compaction process and dynamic compaction process of the above steps (2) and (3), when the generated fault detection stimuli are merged and compressed to generate a compressed background vector or a compressed test vector, due to the compression operation, the fault detection stimuli used for merging and compression need to meet the compression conditions, otherwise the generated fault detection stimuli cannot be merged and compressed into the background vector.
或者换句话说，在上述步骤(3)的动态压实流程中，ATPG工具生成的故障检测激励中的固定位对应于背景向量压缩前的无关位，即对应于合并故障检测激励获得的背景向量的无关位，而背景向量压缩前的无关位的填充值可能会由于压缩运算，导致背景向量压缩前的无关位的填充值确定了下来，此时背景向量压缩前的无关位的填充值可以称为隐含值(implied value)，当该无关位填充的值与故障检测激励中的固定位填充的值不同时，生成的故障检测激励将无法合并压缩至背景向量中，即此时产生了冲突。In other words, in the dynamic compaction process of step (3) above, the fixed bits in the fault detection stimulus generated by the ATPG tool correspond to the don't care bits before the background vector is compressed, that is, they correspond to the don't care bits of the background vector obtained by merging the fault detection stimulus. The fill value of the don't care bits before the background vector is compressed may be determined due to the compression operation. At this time, the fill value of the don't care bits before the background vector is compressed can be called an implied value. When the fill value of the don't care bits is different from the fill value of the fixed bits in the fault detection stimulus, the generated fault detection stimulus cannot be merged and compressed into the background vector, that is, a conflict occurs at this time.
或者再换句话说，在上述步骤(3)的动态压实流程中，ATPG工具生成的故障检测激励可能无法满足压缩运算，因此不能增量合并到背景向量中，由此产生了冲突并增加了动态压实的功耗。Or in other words, in the dynamic compaction process of step (3) above, the fault detection stimulus generated by the ATPG tool may not satisfy the compression operation and therefore cannot be incrementally merged into the background vector, thereby causing a conflict and increasing the power consumption of dynamic compaction.
具体地，上述被测电路中还原出的背景向量B对应于被测电路中的一条扫描链，一条扫描链包括至少一个扫描单元(scan cell)，每个扫描单元的值为背景向量B中的一个值，即向量中的一个元素，而输入被测电路的向量为压缩测试向量B’，若将压缩测试向量B’中的每个压缩值看作一个自由变量，由于压缩运算导致背景向量B中的每个值都可以由压缩测试向量B’中的部分压缩值或全部压缩值线性表示，即每一个扫描单元的值都可以由输入的自由变量线性表示，且扫描单元的数目远大于自由变量的数目。因此，多个扫描单元对应的多个方程之间含有大量的线性相关性，即很多扫描单元上的值可以由其他部分扫描单元上的值线性表示。Specifically, the background vector B restored in the above-mentioned circuit under test corresponds to a scan chain in the circuit under test. A scan chain includes at least one scan cell. The value of each scan cell is a value in the background vector B, that is, an element in the vector. The vector input to the circuit under test is the compressed test vector B'. If each compressed value in the compressed test vector B' is regarded as a free variable, each value in the background vector B can be linearly represented by part of the compressed value or all of the compressed value in the compressed test vector B' due to the compression operation, that is, the value of each scan cell can be linearly represented by the input free variable, and the number of scan cells is much larger than the number of free variables. Therefore, there are a lot of linear correlations between the multiple equations corresponding to the multiple scan cells, that is, the values on many scan cells can be linearly represented by the values on other scan cells.
在动态压实流程生成的背景向量中，只有少部分值是有效值，其余大部分值是无关值，但是随着背景向量中有效值的数量增多，越来越多的无关值被确定了下来，在基于当前的背景向量生成故障检测激励时，若ATPG工具不知道哪些无关值被确定了下来将会导致，故障检测激励无法被压缩至背景向量中，即压缩增量求解不成功，此时就产生了冲突，并增加了动态压实的功耗。在高压缩比场景下，随着故障检测激励的合并、压缩，无关值也越来越多的被确定下来，即隐含值的数量也随之增加，此时ATPG工具生成的故障检测激励中的有效值与压缩产生的隐含值之间的冲突会大量发生。In the background vector generated by the dynamic compaction process, only a small number of values are valid values, and most of the remaining values are irrelevant values. However, as the number of valid values in the background vector increases, more and more irrelevant values are determined. When generating fault detection stimuli based on the current background vector, if the ATPG tool does not know which irrelevant values have been determined, the fault detection stimuli cannot be compressed into the background vector, that is, the compression increment solution is unsuccessful, and conflicts occur at this time, which increases the power consumption of dynamic compaction. In high compression ratio scenarios, as the fault detection stimuli are merged and compressed, more and more irrelevant values are determined, that is, the number of implicit values also increases. At this time, conflicts between the valid values in the fault detection stimuli generated by the ATPG tool and the implicit values generated by compression will occur in large numbers.
通常，为了减少上述动态压实流程中冲突的产生，会在上述步骤(2)之后，步骤(3)之前，对整个背景向量的无关位填充值对应的方程，即扫描单元填充的无关值对应的输入自由变量的线性方程，进行高斯消元计算，以检查当前背景向量中哪些无关值为隐含值，并计算该值，然而该方式计算规模较大，且仅在静态压实流程与动态压实流程之间进行一次，对于动态压实流程中产生的冲突则无法消除，因此，通过该方式生成压缩测试向量的效率较低。鉴于此，本申请实施例提出了一种生成测试向量的方法，能够在增加测试向量的合并成功率的同时，极大地降低测试向量生成功耗。Usually, in order to reduce the generation of conflicts in the above-mentioned dynamic compaction process, after the above-mentioned step (2) and before step (3), Gaussian elimination calculation is performed on the equation corresponding to the irrelevant bit filling value of the entire background vector, that is, the linear equation of the input free variable corresponding to the irrelevant value filled by the scanning unit, to check which irrelevant values in the current background vector are implicit values and calculate the value. However, this method has a large calculation scale and is only performed once between the static compaction process and the dynamic compaction process. The conflicts generated in the dynamic compaction process cannot be eliminated. Therefore, the efficiency of generating compressed test vectors in this way is low. In view of this, an embodiment of the present application proposes a method for generating test vectors, which can greatly reduce the power consumption of test vector generation while increasing the success rate of test vector merging.
首先，为便于理解本申请，对本申请实施例中所涉及的部分术语进行说明。First, to facilitate understanding of the present application, some terms involved in the embodiments of the present application are explained.
矩阵(matrix)：是一个按照长方阵列排列的复数或实数集合。例如，由m×n个数排成的m行n列的数表称为m行n列的矩阵，简称m×n矩阵。行数和列数都等于n的矩阵 称为n阶矩阵，或n阶方阵。在本申请实施例中，涉及的测试向量在通过矩阵表示时，矩阵元素主要包括0和1。Matrix: A set of complex or real numbers arranged in a rectangular array. For example, a table of m×n numbers with m rows and n columns is called a matrix of m rows and n columns, or m×n matrix for short. A matrix with n rows and columns is called an n-order matrix, or an n-order square matrix. In the embodiments of the present application, when the test vectors involved are represented by matrices, the matrix elements mainly include 0 and 1.
向量组：由若干同维数的列向量或同维数的行向量组成的集合。可以将矩阵理解为由向量组构成。Vector group: A set of column vectors or row vectors of the same dimension. A matrix can be understood as consisting of vector groups.
极大无关组：一般是指极大线性无关组，是在线性空间中拥有向量个数最多的线性无关向量组，例如，其定义可以为：设有向量组A：α1，α2，α3，…,αs，若A中能选出r个向量α1，α2，…,αr，满足向量组A0：α1，α2，…,αr线性无关，且向量组A中任意一个向量都可以由向量组A0中的若干向量线性表示，则称向量组A0是向量组A的一个极大线性无关组，简称为极大无关组。Maximal independent group: generally refers to the maximal linearly independent group, which is the linearly independent vector group with the largest number of vectors in the linear space. For example, its definition can be: suppose there is a vector group A: α1, α2, α3, …, αs, if r vectors α1, α2, …, αr can be selected from A, satisfying the vector group A0: α1, α2, …, αr are linearly independent, and any vector in the vector group A can be linearly represented by several vectors in the vector group A0, then the vector group A0 is called a maximal linearly independent group of the vector group A, abbreviated as the maximal independent group.
秩：一个矩阵的秩是其非零子式的最高阶数，一个向量组的秩则是其极大无关组所含的向量个数。对于一个矩阵，当其非零子式的最高阶数等于该矩阵的阶数时，称该矩阵满秩。而对于一个向量组，当极大无关组所含的向量个数等于该向量组的个数时，称该向量组满秩。Rank: The rank of a matrix is the highest order of its non-zero minors, and the rank of a vector group is the number of vectors contained in its maximal independent group. For a matrix, when the highest order of its non-zero minors is equal to the order of the matrix, the matrix is said to be full rank. For a vector group, when the number of vectors contained in the maximal independent group is equal to the number of vector groups, the vector group is said to be full rank.
图3示出了本申请实施例提供的一种生成压缩测试向量的方法示意图。具体地，该方法300包括：FIG3 shows a schematic diagram of a method for generating a compressed test vector provided in an embodiment of the present application. Specifically, the method 300 includes:
S301，根据待测芯片对应的解压缩矩阵，获取第一线性相关矩阵和第一极大无关组，其中，解压缩矩阵为待测芯片的解压缩电路结构对应的矩阵。S301, obtaining a first linear correlation matrix and a first maximally independent group according to a decompression matrix corresponding to the chip under test, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test.
在本申请实施例中，待测芯片为压缩测试向量用于测试的芯片，待测芯片中包括解压缩电路，解压缩电路可以将压缩测试向量解压缩。上述步骤S301可以由ATPG工具执行，ATPG工具可以获取待测芯片的解压缩电路结构，然后根据解压缩电路结构建模，提取解压缩矩阵。In the embodiment of the present application, the chip under test is a chip for testing with compressed test vectors, and the chip under test includes a decompression circuit, which can decompress the compressed test vectors. The above step S301 can be performed by an ATPG tool, which can obtain the decompression circuit structure of the chip under test, and then model according to the decompression circuit structure to extract the decompression matrix.
值得注意的是，解压缩电路结构为待测芯片的测试电路的解压缩电路结构，从而在ATPG工具生成故障检测激励，以及合并、压缩故障检测激励时，根据解压缩电路结构的相关特性对故障检测激励进行合并、压缩，便于解压缩电路后续可以完整地将合并、压缩后的故障检测激励解压缩出来，提升了芯片的测试效率。It is worth noting that the decompression circuit structure is the decompression circuit structure of the test circuit of the chip to be tested. Therefore, when the ATPG tool generates fault detection stimuli, and merges and compresses the fault detection stimuli, the fault detection stimuli are merged and compressed according to the relevant characteristics of the decompression circuit structure, so that the decompression circuit can subsequently completely decompress the merged and compressed fault detection stimuli, thereby improving the test efficiency of the chip.
在本申请实施例中，解压缩电路结构为基于线性的解压缩电路结构，例如解压缩电路结构包括环生成器(ring generator)和相移器(phase shifter)，从而根据环生成器以及相移器的映射关系，可以构建出解压缩矩阵。In an embodiment of the present application, the decompression circuit structure is a linear-based decompression circuit structure. For example, the decompression circuit structure includes a ring generator and a phase shifter, so that a decompression matrix can be constructed according to the mapping relationship between the ring generator and the phase shifter.
可选的，环生成器包括多个移位寄存器，环生成器对应的映射关系可以通过下列公式(1)表示：Optionally, the ring generator includes a plurality of shift registers, and the mapping relationship corresponding to the ring generator can be expressed by the following formula (1):
r t＝R fr t-1+R vx t    (1) r t = R fr t-1 + R v x t (1)
其中，r t表示t时刻移位寄存器的值，R f表示移位寄存器本身的反馈连接结构对应的线性矩阵，r t-1表示t-1时刻环生成器中移位寄存器的值，R v表示输入引脚与移位寄存器的连接结构对应的线性矩阵，x t表示第t次拍打注入的压缩值， Among them, r t represents the value of the shift register at time t, R f represents the linear matrix corresponding to the feedback connection structure of the shift register itself, r t-1 represents the value of the shift register in the ring generator at time t-1, R v represents the linear matrix corresponding to the connection structure between the input pin and the shift register, x t represents the compressed value injected by the tth tap,
可选的，相移器对应的线性矩阵为P，则t时刻环生成器包括的移位寄存器的值的移位值可以通过下列公式(2)表示：Optionally, the linear matrix corresponding to the phase shifter is P, and the shift value of the shift register included in the ring generator at time t can be expressed by the following formula (2):
b t-s＝Pr t-s,t>s    (2) b ts = Pr ts , t>s (2)
其中，b t-s表示移位寄存器的值的移位值，或者说b t-s表示合故障检测激励后获得的背 景向量，r t-s表示t-s时刻移位寄存器的值，s表示压缩测试向量(即压缩解)逐拍输入解压缩电路时的初始化拍打次数，或者说s表示压缩测试向量输入解压缩电路时的有效拍打之前的初始化拍打次数。 Among them, b ts represents the shift value of the shift register, or b ts represents the background vector obtained after the combined fault detection stimulus, r ts represents the value of the shift register at time ts, s represents the number of initialization taps when the compressed test vector (i.e., compressed solution) is input into the decompression circuit beat by beat, or s represents the number of initialization taps before the effective tap when the compressed test vector is input into the decompression circuit.
一种可能的实现方式中，根据上述公式(1)、(2)以及r 0＝0，可以获得下列公式解压缩映射公式(3)，该公式(3)的右端第一个矩阵即为解压缩矩阵，根据该公式(3)即可获得矩阵b与矩阵x的对应关系，即获得背景向量中的值与背景向量的压缩值的对应关系。 In a possible implementation, according to the above formulas (1), (2) and r 0 = 0, the following formula decompression mapping formula (3) can be obtained. The first matrix on the right side of the formula (3) is the decompression matrix. According to the formula (3), the corresponding relationship between the matrix b and the matrix x can be obtained, that is, the corresponding relationship between the value in the background vector and the compressed value of the background vector can be obtained.
Figure PCTCN2022123320-appb-000001
Figure PCTCN2022123320-appb-000001
即可以定义解压缩矩阵E为下列公式(4)：That is, the decompression matrix E can be defined as the following formula (4):
Figure PCTCN2022123320-appb-000002
Figure PCTCN2022123320-appb-000002
在本申请实施例中，可以将解压缩矩阵分解为第一线性相关矩阵和第一极大无关组，例如可以根据解压缩矩阵的性质，层次性的构建第一线性相关矩阵和第一极大无关组，第一线性相关矩阵也可以称为第一线性相关表。In an embodiment of the present application, the decompressed matrix can be decomposed into a first linear correlation matrix and a first maximally independent group. For example, according to the properties of the decompressed matrix, the first linear correlation matrix and the first maximally independent group can be hierarchically constructed. The first linear correlation matrix can also be called a first linear correlation table.
一种可能的实现方式中，第一线性相关矩阵和第一极大无关组的乘积与解压缩矩阵的矩阵块行相对应。应理解，两者乘积与解压缩矩阵的矩阵块行相对应可以是指乘积与矩阵块行相同，也可以是指乘积与矩阵块行的偏差在预设范围内，还可以是指乘积再乘以某个系数后与矩阵块行相同，本申请对此不作限定。可选的，可以根据解压缩矩阵的矩阵块行，例如E i，计算第一线性相关矩阵和第一极大无关组，例如D i和C i，第一线性相关矩阵乘以第一极大无关组等于解压缩矩阵的矩阵块行，即有等式E i＝D i·C i。值得注意的是，一个解压缩矩阵的矩阵块行对应于一个背景向量的列向量，例如b i，一个列向量也可以称为一个测试周期(cycle)。即可以获取一个测试周期内的极大无关组和线性相关矩阵。 In a possible implementation, the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the matrix block row of the decompressed matrix. It should be understood that the product of the two corresponding to the matrix block row of the decompressed matrix may mean that the product is the same as the matrix block row, or that the deviation of the product from the matrix block row is within a preset range, or that the product is the same as the matrix block row after being multiplied by a certain coefficient, and the present application does not limit this. Optionally, the first linear correlation matrix and the first maximally irrelevant group, such as Di and Ci , can be calculated based on the matrix block row of the decompressed matrix, such as Ei , and the first linear correlation matrix multiplied by the first maximally irrelevant group is equal to the matrix block row of the decompressed matrix, that is, there is an equation Ei = Di · Ci . It is worth noting that a matrix block row of a decompressed matrix corresponds to a column vector of a background vector, such as bi , and a column vector can also be called a test cycle. That is, the maximally irrelevant group and the linear correlation matrix within a test cycle can be obtained.
另一种可能的实现方式中，第一线性相关矩阵和第一极大无关组的乘积与解压缩矩阵相对应。应理解，两者乘积与解压缩矩阵相对应可以是指乘积与解压缩矩阵相同，也可以是指乘积与解压缩矩阵的偏差在预设范围内，还可以是指乘积再乘以某个系数后与解压缩矩阵相同，本申请对此不作限定。可选的，还可以根据解压缩矩阵，例如E，计算第一线性相关矩阵和第一极大无关组，例如D和M，，第一线性相关矩阵乘以第一极大无关组等于解压缩矩阵，即有等式E＝D·M。具体地，可以对一个测试周期集合内的每个测试周期内的极大无关组，计算该测试周期集合的极大无关组，即第一极大无关组，例如对{ i} 1≤i≤m计算极大无关组M，并计算该测试周期集合的线性相关矩阵，即第一线性相关矩阵，如D。 In another possible implementation, the product of the first linear correlation matrix and the first maximally irrelevant group corresponds to the decompression matrix. It should be understood that the product of the two corresponding to the decompression matrix may mean that the product is the same as the decompression matrix, or that the deviation between the product and the decompression matrix is within a preset range, or that the product is the same as the decompression matrix after being multiplied by a certain coefficient, and the present application does not limit this. Optionally, the first linear correlation matrix and the first maximally irrelevant group, such as D and M, may also be calculated based on the decompression matrix, such as E, and the first linear correlation matrix multiplied by the first maximally irrelevant group is equal to the decompression matrix, that is, there is an equation E=D·M. Specifically, for each maximally irrelevant group in a test cycle set, the maximally irrelevant group of the test cycle set, that is, the first maximally irrelevant group, may be calculated, for example, the maximally irrelevant group M is calculated for { i } 1≤i≤m , and the linear correlation matrix of the test cycle set, that is, the first linear correlation matrix, such as D, is calculated.
S302，根据第一线性相关矩阵和/或第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，第一目标位包括第一背景向量中的全部或部分无关 位。S302, filling an implicit value into a first target bit in a first background vector according to a first linear correlation matrix and/or a first maximal irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector.
在本申请实施例中，第一背景向量可以为上述图2中的任一背景向量。或者说，第一背景向量为静态压实流程和动态压实流程中的任一背景向量。In the embodiment of the present application, the first background vector may be any background vector in Fig. 2. In other words, the first background vector may be any background vector in a static compaction process and a dynamic compaction process.
在本申请实施例中，第一背景向量可以是ATPG工具合并至少一个故障检测激励后获得的背景向量。第一背景向量包括固定位和无关位，无关位中包括被压缩运算确定的无关位，即当第一背景向量被压缩时，第一背景向量中的部分或全部无关位会被确定下来。为避免后续冲突的产生需要确定该被确定下来的部分或全部无关位的位置和确定下来的值，即隐含值，然后将隐含值填充至第一目标位。In an embodiment of the present application, the first background vector may be a background vector obtained after the ATPG tool merges at least one fault detection stimulus. The first background vector includes fixed bits and irrelevant bits, and the irrelevant bits include irrelevant bits determined by the compression operation, that is, when the first background vector is compressed, some or all of the irrelevant bits in the first background vector will be determined. In order to avoid the occurrence of subsequent conflicts, it is necessary to determine the positions and determined values of some or all of the irrelevant bits that have been determined, that is, implicit values, and then fill the implicit values into the first target bit.
在本申请实施例中，根据第一线性相关矩阵和/或第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量的方式可以有多种，例如可以是下列方式一和方式二中的任意一种。应理解，方式一可以称为动态填充算法，方式二可以称为静态填充算法。值得注意的是，在生成压缩测试向量中，会生成多个背景向量，对于多个背景向量中隐含值的填充方法，方式一和方式二可以单独使用，在单独使用时，本申请实施例对方式一或方式二的使用次数不作限定；方式一和方式二也可以结合使用，在结合使用时，本申请实施例对其先后使用顺序和使用次数不作限定。In an embodiment of the present application, there may be multiple ways to fill the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally independent group to obtain the second background vector, for example, it may be any one of the following ways 1 and 2. It should be understood that way 1 can be called a dynamic filling algorithm, and way 2 can be called a static filling algorithm. It is worth noting that in generating a compressed test vector, multiple background vectors will be generated. For the filling method of implicit values in multiple background vectors, way 1 and way 2 can be used alone. When used alone, the embodiment of the present application does not limit the number of times way 1 or way 2 is used; way 1 and way 2 can also be used in combination. When used in combination, the embodiment of the present application does not limit the order of their use and the number of times they are used.
方式一，包括步骤S304-S305：Method 1, including steps S304-S305:
S304，根据第一线性相关矩阵和第一极大无关组，确定用于指示第一目标位的第一目标位信息，第一目标位信息为第二线性相关矩阵。S304: Determine first target bit information indicating the first target bit according to the first linear correlation matrix and the first maximally independent group, where the first target bit information is the second linear correlation matrix.
在本申请实施例中，第一目标位信息可以用于指示第一目标位，或者换句话说，第一目标位信息可以用于指示第一目标位的位置，也即，第一目标位信息可以用来指示哪些无关位需要填充隐含值。并且，第一目标位信息是一个矩阵，即第二线性相关矩阵。第二线性相关矩阵也可以称为第二线性相关表。In an embodiment of the present application, the first target bit information can be used to indicate the first target bit, or in other words, the first target bit information can be used to indicate the position of the first target bit, that is, the first target bit information can be used to indicate which irrelevant bits need to be filled with implicit values. In addition, the first target bit information is a matrix, namely, a second linear correlation matrix. The second linear correlation matrix can also be called a second linear correlation table.
一种可能的实现方式中，确定第一目标位信息的方式可以是，即确定第二线性相关矩阵的方式可以是，根据解压缩矩阵，获取第一背景向量对应的第一线性方程组的系数矩阵的第二极大无关组，第一线性方程组包括第一背景向量对应的解压缩方程；根据第一极大无关组，向第二极大无关组中添加第二极大无关组的正交补，以获取第三极大无关组；根据第三极大无关组、第一极大无关组和第一线性相关矩阵，确定第二线性相关矩阵。In one possible implementation, the method for determining the first target bit information may be, that is, the method for determining the second linear correlation matrix may be, based on the decompression matrix, obtaining the second maximally irrelevant group of the coefficient matrix of the first linear equation group corresponding to the first background vector, the first linear equation group including the decompression equation corresponding to the first background vector; based on the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group; and determining the second linear correlation matrix based on the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
在本申请实施例中，上述确定第二线性相关矩阵的方式具体可以是：1)根据解压缩矩阵，获取第一背景向量对应的第一线性方程的系数矩阵的第一极大无关组，例如第一极大无关组为B 1；2)根据解压缩矩阵，获取解压缩矩阵线性相关表和极大无关组，例如，解压缩矩阵为E时，有等式E＝D·M，其中矩阵D为解压缩矩阵线性相关表，M为E的极大无关组；3)根据解压缩矩阵的极大无关组，向第一极大无关组中添加正交补，以获取第二极大无关组，例如从M中选取与第一极大无关组正交的线性无关方程B 2，将B 2添加至B 1中，以获取第二极大无关组
Figure PCTCN2022123320-appb-000003
从而M＝T·B；4)根据第二极大无关组和解压缩矩阵，更新解压缩矩阵线性相关表，即确定第二线性相关矩阵，例如，根据等式E＝D·M以及等式M＝T·B，可以得到E＝D·T·B，若设Q＝D·T，则E＝Q·B，即Q为更新后获得的解压缩矩阵线性相关表，也即Q为第二线性相关矩阵。可选的，第二线性相关矩阵可以称为更新后的第一线性相关矩阵，本申请对此不作限定。 In an embodiment of the present application, the above-mentioned method for determining the second linear correlation matrix can be specifically: 1) according to the decompression matrix, obtain the first maximally independent group of the coefficient matrix of the first linear equation corresponding to the first background vector, for example, the first maximally independent group is B1 ; 2) according to the decompression matrix, obtain the decompression matrix linear correlation table and the maximally independent group, for example, when the decompression matrix is E, there is an equation E=D·M, where the matrix D is the decompression matrix linear correlation table, and M is the maximally independent group of E; 3) according to the maximally independent group of the decompression matrix, add orthogonal complement to the first maximally independent group to obtain the second maximally independent group, for example, select a linear independent equation B2 orthogonal to the first maximally independent group from M, and add B2 to B1 to obtain the second maximally independent group
Figure PCTCN2022123320-appb-000003
Thus, M=T·B; 4) According to the second maximally irrelevant group and the decompression matrix, the decompression matrix linear correlation table is updated, that is, the second linear correlation matrix is determined. For example, according to the equation E=D·M and the equation M=T·B, E=D·T·B can be obtained. If Q=D·T is set, then E=Q·B, that is, Q is the decompression matrix linear correlation table obtained after the update, that is, Q is the second linear correlation matrix. Optionally, the second linear correlation matrix can be called the updated first linear correlation matrix, which is not limited in this application.
S305，根据第一目标位信息，在第一目标位中填充隐含值，以获取第二背景向量。S305 , filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.
在本申请实施例中，第二背景向量为通过更新第一背景向量获得的向量，即向第一背 景向量的无关位上填充隐含值后获得的背景向量。从而可以根据更新后的第一背景向量生成故障检测激励，且生成的故障检测激励可以在合并压缩时避免冲突的发生。In the embodiment of the present application, the second background vector is a vector obtained by updating the first background vector, that is, a background vector obtained by filling the irrelevant bits of the first background vector with implicit values. Thus, a fault detection stimulus can be generated according to the updated first background vector, and the generated fault detection stimulus can avoid conflicts when merging and compressing.
在本申请实施例中，第一目标位信息为第二线性相关矩阵，则可以根据第二线性相关矩阵中的元素是否为1，确定第一目标位的位置，然后根据解压缩矩阵和第一背景向量，向确定的第一目标位的位置中填充隐含值，其中，第一目标位中的无关位与第二线性相关矩阵中的元素一一对应。In an embodiment of the present application, the first target bit information is the second linear correlation matrix. The position of the first target bit can be determined based on whether the elements in the second linear correlation matrix are 1, and then the implicit value is filled into the determined position of the first target bit based on the decompression matrix and the first background vector, wherein the irrelevant bits in the first target bit correspond one-to-one to the elements in the second linear correlation matrix.
一种可能的实现方式中，第二线性相关矩阵为更新后的解压缩矩阵线性相关表时，更新后的解压缩矩阵线性相关表中的每一行向量对应于第一背景向量中一个比特位，每一行向量中包括一个或多个元素，元素的取值可以为0或1，当元素取1时，表示对应的比特位可以由第二极大无关组中的线性无关方程组线性表示，因此可以根据更新后的解压缩矩阵线性相关表中元素的取值，确定第一目标位的位置。并在确定第一目标位的位置后，通过计算，确定出无关位上被确定的值，即隐含值。In a possible implementation, when the second linear correlation matrix is an updated decompressed matrix linear correlation table, each row vector in the updated decompressed matrix linear correlation table corresponds to a bit in the first background vector, and each row vector includes one or more elements, and the value of the element can be 0 or 1. When the element is 1, it means that the corresponding bit can be linearly represented by the linear independent equation group in the second maximal independent group. Therefore, the position of the first target bit can be determined according to the value of the element in the updated decompressed matrix linear correlation table. After determining the position of the first target bit, the value determined on the independent bit, that is, the implicit value, is determined by calculation.
关于上述步骤S304-S305的具体实现可参考下述图4的相关说明。For the specific implementation of the above steps S304-S305, please refer to the relevant description of Figure 4 below.
方式二，包括步骤S306-S307：Method 2 includes steps S306-S307:
S306，根据第一极大无关组，确定用于指示第一目标位的第一目标位信息，第一目标位信息为第一背景向量中的目标列向量区间。S306: Determine first target bit information indicating a first target bit according to the first maximally irrelevant group, where the first target bit information is a target column vector interval in the first background vector.
在本申请实施例中，第一背景向量包括至少一个列向量，例如上述公式(3)中的b i表示一个列向量，一个列向量可以称为一个测试周期(cycle)。 In the embodiment of the present application, the first background vector includes at least one column vector. For example, bi in the above formula (3) represents a column vector. A column vector can be called a test cycle.
在本申请实施例中，第一极大无关组可以为一个测试周期内的极大无关组，例如上述步骤S301中的C i。此时，第一极大无关组与一个测试周期对应，即第一极大无关组与第一背景向量的列向量一一对应，可以根据多个第一极大无关组的秩，确定目标列向量区间，目标列向量区间包括至少一个列向量。 In the embodiment of the present application, the first maximally irrelevant group may be a maximally irrelevant group within a test cycle, such as C i in the above step S301. At this time, the first maximally irrelevant group corresponds to a test cycle, that is, the first maximally irrelevant group corresponds to the column vector of the first background vector one-to-one, and the target column vector interval may be determined according to the ranks of the plurality of first maximally irrelevant groups, and the target column vector interval includes at least one column vector.
一种可能的实现方式中，根据多个第一极大无关组的秩，确定目标列向量区间的方式可以是：根据解压缩矩阵和第一背景向量，获取至少一个第二线性方程组，第二线性方程组包括第一背景向量的解压缩方程，第二线性方程组与第一背景向量中的连续列向量区间一一对应；根据至少一个第二线性方程组，确定至少一个第一列向量区间，第一列向量区间对应的第二线性方程组的线性无关方程的个数大于第一阈值；根据至少一个第一列向量区间，确定第二列向量区间，第二列向量区间为至少一个第一列向量区间中包括的列向量数量最多的列向量区间；根据第二列向量区间，确定目标列向量区间，目标列向量区间包括第二列向量区间。In one possible implementation, the target column vector interval is determined according to the ranks of multiple first maximal independent groups as follows: at least one second linear equation group is obtained according to the decompression matrix and the first background vector, the second linear equation group includes the decompression equation of the first background vector, and the second linear equation group corresponds one-to-one to the continuous column vector intervals in the first background vector; at least one first column vector interval is determined according to at least one second linear equation group, and the number of linear independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold; a second column vector interval is determined according to at least one first column vector interval, and the second column vector interval is the column vector interval with the largest number of column vectors included in at least one first column vector interval; a target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.
可选的，第一阈值的确定方式可以是：在每条测试向量的生成过程中，第一阈值可以采用不同的人工经验值，也可以通过学习进行动态调节；Optionally, the first threshold may be determined in the following manner: in the process of generating each test vector, the first threshold may adopt different artificial experience values, or may be dynamically adjusted through learning;
在本申请实施例中，根据第二列向量区间，确定目标列向量区间的方式可以是：确定第二列向量区间对应的至少一个第一极大无关组的秩为第一数值；判断第二列向量区间对应第二线性方程组的线性无关方程的个数是否等于第一数值；根据判断结果，更新第二列向量区间为第三列向量区间；确定第四列向量区间对应的至少一个第一极大无关组的秩与第四列向量区间对应的第二线性方程组的线性无关方程的个数相等，第四列向量区间为第三列向量区间的相邻列向量区间；确定目标列向量区间为第三列向量区间和第四列向量区间的合集。In an embodiment of the present application, a method for determining a target column vector interval based on the second column vector interval may be: determining that the rank of at least one first maximally irrelevant group corresponding to the second column vector interval is a first numerical value; determining whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first numerical value; based on the judgment result, updating the second column vector interval to a third column vector interval; determining that the rank of at least one first maximally irrelevant group corresponding to the fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval; determining the target column vector interval to be the union of the third column vector interval and the fourth column vector interval.
在本申请实施例中，根据判断结果，更新第二列向量区间为第三列向量区间的方式可以是：当第二列向量区间对应的线性无关方程的个数不等于第一数值时，确定该线性无关方程中部分常数项的值，以使得第二列向量区间更新为第三列向量区间，第三列向量区间对应的第二线性无关方程组的线性无关方程的个数等于第一数值。应理解，第二列向量区间与第三列向量区间包括的列向量个数相同，不同之处在于，第三列向量区间中部分无关位上的值被确定下来了，即常数项的值被确定了。In an embodiment of the present application, according to the judgment result, the method of updating the second column vector interval to the third column vector interval can be: when the number of linearly independent equations corresponding to the second column vector interval is not equal to the first value, determine the value of some constant terms in the linearly independent equations, so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linearly independent equation group corresponding to the third column vector interval is equal to the first value. It should be understood that the second column vector interval includes the same number of column vectors as the third column vector interval, and the difference is that the values on some irrelevant bits in the third column vector interval are determined, that is, the value of the constant term is determined.
可选的，上述确定常数项的值的方式可以是根据该常数项出现值的可能性随机给定。Optionally, the above method of determining the value of the constant term may be to randomly assign the value according to the probability of occurrence of the value of the constant term.
在本申请实施例中，确定目标列向量区间的具体方式可以是：1)根据解压缩矩阵，获取第一背景向量中每个列向量中的无关值关于压缩值的线性方程，即每个测试周期内的元素关于压缩值的线性方程；2)然后计算每个测试周期内的线性无关方程；3)接着获取测试周期区域内的线性无关方程的数量大于第一阈值的测试周期区域，或者说，获取大于等于第一阈值的列向量区间；4)从获取的测试周期区域内选择第一测试周期区域，第一测试周期区域为获取的测试周期区域中长度最大的区域，即包括的列向量最多的第一列向量区间，例如(b i，b j)；5)向第一测试周期区域内的无关位上随机填充值，以使得第一测试周期区域为满秩，即使得第一列向量区间内的线性无关方程的数量等于该列向量区间对应的多个第一极大无关组的秩；6)外扩第一测试周期区域，获取满秩的第二测试周期区域，即第二列向量区间内的线性无关方程的数量等于该列向量区间对应的多个第一极大无关组的秩。 In an embodiment of the present application, a specific method for determining a target column vector interval may be: 1) obtaining, according to the decompression matrix, a linear equation of the irrelevant value in each column vector in the first background vector with respect to the compressed value, that is, a linear equation of the element in each test cycle with respect to the compressed value; 2) then calculating the linearly independent equations in each test cycle; 3) then obtaining a test cycle region in which the number of linearly independent equations in the test cycle region is greater than a first threshold, or in other words, obtaining a column vector interval greater than or equal to the first threshold; 4) selecting a first test cycle region from the obtained test cycle region, the first test cycle region being the region with the largest length in the obtained test cycle region, that is, the first column vector interval including the most column vectors, for example (b i , b j ); 5) randomly filling values into irrelevant bits in the first test cycle region so that the first test cycle region is full rank, that is, the number of linearly independent equations in the first column vector interval is equal to the rank of the multiple first maximally irrelevant groups corresponding to the column vector interval; 6) expanding the first test cycle region to obtain a second test cycle region of full rank, that is, the number of linearly independent equations in the second column vector interval is equal to the rank of the multiple first maximally irrelevant groups corresponding to the column vector interval.
值得注意的值，上述“满秩”是指背景向量中的某个列向量区间的解压缩方程组中线性无关方程的个数，与该列向量区间对应的解压缩矩阵的极大无关组的秩相等，或者说，与该列向量区间对应的解压缩矩阵的极大无关组包括的向量个数相等。It is worth noting that the above-mentioned "full rank" means that the number of linearly independent equations in the decompression equation group of a certain column vector interval in the background vector is equal to the rank of the maximal independent group of the decompression matrix corresponding to the column vector interval, or in other words, the number of vectors included in the maximal independent group of the decompression matrix corresponding to the column vector interval is equal.
S307，根据第一目标位信息，在第一目标位中填充隐含值，以获取第二背景向量。S307 , filling an implicit value in the first target bit according to the first target bit information to obtain a second background vector.
在本申请实施例中，可以根据目标列向量区间和解压缩矩阵，计算目标列向量区间中的无关位的隐含值；将隐含值填充至第一目标位中，以获取第二背景向量。或者换句话说，将第一背景向量中的部分值确定下来，即更新第一背景向量，可获得第二背景向量，从而在更新第一背景向量后，可以避免后续由于部分确定的无关位导致的冲突问题，提升生成压缩测试向量的效率。In the embodiment of the present application, the implicit value of the irrelevant bit in the target column vector interval can be calculated according to the target column vector interval and the decompression matrix; the implicit value is filled into the first target bit to obtain the second background vector. In other words, the second background vector can be obtained by determining part of the value in the first background vector, that is, updating the first background vector, so that after the first background vector is updated, the subsequent conflict problem caused by the partially determined irrelevant bit can be avoided, and the efficiency of generating the compressed test vector can be improved.
关于上述步骤S306-S307的具体实现可参考下述图5的相关说明。For the specific implementation of the above steps S306-S307, please refer to the relevant description of Figure 5 below.
S303，根据第二背景向量，生成压缩测试向量。S303: Generate a compressed test vector according to the second background vector.
在本申请实施例中，可以直接对第二背景向量进行压缩，生成压缩测试向量，也可以根据第二背景向量生成故障检测激励，在经过一系列的合并、压缩后，生成压缩测试向量，也可以再经过类似于上述步骤S301-S302的重复一次或多次操作后，生成压缩测试向量，本申请对此不作限定。In an embodiment of the present application, the second background vector can be directly compressed to generate a compressed test vector, or a fault detection stimulus can be generated based on the second background vector. After a series of merging and compression, a compressed test vector is generated. Alternatively, a compressed test vector can be generated after repeating one or more operations similar to the above steps S301-S302. The present application does not limit this.
因此，上述方法通过对第一背景向量填充隐含值，生成第二背景向量后，再生成压缩测试向量，即对第一背景向量进行了更新，从而避免了由于第一背景向量中由于压缩运算应该确定的值未被确定，导致的后续合并、压缩的冲突的问题，提升了生成压缩测试向量的效率。Therefore, the above method fills the first background vector with implicit values, generates the second background vector, and then generates the compressed test vector, that is, updates the first background vector, thereby avoiding the problem of subsequent merging and compression conflicts caused by the fact that the value that should be determined by the compression operation in the first background vector is not determined, thereby improving the efficiency of generating compressed test vectors.
图4示出了本申请实施例提供的一种生成压缩测试向量的示例性方法的示意图。具体地，该方法400包括：FIG4 is a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application. Specifically, the method 400 includes:
S401，获取第一背景向量。S401, obtaining a first background vector.
在本申请实施例中，第一背景向量可以是经过静态压实流程后获得的背景向量，也可以是动态压实流程中获得的背景向量，本申请对此不作限定。In an embodiment of the present application, the first background vector may be a background vector obtained after a static compaction process, or may be a background vector obtained during a dynamic compaction process, and the present application does not impose any limitation on this.
S402，获取第一背景向量对应的极大无关组B 1。 S402, obtaining a maximally irrelevant group B 1 corresponding to a first background vector.
在本申请实施例中，极大无关组B 1为第一背景向量对应的线性方程组的系数矩阵的极大无关组，该线性方程组包括第一背景向量的压缩方程。 In the embodiment of the present application, the maximal independent group B1 is a maximal independent group of the coefficient matrix of the linear equation group corresponding to the first background vector, and the linear equation group includes the compression equation of the first background vector.
S403，基于解压缩矩阵的极大无关组M，将第一背景向量的对应的极大无关组B 1补全为极大无关组B，并建立映射关系M＝T·B。 S403: Based on the maximally irrelevant group M of the decompressed matrix, the maximally irrelevant group B1 corresponding to the first background vector is completed into the maximally irrelevant group B, and a mapping relationship M=T·B is established.
在本申请实施例中，从极大无关组M中选取方程组B 2，将B 2添加至B 1中，获取极大无关组B，使得M＝T·B。 In the embodiment of the present application, the equation group B 2 is selected from the maximally independent group M, and B 2 is added to B 1 to obtain the maximally independent group B, so that M=T·B.
S404，更新解压缩矩阵对应的线性相关矩阵为Q＝D·T。S404, updating the linear correlation matrix corresponding to the decompression matrix to Q=D·T.
在本申请实施例中，将解压缩矩阵的线性相关矩阵从D更新为Q。In the embodiment of the present application, the linear correlation matrix of the decompressed matrix is updated from D to Q.
S405，根据更新后的线性相关矩阵Q，计算并填充隐含值。S405, calculating and filling implicit values according to the updated linear correlation matrix Q.
关于上述步骤S401-S405的具体实现可参考上述步骤S304-S305，此处不再赘述。For the specific implementation of the above steps S401-S405, please refer to the above steps S304-S305, which will not be repeated here.
图5示出了本申请实施例提供的一种生成压缩测试向量的示例性方法示意图。具体地，该方法500包括：FIG5 shows a schematic diagram of an exemplary method for generating a compressed test vector provided by an embodiment of the present application. Specifically, the method 500 includes:
S501，获取第一背景向量。S501, obtaining a first background vector.
在本申请实施例中，第一背景向量可以是经过静态压实流程后获得的背景向量，也可以是动态压实流程中获得的背景向量，本申请对此不作限定。In an embodiment of the present application, the first background vector may be a background vector obtained after a static compaction process, or may be a background vector obtained during a dynamic compaction process, and the present application does not impose any limitation on this.
S502，获取第一背景向量中多个列向量区间对应的线性方程组的秩。S502, obtaining the rank of a linear equation group corresponding to multiple column vector intervals in the first background vector.
在本申请实施例中，多个列向量区间对应的线性方程组包括背景向量的解压缩方程，多个列向量区间中每个列向量区间对应的线性方程组的秩可以称为区间秩，即上述步骤S502为获取多个区间秩。In an embodiment of the present application, the linear equation group corresponding to multiple column vector intervals includes the decompression equation of the background vector, and the rank of the linear equation group corresponding to each column vector interval in the multiple column vector intervals can be called the interval rank, that is, the above step S502 is to obtain multiple interval ranks.
S503，判断秩是否大于第一阈值。S503: Determine whether the rank is greater than a first threshold.
在本申请实施例中，判断多个区间秩中是否有大于第一阈值的区间秩。In the embodiment of the present application, it is determined whether there is an interval rank greater than a first threshold among multiple interval ranks.
若无，则停止后续的步骤。If not, stop the subsequent steps.
若有，则继续下列步骤：If yes, continue with the following steps:
S504，补全秩大于第一阈值的多个列向量区间中连续列向量个数最多的列向量区间的秩为满秩。S504: Fill in the rank of a column vector interval with the largest number of consecutive column vectors among multiple column vector intervals whose ranks are greater than a first threshold, to be full rank.
在本申请实施例中，首先需要选取多个列向量区间中连续列向量个数最多列向量区间，然后将确定该列向量区间中部分无关位的值，使得该列向量区间为满秩。关于满秩在本申请中的含义可参考上述步骤S306中的相关说明，此处不再赘述。In the embodiment of the present application, first, it is necessary to select a column vector interval with the largest number of consecutive column vectors from multiple column vector intervals, and then determine the values of some irrelevant bits in the column vector interval so that the column vector interval is full rank. For the meaning of full rank in the present application, please refer to the relevant description in the above step S306, which will not be repeated here.
S506，检查邻近列向量区间是否为满秩，更新满秩区间。S506, check whether the adjacent column vector interval is full rank, and update the full rank interval.
在本申请实施例中，可以检查上述步骤S504中确定的满秩区间的邻近区间是否为满秩，若有则更新满秩区间为步骤S504中确定的满秩区间与满秩的邻近区间的集合。In an embodiment of the present application, it is possible to check whether the adjacent interval of the full rank interval determined in the above step S504 is full rank. If so, the full rank interval is updated to be the set of the full rank interval determined in step S504 and its adjacent intervals.
S507，计算更新后的满秩区间的隐含值。S507, calculating the updated implicit value of the full rank interval.
在本申请实施例中，计算更新后的满秩区间的隐含值，将其填充至第一背景向量后，既可以获得第二背景向量。In the embodiment of the present application, the implicit value of the updated full rank interval is calculated and filled into the first background vector to obtain the second background vector.
关于上述步骤S501-S506的具体实现可参考上述步骤S306-S307，此处不再赘述。For the specific implementation of the above steps S501-S506, please refer to the above steps S306-S307, which will not be repeated here.
上文详细地描述了本申请实施例的方法实施例，下面描述本申请实施例的装置实施例，装置实施例与方法实施例相互对应，因此未详细描述的部分可参见前面方法实施例，装置可以实现上述方法中任意可能实现的方式。The above describes in detail the method embodiment of the embodiment of the present application, and the following describes the device embodiment of the embodiment of the present application. The device embodiment and the method embodiment correspond to each other, so the parts that are not described in detail can refer to the previous method embodiment, and the device can implement any possible implementation method of the above method.
图6示出了本申请提供的一个实施例的生成压缩测试向量的装置600的示意性框图。该装置600可以执行上述本申请实施例的生成压缩测试向量的方法。Fig. 6 shows a schematic block diagram of an apparatus 600 for generating a compressed test vector according to an embodiment of the present application. The apparatus 600 can execute the method for generating a compressed test vector according to the embodiment of the present application.
如图6所示，该装置包括处理模块601。As shown in FIG. 6 , the device includes a processing module 601 .
当该装置600执行上述方法300时，处理模块601用于：根据待测芯片对应的解压缩矩阵，获取第一线性相关矩阵和第一极大无关组，其中，所述解压缩矩阵为所述待测芯片的解压缩电路结构对应的矩阵；根据所述第一线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，所述第一目标位包括所述第一背景向量中的全部或部分无关位；根据所述第二背景向量，生成压缩测试向量。When the device 600 executes the above method 300, the processing module 601 is used to: obtain a first linear correlation matrix and a first maximally irrelevant group according to the decompression matrix corresponding to the chip under test, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test; fill an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector; and generate a compressed test vector according to the second background vector.
关于上述装置600的更详细功能，可参考上述方法实施中的相关描述，此处不再赘述。For more detailed functions of the above-mentioned device 600, please refer to the relevant description in the implementation of the above-mentioned method, which will not be repeated here.
图7是本申请提供的一个实施例的压缩测试向量的装置的硬件结构示意图。图7所示的压缩测试向量的装置700包括存储器701、处理器702、通信接口703以及总线704。其中，存储器701、处理器702、通信接口703通过总线704实现彼此之间的通信连接。FIG7 is a schematic diagram of the hardware structure of a device for compressing test vectors according to an embodiment of the present application. The device 700 for compressing test vectors shown in FIG7 includes a memory 701, a processor 702, a communication interface 703, and a bus 704. The memory 701, the processor 702, and the communication interface 703 are connected to each other through the bus 704.
存储器701可以是只读存储器(read-only memory，ROM)，静态存储设备和随机存取存储器(random access memory，RAM)。存储器701可以存储程序，当存储器701中存储的程序被处理器702执行时，处理器702和通信接口703用于执行本申请实施例的压缩测试向量的方法的各个步骤。The memory 701 may be a read-only memory (ROM), a static storage device, and a random access memory (RAM). The memory 701 may store a program. When the program stored in the memory 701 is executed by the processor 702, the processor 702 and the communication interface 703 are used to execute the various steps of the method for compressing the test vector of the embodiment of the present application.
处理器702可以采用通用的中央处理器(central processing unit，CPU)，微处理器，应用专用集成电路(application specific integrated circuit，ASIC)，图形处理器(graphics processing unit，GPU)或者一个或多个集成电路，用于执行相关程序，以实现本申请实施例的压缩测试向量的装置中的单元所需执行的功能，或者执行本申请实施例的压缩测试向量的方法。Processor 702 can adopt a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits to execute relevant programs to implement the functions required to be performed by the units in the device for compressing the test vector of the embodiment of the present application, or to execute the method for compressing the test vector of the embodiment of the present application.
处理器702还可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，本申请实施例的压缩测试向量的方法的各个步骤可以通过处理器702中的硬件的集成逻辑电路或者软件形式的指令完成。The processor 702 may also be an integrated circuit chip with signal processing capability. In the implementation process, each step of the method for compressing test vectors in the embodiment of the present application may be completed by hardware integrated logic circuits in the processor 702 or software instructions.
上述处理器702还可以是通用处理器、数字信号处理器(digital signal processing，DSP)、ASIC、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器701，处理器702读取存储器701中的信息，结合其硬件完成本申请实施例的压缩测试向量的装置中包括的单元所需执行的功能，或者执行本申请实施例的压缩测试向量的方法。The processor 702 may also be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. The methods, steps, and logic diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor. The software module may be located in a mature storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 701, and the processor 702 reads the information in the memory 701, and combines its hardware to complete the functions required to be performed by the units included in the device for compressing the test vector of the embodiment of the present application, or executes the method for compressing the test vector of the embodiment of the present application.
通信接口703使用例如但不限于收发器一类的收发装置，来实现装置700与其他设备或通信网络之间的通信。例如，可以通过通信接口703获取未知设备的流量数据。The communication interface 703 uses a transceiver such as, but not limited to, a transceiver to implement communication between the device 700 and other devices or a communication network. For example, the traffic data of an unknown device can be obtained through the communication interface 703.
总线704可包括在装置700各个部件(例如，存储器701、处理器702、通信接口703)之间传送信息的通路。The bus 704 may include a path for transmitting information between various components of the device 700 (eg, the memory 701 , the processor 702 , and the communication interface 703 ).
应注意，尽管上述装置700仅仅示出了存储器、处理器、通信接口，但是在具体实现过程中，本领域的技术人员应当理解，装置700还可以包括实现正常运行所必须的其他器件。同时，根据具体需要，本领域的技术人员应当理解，装置700还可包括实现其他附加功能的硬件器件。此外，本领域的技术人员应当理解，装置700也可仅仅包括实现本申请实施例所必须的器件，而不必包括图7中所示的全部器件。It should be noted that although the above device 700 only shows a memory, a processor, and a communication interface, in the specific implementation process, those skilled in the art should understand that the device 700 may also include other devices necessary for normal operation. At the same time, according to specific needs, those skilled in the art should understand that the device 700 may also include hardware devices for implementing other additional functions. In addition, those skilled in the art should understand that the device 700 may also only include the devices necessary for implementing the embodiments of the present application, and does not necessarily include all the devices shown in FIG. 7.
本申请实施例还提供了一种计算机可读存储介质，存储用于设备执行的程序代码，程序代码包括用于执行上述压缩测试向量的方法中的步骤的指令。An embodiment of the present application also provides a computer-readable storage medium that stores program code for execution by a device, wherein the program code includes instructions for executing the steps in the above-mentioned method for compressing test vectors.
本申请实施例还提供了一种计算机程序产品，所述计算机程序产品包括存储在计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，使所述计算机执行上述压缩测试向量的方法。An embodiment of the present application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the above-mentioned method of compressing test vectors.
上述的计算机可读存储介质可以是暂态计算机可读存储介质，也可以是非暂态计算机可读存储介质。The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
在本申请所提供的几个实施例中，应该理解到，所揭露的***、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代 码的介质。If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (24)

  1. 一种生成压缩测试向量的方法，其特征在于，包括：A method for generating a compressed test vector, comprising:
    根据待测芯片对应的解压缩矩阵，获取第一线性相关矩阵和第一极大无关组，其中，所述解压缩矩阵为所述待测芯片的解压缩电路结构对应的矩阵；According to the decompression matrix corresponding to the chip under test, a first linear correlation matrix and a first maximally independent group are obtained, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test;
    根据所述第一线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，所述第一目标位包括所述第一背景向量中的全部或部分无关位；Filling an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector;
    根据所述第二背景向量，生成压缩测试向量。A compressed test vector is generated according to the second background vector.
  2. 根据权利要求1所述的方法，其特征在于，所述根据第一线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，包括：The method according to claim 1, characterized in that the step of filling the first target bit in the first background vector with an implicit value according to the first linear correlation matrix and/or the first maximally independent group to obtain the second background vector comprises:
    根据所述第一线性相关矩阵和所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为第二线性相关矩阵；Determine, according to the first linear correlation matrix and the first maximally independent group, first target bit information for indicating a first target bit, wherein the first target bit information is a second linear correlation matrix;
    根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述第一线性相关矩阵和所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为第二线性相关矩阵，包括：The method according to claim 2 is characterized in that the determining, according to the first linear correlation matrix and the first maximally independent group, first target bit information indicating the first target bit, the first target bit information being a second linear correlation matrix, comprises:
    根据所述解压缩矩阵，获取所述第一背景向量对应的第一线性方程组的系数矩阵的第二极大无关组，所述第一线性方程组包括所述第一背景向量对应的解压缩方程；According to the decompression matrix, obtaining a second maximal independent group of coefficient matrices of a first linear equation group corresponding to the first background vector, wherein the first linear equation group includes a decompression equation corresponding to the first background vector;
    根据所述第一极大无关组，向所述第二极大无关组中添加所述第二极大无关组的正交补，以获取第三极大无关组；According to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group;
    根据所述第三极大无关组、所述第一极大无关组和所述第一线性相关矩阵，确定所述第二线性相关矩阵。The second linear correlation matrix is determined according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  4. 根据权利要求2或3所述的方法，其特征在于，所述根据所述第一目标位信息，在所述第一目标位中填充隐含值，包括：The method according to claim 2 or 3, characterized in that filling the first target bit with an implicit value according to the first target bit information comprises:
    根据所述第二线性相关矩阵中的元素是否为1，确定所述第一目标位的位置，所述第一目标位中的所述无关位与所述第二线性相关矩阵中的所述元素一一对应；Determine the position of the first target bit according to whether the element in the second linear correlation matrix is 1, and the don't care bits in the first target bit correspond to the elements in the second linear correlation matrix one by one;
    根据解压缩矩阵和所述第一背景向量，向确定的所述第一目标位的位置中填充隐含值。Fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.
  5. 根据权利要求1所述的方法，其特征在于，所述根据第一所述线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，包括：The method according to claim 1, characterized in that the step of filling an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally independent group to obtain a second background vector comprises:
    根据所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为所述第一背景向量中的目标列向量区间；Determine, according to the first maximally irrelevant group, first target bit information for indicating a first target bit, wherein the first target bit information is a target column vector interval in the first background vector;
    根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
  6. 根据权利要求5所述的方法，其特征在于，所述第一背景向量包括至少一个列向量，所述第一极大无关组与所述列向量一一对应，所述根据所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，包括：The method according to claim 5, characterized in that the first background vector includes at least one column vector, the first maximally irrelevant group corresponds to the column vector one-to-one, and determining the first target bit information indicating the first target bit according to the first maximally irrelevant group comprises:
    根据多个所述第一极大无关组的秩，确定所述目标列向量区间，所述目标列向量区间包括连续的至少一个列向量。The target column vector interval is determined according to the ranks of the plurality of the first maximally unrelated groups, and the target column vector interval includes at least one continuous column vector.
  7. 根据权利要求6所述的方法，其特征在于，所述根据多个所述第一极大无关组的秩，确定所述目标列向量区间，包括：The method according to claim 6, characterized in that the step of determining the target column vector interval according to the ranks of the plurality of first maximally unrelated groups comprises:
    根据所述解压缩矩阵和所述第一背景向量，获取至少一个第二线性方程组，所述第二线性方程组包括所述第一背景向量的解压缩方程，所述第二线性方程组与所述第一背景向量中的连续列向量区间一一对应；According to the decompression matrix and the first background vector, obtaining at least one second linear equation group, the second linear equation group includes a decompression equation of the first background vector, and the second linear equation group has a one-to-one correspondence with a continuous column vector interval in the first background vector;
    根据所述至少一个第二线性方程组，确定至少一个第一列向量区间，所述第一列向量区间对应的第二线性方程组的线性无关方程的个数大于第一阈值；Determine at least one first column vector interval according to the at least one second linear equation group, wherein the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold;
    根据所述至少一个第一列向量区间，确定第二列向量区间，所述第二列向量区间为所述至少一个第一列向量区间中包括的列向量数量最多的列向量区间；Determine a second column vector interval according to the at least one first column vector interval, where the second column vector interval is a column vector interval including the largest number of column vectors in the at least one first column vector interval;
    根据所述第二列向量区间，确定所述目标列向量区间，所述目标列向量区间包括所述第二列向量区间。The target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.
  8. 根据权利要求7所述的方法，其特征在于，所述根据所述第二列向量区间，确定所述目标列向量区间，包括：The method according to claim 7, characterized in that the step of determining the target column vector interval according to the second column vector interval comprises:
    确定所述第二列向量区间对应的至少一个所述第一极大无关组的秩为第一数值；Determine that the rank of at least one of the first maximally unrelated groups corresponding to the second column vector interval is a first value;
    判断所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数是否等于所述第一数值；Determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value;
    根据判断结果，更新所述第二列向量区间为第三列向量区间；According to the judgment result, the second column vector interval is updated to the third column vector interval;
    确定第四列向量区间对应的至少一个所述第一极大无关组的秩与所述第四列向量区间对应的所述第二线性方程组的线性无关方程的个数相等，所述第四列向量区间为所述第三列向量区间的邻近列向量区间；Determine that the rank of at least one of the first maximally independent groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval;
    确定所述目标列向量区间为所述第三列向量区间和所述第四列向量区间的合集。The target column vector interval is determined to be a union of the third column vector interval and the fourth column vector interval.
  9. 根据权利要求8所述的方法，其特征在于，所述根据判断结果，更新所述第二列向量区间为第三列向量区间，包括：The method according to claim 8, characterized in that the updating of the second column vector interval to a third column vector interval according to the judgment result comprises:
    当所述判断结果为所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数不等于所述第一数值时，确定所述线性无关方程中部分常数项的值，以使得所述第二列向量区间更新为所述第三列向量区间，所述第三列向量区间对应的所述第二线性方程组的线性无关方程的个数等于所述第一数值。When the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, the values of some constant terms in the linearly independent equations are determined so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
  10. 根据权利要求5-9中任一项所述的方法，其特征在于，所述根据所述第一目标位信息，在所述第一目标位中填充隐含值，包括：The method according to any one of claims 5 to 9, characterized in that filling the first target bit with an implicit value according to the first target bit information comprises:
    根据所述目标列向量区间和所述解压缩矩阵，计算所述目标列向量区间中的无关位的隐含值；Calculate the implicit value of the don't care bits in the target column vector interval according to the target column vector interval and the decompression matrix;
    将所述隐含值填充至所述第一目标位中。The first target bit is filled with the implicit value.
  11. 根据权利要求1-10中任一项所述的方法，其特征在于，所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵的矩阵块行相对应；或者，The method according to any one of claims 1 to 10, characterized in that the product of the first linear correlation matrix and the first maximal independent group corresponds to a matrix block row of the decompressed matrix; or
    所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵相对应。The product of the first linear dependence matrix and the first maximally independent group corresponds to the decompressed matrix.
  12. 一种生成压缩测试向量的装置，其特征在于，所述装置包括处理模块，所述处理模块用于：A device for generating a compressed test vector, characterized in that the device comprises a processing module, wherein the processing module is used to:
    根据待测芯片对应的解压缩矩阵，获取第一线性相关矩阵和第一极大无关组，其中，所述解压缩矩阵为所述待测芯片的解压缩电路结构对应的矩阵；According to the decompression matrix corresponding to the chip under test, a first linear correlation matrix and a first maximally independent group are obtained, wherein the decompression matrix is a matrix corresponding to the decompression circuit structure of the chip under test;
    根据所述第一线性相关矩阵和/或所述第一极大无关组，向第一背景向量中的第一目标位填充隐含值，以获取第二背景向量，所述第一目标位包括所述第一背景向量中的全部或部分无关位；Filling an implicit value into a first target bit in a first background vector according to the first linear correlation matrix and/or the first maximally irrelevant group to obtain a second background vector, wherein the first target bit includes all or part of the irrelevant bits in the first background vector;
    根据所述第二背景向量，生成压缩测试向量。A compressed test vector is generated according to the second background vector.
  13. 根据权利要求12所述的装置，其特征在于，所述处理模块具体用于：The device according to claim 12, characterized in that the processing module is specifically used to:
    根据所述第一线性相关矩阵和所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为第二线性相关矩阵；Determine, according to the first linear correlation matrix and the first maximally independent group, first target bit information for indicating a first target bit, wherein the first target bit information is a second linear correlation matrix;
    根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
  14. 根据权利要求13所述的装置，其特征在于，所述处理单元还具体用于：The device according to claim 13, characterized in that the processing unit is further specifically used for:
    根据所述解压缩矩阵，获取所述第一背景向量对应的第一线性方程组的系数矩阵的第二极大无关组，所述第一线性方程组包括所述第一背景向量对应的解压缩方程；According to the decompression matrix, obtaining a second maximal independent group of coefficient matrices of a first linear equation group corresponding to the first background vector, wherein the first linear equation group includes a decompression equation corresponding to the first background vector;
    根据所述第一极大无关组，向所述第二极大无关组中添加所述第二极大无关组的正交补，以获取第三极大无关组；According to the first maximally irrelevant group, adding the orthogonal complement of the second maximally irrelevant group to the second maximally irrelevant group to obtain a third maximally irrelevant group;
    根据所述第三极大无关组、所述第一极大无关组和所述第一线性相关矩阵，确定所述第二线性相关矩阵。The second linear correlation matrix is determined according to the third maximally irrelevant group, the first maximally irrelevant group and the first linear correlation matrix.
  15. 根据权利要求13或14所述的装置，其特征在于，所述处理单元还具体用于：The device according to claim 13 or 14, characterized in that the processing unit is further specifically used for:
    根据所述第二线性相关矩阵中的元素是否为1，确定所述第一目标位的位置，所述第一目标位中的所述无关位与所述第二线性相关矩阵中的所述元素一一对应；Determine the position of the first target bit according to whether the element in the second linear correlation matrix is 1, and the don't care bits in the first target bit correspond to the elements in the second linear correlation matrix one by one;
    根据解压缩矩阵和所述第一背景向量，向确定的所述第一目标位的位置中填充隐含值。Fill the determined position of the first target bit with an implicit value according to the decompression matrix and the first background vector.
  16. 根据权利要求12所述的装置，其特征在于，所述处理单元具体用于：The device according to claim 12, characterized in that the processing unit is specifically used for:
    根据所述第一极大无关组，确定用于指示第一目标位的第一目标位信息，所述第一目标位信息为所述第一背景向量中的目标列向量区间；Determine, according to the first maximally irrelevant group, first target bit information for indicating a first target bit, wherein the first target bit information is a target column vector interval in the first background vector;
    根据所述第一目标位信息，在所述第一目标位中填充隐含值，以获取第二背景向量。According to the first target bit information, an implicit value is filled in the first target bit to obtain a second background vector.
  17. 根据权利要求16所述的装置，其特征在于，所述第一背景向量包括至少一个列向量，所述第一极大无关组与所述列向量一一对应，所述处理单元还具体用于：The device according to claim 16, characterized in that the first background vector includes at least one column vector, the first maximally irrelevant group corresponds to the column vector one by one, and the processing unit is further specifically used for:
    根据多个所述第一极大无关组的秩，确定所述目标列向量区间，所述目标列向量区间包括连续的至少一个列向量。The target column vector interval is determined according to the ranks of the plurality of the first maximally unrelated groups, and the target column vector interval includes at least one continuous column vector.
  18. 根据权利要求17所述的装置，其特征在于，所述处理单元还具体用于：The device according to claim 17, characterized in that the processing unit is further specifically used for:
    根据所述解压缩矩阵和所述第一背景向量，获取至少一个第二线性方程组，所述第二线性方程组包括所述第一背景向量的解压缩方程，所述第二线性方程组与所述第一背景向量中的连续列向量区间一一对应；According to the decompression matrix and the first background vector, obtaining at least one second linear equation group, the second linear equation group includes a decompression equation of the first background vector, and the second linear equation group has a one-to-one correspondence with a continuous column vector interval in the first background vector;
    根据所述至少一个第二线性方程组，确定至少一个第一列向量区间，所述第一列向量区间对应的第二线性方程组的线性无关方程的个数大于第一阈值；Determine at least one first column vector interval according to the at least one second linear equation group, wherein the number of linearly independent equations of the second linear equation group corresponding to the first column vector interval is greater than a first threshold;
    根据所述至少一个第一列向量区间，确定第二列向量区间，所述第二列向量区间为所述至少一个第一列向量区间中包括的列向量数量最多的列向量区间；Determine a second column vector interval according to the at least one first column vector interval, where the second column vector interval is a column vector interval including the largest number of column vectors in the at least one first column vector interval;
    根据所述第二列向量区间，确定所述目标列向量区间，所述目标列向量区间包括所述第二列向量区间。The target column vector interval is determined according to the second column vector interval, and the target column vector interval includes the second column vector interval.
  19. 根据权利要求18所述的装置，其特征在于，所述处理单元还具体用于：The device according to claim 18, characterized in that the processing unit is further specifically used for:
    确定所述第二列向量区间对应的至少一个所述第一极大无关组的秩为第一数值；Determine that the rank of at least one of the first maximally unrelated groups corresponding to the second column vector interval is a first value;
    判断所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数是否等于所述第一数值；Determine whether the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is equal to the first value;
    根据判断结果，更新所述第二列向量区间为第三列向量区间；According to the judgment result, the second column vector interval is updated to the third column vector interval;
    确定第四列向量区间对应的至少一个所述第一极大无关组的秩与所述第四列向量区间对应的所述第二线性方程组的线性无关方程的个数相等，所述第四列向量区间为所述第三列向量区间的邻近列向量区间；Determine that the rank of at least one of the first maximally independent groups corresponding to a fourth column vector interval is equal to the number of linearly independent equations of the second linear equation group corresponding to the fourth column vector interval, and the fourth column vector interval is an adjacent column vector interval of the third column vector interval;
    确定所述目标列向量区间为所述第三列向量区间和所述第四列向量区间的合集。The target column vector interval is determined to be a union of the third column vector interval and the fourth column vector interval.
  20. 根据权利要求19所述的装置，其特征在于，所述处理单元还用于：The device according to claim 19, characterized in that the processing unit is further used for:
    当所述判断结果为所述第二列向量区间对应的所述第二线性方程组的线性无关方程的个数不等于所述第一数值时，确定所述线性无关方程中部分常数项的值，以使得所述第二列向量区间更新为所述第三列向量区间，所述第三列向量区间对应的所述第二线性方程组的线性无关方程的个数等于所述第一数值。When the judgment result is that the number of linearly independent equations of the second linear equation group corresponding to the second column vector interval is not equal to the first numerical value, the values of some constant terms in the linearly independent equations are determined so that the second column vector interval is updated to the third column vector interval, and the number of linearly independent equations of the second linear equation group corresponding to the third column vector interval is equal to the first numerical value.
  21. 根据权利要求16-20中任一项所述的装置，其特征在于，所述处理单元还用于：The device according to any one of claims 16 to 20, characterized in that the processing unit is further used for:
    根据所述目标列向量区间和所述解压缩矩阵，计算所述目标列向量区间中的无关位的隐含值；Calculate the implicit value of the don't care bits in the target column vector interval according to the target column vector interval and the decompression matrix;
    将所述隐含值填充至所述第一目标位中。The first target bit is filled with the implicit value.
  22. 根据权利要求12-21中任一项所述的装置，其特征在于，所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵的矩阵块行相对应；或者，The device according to any one of claims 12 to 21, characterized in that the product of the first linear correlation matrix and the first maximal independent group corresponds to a matrix block row of the decompressed matrix; or
    所述第一线性相关矩阵和所述第一极大无关组的乘积与所述解压缩矩阵相对应。The product of the first linear dependence matrix and the first maximally independent group corresponds to the decompressed matrix.
  23. 一种生成压缩测试向量的装置，其特征在于，包括处理器和存储器，所述存储器用于存储程序，所述处理器用于从所述存储器中调用并运行所述程序以执行权利要求1至11中任一项所述的方法。A device for generating a compressed test vector, characterized in that it comprises a processor and a memory, wherein the memory is used to store a program, and the processor is used to call and run the program from the memory to execute the method described in any one of claims 1 to 11.
  24. 一种计算机可读存储介质，其特征在于，包括计算机程序，当所述计算机程序在计算机上运行时，使得所述计算机执行权利要求1至11中任一项所述的方法。A computer-readable storage medium, characterized in that it includes a computer program, and when the computer program is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 11.
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