CN102222660B - Double-lead-frame multi-chip common package body and manufacturing method thereof - Google Patents

Double-lead-frame multi-chip common package body and manufacturing method thereof Download PDF

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Publication number
CN102222660B
CN102222660B CN201010167961.3A CN201010167961A CN102222660B CN 102222660 B CN102222660 B CN 102222660B CN 201010167961 A CN201010167961 A CN 201010167961A CN 102222660 B CN102222660 B CN 102222660B
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Prior art keywords
chip
contact zone
lead
brace
lead frame
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CN201010167961.3A
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CN102222660A (en
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刘凯
石磊
鲁军
安荷·叭剌
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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Alpha and Omega Semiconductor Ltd
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Abstract

The invention discloses a double-lead frame multi-chip common package body and a manufacturing method thereof. The common package body comprises two lead frames, a plurality of chips and two connecting plates, wherein the chips comprise a first chip, a second chip and a third chip; the first chip is arranged on a first lead frame; the second chip and the third chip are arranged on a second lead frame together; the third chip is a bypass capacitor; the connecting plates are respectively a top connecting plate and a stereo connecting plate; the top connecting plate is connected with a top contact region of the second chip and an external pin of the first lead frame, and the top connecting plate is simultaneously connected with a top contact region of the third chip. According to the invention, the manufacturing process of a multi-frame multi-chip package is simplified, the resistance and inductance among the chips are reduced, and the bypass capacitor is integrated in the package, the parasitic inductance in the packaging process is reduced, thus the energy conversion efficiency of a whole device is improved, the size of a semi-conductor package is reduced, additionally, the process provided by the invention is simple to operate and has low the manufacturing cost.

Description

Double-lead-frame multi-chip common package body and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor package and manufacture method, particularly a kind of Double-lead-frame multi-chip common package body and manufacture method thereof.
Background technology
Power MOSFET crystal (metal-oxide-semiconductor field effecttransistor, being called for short MOSFET) device has high density of integration, high reliability, extremely low static leakage current and the power handling capability of updating, is widely used in the field such as consumer electronics, computer.
In prior art, as shown in Figure 1, pipe mos field effect transistor (HSMOSFET) 2 and lower pipe mos field effect transistor (LS MOSFET) 1 o'clock in encapsulation, upper pipe MOSFET2 and lower pipe MOSFET 1 are separately positioned on a lead frame chip carrier 4 and chip carrier 3,5 connect respectively lower pipe MOSFET 1 and the contact zone, top of upper pipe MOSFET 2, lower pipe MOSFET 1 and contact zone, bottom and the chip carrier 3 of chip carrier 3 and upper pipe MOSFET 2 by going between.
In prior art, as shown in Figure 2, the electric capacity of surface installing type 11 is arranged on to the surface of semiconductor packages 12, to reduce stray inductance.
In the encapsulation of above-mentioned device, connect chip by lead-in wire, increase resistance and inductance between chip, in semiconductor package surface, capacitor is set in addition, increase size and the cost of semiconductor packages.
Summary of the invention
The object of this invention is to provide a kind of Double-lead-frame multi-chip common package body and manufacture method thereof, this encapsulating structure by brace for being connected between the connection between chip and chip and chip carrier, resistance and inductance between chip are reduced, an and integrated shunt capacitance in encapsulation, reduce the stray inductance in encapsulation process, improve the energy conversion efficiency of whole device, and reduced the size of semiconductor packages simultaneously, technological operation of the present invention is simple, easy to operate, low cost of manufacture.
In order to achieve the above object, technical scheme of the present invention is: a kind of Double-lead-frame multi-chip common package body, be characterized in, and comprising:
The first lead frame and the second lead frame, described the first lead frame comprises first chip carrier and multiple external pin, described the second lead frame comprises second chip carrier and a three-dimensional brace forming with the second chip carrier one;
There is respectively the first chip and second chip of contact zone, several top and a contact zone, bottom; Described the first chip is arranged on the first chip carrier, and described the second chip is arranged on the second chip carrier; The contact zone, bottom of described the first chip is electrically connected with the first chip carrier, and the contact zone, bottom of described the second chip is electrically connected with the second chip carrier;
Described three-dimensional brace connects one first contact zone, top of the first chip, and the first chip is connected with the second chip carrier electricity, thereby the first contact zone, top of the first chip and contact zone, the bottom electricity of the second chip are communicated with.
Above-mentioned Double-lead-frame multi-chip common package body, wherein,
Also comprise a top brace, described top brace connects a contact zone, top and at least one external pin of the second chip.
Above-mentioned Double-lead-frame multi-chip common package body, wherein,
Described top brace further extends one second contact zone, top that connects the first chip.
Above-mentioned Double-lead-frame multi-chip common package body, wherein,
Described multiple chip also comprises the 3rd chip with a contact zone, top and a contact zone, bottom, and described the 3rd chip is arranged on the first chip carrier, and the contact zone, bottom of described the 3rd chip is electrically connected with the first chip carrier; Described top brace further extends the contact zone, top that connects the 3rd chip.
Above-mentioned Double-lead-frame multi-chip common package body, wherein,
Described the first chip is upper pipe mos field effect transistor, and described the second chip is lower pipe mos field effect transistor, and described the 3rd chip is shunt capacitance.
A kind of Double-lead-frame multi-chip common package body, is characterized in, comprising:
Two lead frames, are respectively the first lead frame and the second lead frame, and described the first lead frame comprises first chip carrier and multiple external pin, and described the second lead frame comprises second chip carrier;
Multiple chips, described multiple chips have respectively contact zone, top and contact zone, bottom; Described multiple chip further comprises the first chip, the second chip and the 3rd chip; Described the first chip and the 3rd chip are arranged on the first chip carrier, described the second chip is arranged on the second chip carrier, the contact zone, bottom of described the first chip and the 3rd chip is connected with the first chip carrier electricity respectively, the contact zone, bottom of described the second chip is connected with the second chip carrier electricity, described the first chip and the second chip also comprise respectively top gate contact zone, and the gate contact zone of the first chip and the second chip is connected with the external pin of the first lead frame respectively;
A top brace, for the connection in multi-chip common package body, described top brace connects contact zone, top and the external pin of the second chip, and described top brace connects the contact zone, top of the 3rd chip simultaneously;
The contact zone, top of described the first chip is connected with described the second chip carrier electricity.
Above-mentioned Double-lead-frame multi-chip common package body, wherein, connects the contact zone, top of the first chip and the inside pin of the second lead frame by lead-in wire.
Above-mentioned Double-lead-frame multi-chip common package body, wherein, described the first chip and the 3rd integrated chip are that a chip is arranged on the first lead frame.
Above-mentioned Double-lead-frame multi-chip common package body, wherein, the first described chip is upper pipe mos field effect transistor, and described the second chip is lower pipe mos field effect transistor, and described the 3rd chip is shunt capacitance.
A manufacture method for Double-lead-frame multi-chip common package body, is characterized in, comprises the following steps:
Step 1: first lead frame is provided, and described the first lead frame comprises the first chip carrier and multiple external pin;
Step 2: multiple chips are provided, comprise the first chip and the second chip, described the first chip and the second chip comprise respectively contact zone, bottom and contact zone, top;
Step 3: described the first chip is arranged on the first chip carrier, and the contact zone, bottom of the first chip is connected by adhesives electricity with the first chip carrier;
Step 4: second lead frame and a three-dimensional brace are provided, described the second lead frame comprises second chip carrier, described the second chip carrier and the integrated shaped structure of described three-dimensional brace, three-dimensional brace connects the contact zone, top of the first chip;
Step 5: the second chip is arranged on the second chip carrier, and the contact zone, bottom of the second chip is connected with the second chip carrier electricity;
Step 6: a top brace is provided, and described top brace connects the contact zone, top of the second chip and the external pin of the first lead frame.
An encapsulation manufacturing method for Double-lead-frame multi-chip common package body, is characterized in, comprises the following steps:
Step 1: first lead frame is provided, and described the first lead frame comprises the first chip carrier and multiple external pin;
Step 2: multiple chips are provided, multiple chips comprise the first chip, the second chip and the 3rd chip, the first chip and the 3rd chip are arranged on the first chip carrier, described multiple chip all comprises respectively contact zone, bottom and contact zone, top, and the contact zone, bottom of the first chip and the 3rd chip is connected with the first chip carrier electricity;
Step 3: second lead frame is provided, and described the second lead frame comprises the second chip carrier, contact zone, top and second chip carrier of connection the first chip;
Step 4: the second chip is arranged on to the second chip carrier and draws, and described the second chip is connected with described the second chip carrier electricity;
Step 5: a top brace is provided, and top brace is connected to the contact zone, top of the second chip and the external pin of the first lead frame, and described top brace connects the contact zone, top of the 3rd chip simultaneously;
Step 6: the contact zone, top of the first chip and the second chip comprises a gate contact zone, the gate contact zone of the first chip and the second chip is connected with the external pin of the first lead frame respectively;
Step 7: clean lead frame, with plastic-sealed body encapsulating lead, brace and chip, the only external pin of exposed portions serve lead frame, electroplate pin.
The manufacture method of above-mentioned Double-lead-frame multi-chip common package body, wherein, in step 3, also comprise a three-dimensional brace, described three-dimensional brace and the integrated shaped structure of described the second chip carrier, or described three-dimensional brace is connected with described the second chip carrier electricity, described three-dimensional brace is connected with the contact zone, top of the first chip, thereby the contact zone, top of the first chip is connected with the second chip carrier electricity.
The encapsulation manufacturing method of above-mentioned Double-lead-frame multi-chip common package body, wherein, in step 3, also comprises multiple lead-in wires, connects contact zone, top and second chip carrier of the first chip by described lead-in wire.
The manufacture method of above-mentioned Double-lead-frame multi-chip common package body, wherein, in step 2, first by the first chip and the 3rd integrated chip in an integrated chip, then described integrated chip is arranged on the first lead frame.
The manufacture method of above-mentioned Double-lead-frame multi-chip common package body, wherein, further comprising the steps of in step 6:
A) on the grid of the grid of the first chip, the second chip, Reflow Soldering pellet forms salient point;
B) connect respectively gate contact zone on the first chip and the second chip and the external pin of the first lead frame with lead-in wire.
The manufacture method of above-mentioned Double-lead-frame multi-chip common package body, wherein, by adhesives, chip is arranged on chip carrier, and carry out being connected of brace and contact zone, chip top by adhesives, on described three-dimensional brace and top brace, multiple holes are set, by described multiple holes absorption adhesivess, make to stablize and be connected between the contact zone, top of brace and chip.
The manufacture method of above-mentioned Double-lead-frame multi-chip common package body, wherein, described the first chip is upper pipe mos field effect transistor, and described the second chip is lower pipe mos field effect transistor, and the 3rd described chip is shunt capacitance.
The manufacture method of above-mentioned Double-lead-frame multi-chip common package body, wherein, described the first lead frame and the as a whole framework of the second lead frame.
A kind of Double-lead-frame multi-chip common package body of the present invention and manufacture thereof, owing to adopting technique scheme, make it compared with prior art, have the following advantages and good effect:
1, the present invention connects the pin of two chips and lead frame simultaneously by a brace, has simplified manufacture craft.
2, the present invention, due to brace is used between chip and being connected between chip and chip carrier, has reduced resistance and inductance between chip, and has dwindled the distance between chip.
3, the present invention is due to an integrated shunt capacitance in the encapsulation of chip, thereby stray inductance is minimized, and improved the energy conversion efficiency of whole device.
4, the making of the technique of Double-lead-frame multi-chip common package body of the present invention is simple, easy to operate, low cost of manufacture.
Brief description of the drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.But appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 is the encapsulating structure schematic diagram of above managing MOSFET and lower pipe MOSET in prior art.
Fig. 2 is the structural representation that electric capacity is set in semiconductor package surface in prior art.
Fig. 3 is the structural representation of embodiment mono-Double-lead-frame multi-chip common package body.
Fig. 4 is the manufacture method flow chart of embodiment mono-Double-lead-frame multi-chip common package body
Fig. 5 is the structural representation of embodiment bis-Double-lead-frame multi-chip common package bodies.
Fig. 6 is the manufacture method flow chart of embodiment bis-Double-lead-frame multi-chip common package bodies.
The the first lead frame structure schematic diagram providing in the manufacture method process of Fig. 7 for embodiment bis-Double-lead-frame multi-chip common package bodies.
Fig. 8 is arranged on the structural representation on the first chip carrier by the first chip and the 3rd chip in the manufacture method process of embodiment bis-Double-lead-frame multi-chip common package bodies.
Fig. 9 is the second chip carrier of integral forming in the manufacture method process of embodiment bis-Double-lead-frame multi-chip common package bodies and the structural representation of three-dimensional brace.
Figure 10 is the structural representation of second chip and top brace in the manufacture method process of embodiment bis-Double-lead-frame multi-chip common package bodies.
Figure 11 is the structural representation of embodiment tri-Double-lead-frame multi-chip common package bodies.
Figure 12 is the structural representation of embodiment tetra-Double-lead-frame multi-chip common package bodies.
Figure 13 is the manufacture method flow chart of embodiment tetra-Double-lead-frame multi-chip common package bodies.
Embodiment
Embodiment mono-, as shown in Figure 3, a kind of Double-lead-frame multi-chip common package body, comprises two lead frames, two chips and two braces.Two lead frames are respectively the first lead frame 101 and the second lead frame 102, the first lead frame 101 comprises the first chip carrier 110 and multiple external pin 111,112,113,114 and multiple inner pin (option, in figure, do not show), multiple external pins are for connection corresponding to inside chip, when practical application, can increase on demand or reduce; The second lead frame 102 comprises the second chip carrier 120 and multiple inner pin (not showing in optional term diagram) and multiple muscle 121,122 that connects, and connects muscle 121,122 for the connection between lead frame, lead frame is erected to reinforcement effect simultaneously.Multiple chips have respectively contact zone, top (not shown) and contact zone, bottom (not shown), and two chips are respectively the first chip 130 and the second chip 140; By adhesives, preferably as by conducting resinl or solder(ing) paste, the first chip 130 being arranged on the first chip carrier 110, same, by adhesives, the second chip 140 is arranged on the second chip carrier 120; The contact zone, bottom of the first chip 130 is connected with external pin 112 electricity of the first lead frame 101, and the contact zone, bottom of the second chip 140 is connected with the second chip carrier 120 electricity.Brace is for the connection in multi-chip common package body, two braces comprise three-dimensional brace 150 and top brace 160, preferably, three-dimensional brace 150 and the integrated shaped structure of the second chip carrier 120, it is a part of the second lead frame 102, or three-dimensional brace 150 is connected with the second chip carrier 120 electricity; Connect the contact zone, top of the first chip 130 by the three-dimensional brace 150 of cementation of electrically conductive binding material simultaneously, the first chip 130 is connected with the second chip carrier 120 electricity, because the second chip 140 is connected with the second chip carrier 120 electricity, thereby be communicated with the second chip 140 electricity by three-dimensional brace 150 and the second chip carrier 120, the first chips 130.Top brace 160 connects the contact zone, top of the second chip 140 and 110 external pins 114 of the first chip carrier, preferably, the first chip 130 is upper pipe mos field effect transistor, and the second chip 140 is lower pipe mos field effect transistor.In the present embodiment, three-dimensional brace 150 and top brace 160, dwindle on the one hand the distance between upper pipe mos field effect transistor and lower pipe mos field effect transistor, inductance and resistance between chip are reduced on the other hand, wherein due to three-dimensional brace 150 and the second chip carrier 120 integrally formed, guarantee stable connection between three-dimensional brace 150 and the second chip carrier 120, the present embodiment has been enumerated the encapsulation of two chips, in actual package process, multiple chips can be set on Double-lead-frame, connect each chip by brace, realize the common encapsulation of Double-lead-frame multi-chip, manufacture craft is simple and convenient.
Double-lead-frame multi-chip common package body is in manufacturing process, as shown in Figure 4, comprise following step: first, first lead frame 101 is provided, the first lead frame 101 comprises chip carrier 110 and multiple external pin 111,112,113,114, also optionally comprises multiple inner pin (not shown); Multiple chips are provided simultaneously, comprise the first chip 130 and the second chip 140, preferably, the first chip 130 is upper pipe mos field effect transistor, the second chip 140 is lower pipe mos field effect transistor, and the first chip 130 and the second chip 140 comprise respectively contact zone, bottom and contact zone, top; Secondly, by electrically conductive binding material, the first chip 130 is arranged on the first chip carrier 110, the contact zone, bottom of the first chip 130 is connected with the first chip carrier electricity, and draws by the external pin 112 that connects the first chip carrier 110; Then, second lead frame 102 and a three-dimensional brace 150 are provided, the second lead frame 102 comprises chip carrier 120, also can comprise the multiple muscle 121,122 that connect of multiple inner pin (not shown), preferably, the second chip carrier 120 and the integrated shaped structure of three-dimensional brace 150, it is a part of the second lead frame 102, or three-dimensional brace 150 is connected with the second chip carrier 120 electricity, three-dimensional brace 150 connects the contact zone, top of the first chip 130 by electrically conducting adhesive; Then, by electrically conductive binding material, for example, by conducting resinl or solder(ing) paste, the second chip 140 is arranged on the second chip carrier 120, the contact zone, bottom of the second chip 140 is connected with the second chip carrier 120 electricity; Finally, provide a top brace 160, top brace 160 connects the contact zone, top of the second chip 140 and the external pin 114 of the first lead frame 101.
Embodiment bis-, as shown in Figure 5, a kind of Double-lead-frame multi-chip common package body, comprises two lead frames, three chips and two braces.Two lead frames are respectively the first lead frame 201 and the second lead frame 202, the first lead frame 201 comprises the first chip carrier 210 and multiple external pin 211,212,213,214,215 and multiple inner pin (not shown) optionally, multiple external pins are for connection corresponding to inside chip, when practical application, can increase on demand or reduce; The second lead frame 202 comprise the second chip carrier 220 and optionally multiple inner pin (not shown) and multiple connect muscle 221,222, connect muscle 221,222 for the connection between lead frame, lead frame is erected to reinforcement effect simultaneously.Multiple chips have respectively contact zone, top and contact zone, bottom, and multiple chips comprise the first chip 230, the second chip 240 and the 3rd chip 250; The first chip 230 and the 3rd chip 250 are arranged on the first chip carrier 210 by electrically conductive binding material, by electrically conductive binding material, the second chip 240 are arranged on the second chip carrier 220 equally, and preferably, electrically conductive binding material is tinol or conducting resinl.The contact zone, bottom of the first chip 230 and the 3rd chip 250 is connected with external pin 212,213 electricity of the first chip carrier 210 respectively, and the contact zone, bottom of the second chip 240 is connected with the second chip carrier 220 electricity; The first chip 230 and the second chip 240 also comprise respectively gate contact zone 2311,2411, the gate contact zone 2311,2411 of the first chip 230 and the second chip 240 is connected with external pin 211,214 electricity of the first chip carrier 210 respectively, preferably, the gate contact zone 2311,2411 of the first chip 230 and the second chip 240 is connected with the external pin 211,214 of the first lead frame 210 respectively by lead-in wire 280.Two braces are respectively three-dimensional brace 260 and top brace 270, on three-dimensional brace 260 and top brace 270, be respectively equipped with multiple holes 261, 271, multiple holes 261, 271 for adsorbing adhesives, make stable connection between the contact zone, top of brace and chip, preferably, three-dimensional brace 260 and the second chip carrier 220 are one-body molded, it is a part of the second lead frame 202, or three-dimensional brace 260 is connected with the second chip carrier 220 electricity, three-dimensional brace 260 connects the contact zone, top of the first chip 230, thereby the contact zone, top of the first chip 230 is connected with the second chip carrier 220 electricity, top brace 270 is for the connection in multi-chip common package body, top brace 270 connects the contact zone, top of the second chip 220 and the external pin 215 of the first lead frame 201, and top brace 270 connects the contact zone, top of the 3rd chip 250 simultaneously, preferably, the first chip 230 is upper pipe mos field effect transistor, the second chip 240 is lower pipe mos field effect transistor, the 3rd chip 250 is shunt capacitance, shunt capacitance 250 is for reducing stray inductance, in the present embodiment, three-dimensional brace 260 and top brace 270, dwindle on the one hand the distance between upper pipe mos field effect transistor and lower pipe mos field effect transistor, inductance and resistance between chip have been reduced on the other hand simultaneously, wherein due to three-dimensional brace 260 and the second chip carrier 220 integrally formed, stable connection between three-dimensional brace 260 and the second chip carrier 220, in addition, shunt capacitance reduces the stray inductance in circuit, improve the energy conversion efficiency of whole device, the present embodiment has been enumerated the encapsulation of two chips, in actual package process, multiple chips can be set on Double-lead-frame, connect each chip by brace, realize the common encapsulation of Double-lead-frame multi-chip.
Double-lead-frame multi-chip common package body is in the time of manufacturing process, as shown in Fig. 6-10, comprise the following steps, as shown in Figure 7, first first lead frame 201 is provided, the first lead frame 201 comprises the first chip carrier 210 and multiple external pin 211,212,213,214,215, also optionally comprises multiple inner pin (not shown), next provides multiple chips, multiple chips comprise the first chip 230, the second chip 240 and the 3rd chip 250, preferably, the first chip 230 is upper pipe mos field effect transistor, the second chip 240 is lower pipe mos field effect transistor, the 3rd chip 250 is shunt capacitance, the first chip 230, the second chip 240 and the 3rd chip 250 all comprise respectively bottom contact zone (not shown) and contact zone, top 231, 241, 251, as shown in Figure 8, the first chip 230 and the 3rd chip 250 are arranged on the first chip carrier 210, preferably, pass through bonding agent, for example by conducting resinl or solder(ing) paste, the first chip 230 and the 3rd chip 250 are arranged on the first chip carrier 210, the contact zone, bottom of the first chip 230 and the 3rd chip 250 is connected with the first chip carrier 210 electricity simultaneously, again, as shown in Figure 9, second lead frame 202 and a three-dimensional brace 260 are provided, preferably, three-dimensional brace 260 and the integrated shaped structure of the second chip carrier 220, or three-dimensional brace 260 is connected with the second chip carrier 220 electricity, the second lead frame 202 comprises multiple muscle 221 that connect, 222, three-dimensional brace 260 is provided with multiple holes 261, at hole site absorption bonding agent, by bonding agent, three-dimensional brace 260 is connected with the contact zone, top 231 of the first chip 230, preferably, three-dimensional brace 260 is connected with the contact zone, source of the first chip 230, thereby the contact zone, top of the first chip 230 is connected with the second chip carrier 220 electricity, then, as shown in figure 10, the second chip 240 is arranged on the second chip carrier 220, and the contact zone, bottom of the second chip 240 is connected with the second chip carrier 220 electricity, then a top brace 270 is provided, top brace 270 is provided with multiple holes 271, at the position in multiple holes 271 absorption bonding agent, thereby connect the contact zone, top of top brace 270 and the second chip, top brace 270 connects the external pin 215 of the first lead frame 201 and the contact zone, top 251 of the 3rd chip 250 simultaneously, then, in the gate contact zone of the first chip and the second chip, 2311,2411 place reflux solder balls form salient points, 280 respectively the gate contact zone of the first chip and the second chip 2311,2411 are connected on the pin 211,214 of the first lead frame by going between, finally, clean plastic-sealed body encapsulated core bar used for lead frame, brace and chip, only the external pin of exposed portions serve lead frame and plating pin.
Embodiment tri-, as described in Example 11, a kind of Double-lead-frame multi-chip common package body, comprise two lead frames, two braces and three chips, two lead frames are respectively the first lead frame 301 and the second lead frame 302, two braces are respectively three-dimensional brace 350 and top brace 360, three chips are respectively the first chip, the second chip 340 and the 3rd chip, preferably, pipe mos field effect transistor on the first chip, the second chip 340 is lower pipe mos field effect transistor, the 3rd chip is shunt capacitance, as shown in figure 10, embodiment tri-and embodiment bis-are basic identical, difference is, first upper pipe mos field effect transistor and shunt capacitance are integrated into a chip 330 and are arranged on the first chip carrier 310, upper pipe mos field effect transistor and shunt capacitance are integrated on an integrated chip, reduce the stray inductance of chip, improve the energy conversion efficiency of whole device, and improve the integrated level of chip package.
Embodiment tetra-, as shown in figure 12, a kind of Double-lead-frame multi-chip common package body, comprises two lead frames, three chips and a brace.Two lead frames are respectively the first lead frame 401 and the second lead frame 402, preferably, two parts of the first lead frame and the as a whole substrate of the second lead frame, whole substrate can comprise multiple parts, the first lead frame 401 comprises the first chip carrier 410 and multiple external pin 411,412,413,414,415, also optionally comprise multiple inner pin (not shown), the second lead frame 402 comprises the second chip carrier 420 and multiple muscle 421,422 that connects, and also can comprise multiple inner pin (not shown).Multiple chips have respectively contact zone, top and contact zone, bottom, and multiple chips comprise the first chip 430, the second chip 440 and the 3rd chip 450; Preferably, the first chip 430 is upper pipe mos field effect transistor, and the second chip 440 is lower pipe mos field effect transistor, and the 3rd chip 450 is shunt capacitance.The first chip 430 and the 3rd chip 450 are arranged on the first chip carrier 410 by adhesives, the second chip 440 is arranged on the second chip carrier 420 by adhesives, the contact zone, bottom of the first chip 430 and the 3rd chip 450 is connected with the first chip carrier 410 electricity respectively, the contact zone, bottom of the second chip 440 is connected with the second chip carrier 420 electricity, the first chip 430 and the second chip 440 also comprise respectively gate contact zone 4311, 4411, the gate contact zone 4311 of the first chip 430 and the second chip 440, 4411 respectively with the external pin 411 of the first lead frame 401, 414 electricity connect, preferably, the gate contact zone 4311 of the first chip 430 and the second chip 440, 4411 by lead-in wire 480 respectively with the external pin 411 of the first chip carrier 410, 414 connect.A brace is top brace 460, and top brace 460 is provided with multiple holes 461, and multiple holes 461 are for adsorbing adhesives, thereby better connects the contact zone, top of top brace 460 and the second chip 420; Top brace 460 connects the contact zone, top of the second chip 420 and the external pin 415 of the first lead frame 401, and top brace 460 connects the contact zone, top of the 3rd chip 450 simultaneously; The contact zone, top 4312 of the first chip 430 is connected with the second chip carrier 420 electricity by lead-in wire 470, thereby the first chip 430 is connected with the second chip 420 electricity, in the present embodiment, top brace 460 is for being connected between chip and between chip and chip carrier, reduce the inductance between chip, improve the stability connecting, between local chip, connected by lead-in wire, improved the flexibility that chip connects simultaneously.
The manufacturing process of Double-lead-frame multi-chip common package body, comprise the following steps, first a monolith substrate is provided, monolith substrate comprises the first lead frame 401 and the second lead frame 402, the first lead frame 401 comprises the first chip carrier 410 and multiple external pin 411, 412, 413, 414, 415, also can comprise multiple inner pin (not shown), the second lead frame 402 comprises the second chip carrier 420 and multiple muscle 421 that connects, 422, also can comprise multiple inner pin (not shown), preferably, the first lead frame 401 and the as a whole framework of the second lead frame 402, then multiple chips are provided, multiple chips comprise the first chip 430, the second chip 440 and the 3rd chip 450, preferably, the first chip 430 is upper pipe mos field effect transistor, the second chip 440 is lower pipe mos field effect transistor, the 3rd chip 450 is shunt capacitance, the first chip 430 and the 3rd chip 450 are arranged on the first chip carrier 410, preferably, pass through binding agent, for example by conducting resinl or solder(ing) paste, the first chip 430 and the 3rd chip 450 are arranged on the first chip carrier 410, contact zone, the bottom electricity of the first chip 430 and the 3rd chip 450 is connected to the first chip carrier 410 and external pin 412 simultaneously, 413 electricity connect, again, contact zone, top by 470 connection the first chips 430 that go between and the second chip carrier or the inside pin (not shown) being connected with the second chip carrier electricity, then, the second chip 440 is arranged on the second chip carrier, and the second chip 440 is connected with the second chip carrier 420 electricity, a top brace 460 is then provided, top brace 460 is provided with multiple holes 461, adhesives is adsorbed in multiple holes 461, connect the contact zone, top of top brace 460 and the second chip 440, top brace 460 is connected to the contact zone, top of the second chip 440 and the external pin 415 of the first lead frame 401, and top brace 460 connects the contact zone, top of the 3rd chip 450 simultaneously, then, 480 respectively the gate contact zone of the first chip 430 and the second chip 440 4311,4411 is connected on the pin 411,414 of the first lead frame by going between, finally, clean lead frame, with plastic-sealed body encapsulated core bar, brace and chip, the only external pin of exposed portions serve lead frame, electroplates pin.
Certainly, must recognize, above-mentioned introduction is the explanation about the preferred embodiment of the present invention, and only otherwise depart from the shown spirit and scope of claims subsequently, the present invention also exists many amendments.
The present invention is only confined to the shown details of above-mentioned explanation or accompanying drawing and method anything but.The present invention can have other embodiment, and can adopt various ways to be implemented.In addition, everybody also must recognize, the wording that used here and term and digest, just in order to realize the object of introduction, are only confined to this anything but.
Just because of this, one skilled in the art will appreciate that the present invention based on viewpoint can be used as at any time and implement several targets of the present invention and design other structure, method and system.So, it is essential, appended claim is by the construction that is regarded as having comprised that all these are of equal value, as long as they are without departing from the spirit and scope of the present invention.

Claims (14)

1. a Double-lead-frame multi-chip common package body, is characterized in that, comprising:
The first lead frame and the second lead frame, described the first lead frame comprises first chip carrier and multiple external pin, described the second lead frame comprises second chip carrier and a three-dimensional brace forming with the second chip carrier one, and this solid brace is a part of the second lead frame;
There is respectively the first chip and second chip of contact zone, several top and a contact zone, bottom; Described the first chip is arranged on the first chip carrier, and described the second chip is arranged on the second chip carrier; The contact zone, bottom of described the first chip is electrically connected with the first chip carrier, and the contact zone, bottom of described the second chip is electrically connected with the second chip carrier;
Described three-dimensional brace connects one first contact zone, top of the first chip, and the first chip is connected with the second chip carrier electricity, thereby the first contact zone, top of the first chip and contact zone, the bottom electricity of the second chip are communicated with.
2. Double-lead-frame multi-chip common package body according to claim 1, is characterized in that,
Also comprise a top brace, described top brace connects a contact zone, top and at least one external pin of the second chip.
3. Double-lead-frame multi-chip common package body according to claim 2, is characterized in that,
Described top brace further extends one second contact zone, top that connects the first chip.
4. Double-lead-frame multi-chip common package body according to claim 2, is characterized in that,
Also comprise the 3rd chip with a contact zone, top and a contact zone, bottom, described the 3rd chip is arranged on the first chip carrier, and the contact zone, bottom of described the 3rd chip is electrically connected with the first chip carrier; Described top brace further extends the contact zone, top that connects the 3rd chip.
5. Double-lead-frame multi-chip common package body according to claim 4, is characterized in that,
Described the first chip is upper pipe mos field effect transistor, and described the second chip is lower pipe mos field effect transistor, and described the 3rd chip is shunt capacitance.
6. a Double-lead-frame multi-chip common package body, is characterized in that, comprising:
Two lead frames, be respectively the first lead frame and the second lead frame, described the first lead frame comprises first chip carrier and multiple external pin, described the second lead frame comprises second chip carrier and a three-dimensional brace forming with the second chip carrier one, and this solid brace is a part of the second lead frame;
Multiple chips, described multiple chips have respectively contact zone, top and contact zone, bottom; Described multiple chip further comprises the first chip, the second chip and the 3rd chip; Described the first chip and the 3rd chip are arranged on the first chip carrier, described the second chip is arranged on the second chip carrier, the contact zone, bottom of described the first chip and the 3rd chip is connected with the first chip carrier electricity respectively, the contact zone, bottom of described the second chip is connected with the second chip carrier electricity, described the first chip and the second chip also comprise respectively top gate contact zone, and the gate contact zone of the first chip and the second chip is connected with the external pin of the first lead frame respectively;
A top brace, for the connection in multi-chip common package body, described top brace connects contact zone, top and the external pin of the second chip, and described top brace connects the contact zone, top of the 3rd chip simultaneously;
Described three-dimensional brace connects the contact zone, top of the first chip, and the contact zone, top of described the first chip is connected with described the second chip carrier electricity.
7. Double-lead-frame multi-chip common package body according to claim 6, is characterized in that, described the first chip and the 3rd integrated chip are that a chip is arranged on the first lead frame.
8. according to the Double-lead-frame multi-chip common package body described in claim 6 or 7, it is characterized in that, the first described chip is upper pipe mos field effect transistor, described the second chip is lower pipe mos field effect transistor, and described the 3rd chip is shunt capacitance.
9. a manufacture method for Double-lead-frame multi-chip common package body, is characterized in that, comprises the following steps:
Step 1: first lead frame is provided, and described the first lead frame comprises the first chip carrier and multiple external pin;
Step 2: multiple chips are provided, comprise the first chip and the second chip, described the first chip and the second chip comprise respectively contact zone, bottom and contact zone, top;
Step 3: described the first chip is arranged on the first chip carrier, and the contact zone, bottom of the first chip is connected by adhesives electricity with the first chip carrier;
Step 4: second lead frame and a three-dimensional brace are provided, described the second lead frame comprises second chip carrier, described the second chip carrier and the integrated shaped structure of described three-dimensional brace, this solid brace is a part of the second lead frame, and three-dimensional brace connects the contact zone, top of the first chip;
Step 5: the second chip is arranged on the second chip carrier, and the contact zone, bottom of the second chip is connected with the second chip carrier electricity;
Step 6: a top brace is provided, and described top brace connects the contact zone, top of the second chip and the external pin of the first lead frame.
10. an encapsulation manufacturing method for Double-lead-frame multi-chip common package body, is characterized in that, comprises the following steps:
Step 1: first lead frame is provided, and described the first lead frame comprises the first chip carrier and multiple external pin;
Step 2: multiple chips are provided, multiple chips comprise the first chip, the second chip and the 3rd chip, the first chip and the 3rd chip are arranged on the first chip carrier, described multiple chip all comprises respectively contact zone, bottom and contact zone, top, and the contact zone, bottom of the first chip and the 3rd chip is connected with the first chip carrier electricity;
Step 3: second lead frame is provided, described the second lead frame comprises the second chip carrier and a three-dimensional brace forming with the second chip carrier one, this solid brace is a part of the second lead frame, described three-dimensional brace is connected with the contact zone, top of the first chip, thereby the contact zone, top of the first chip is connected with the second chip carrier electricity;
Step 4: the second chip is arranged on the second chip carrier, and described the second chip is connected with described the second chip carrier electricity;
Step 5: a top brace is provided, and top brace is connected to the contact zone, top of the second chip and the external pin of the first lead frame, and described top brace connects the contact zone, top of the 3rd chip simultaneously;
Step 6: the contact zone, top of the first chip and the second chip comprises a gate contact zone, the gate contact zone of the first chip and the second chip is connected with the external pin of the first lead frame respectively;
Step 7: clean lead frame, with plastic-sealed body encapsulating lead, brace and chip, the only external pin of exposed portions serve lead frame, electroplate pin.
The manufacture method of 11. Double-lead-frame multi-chip common package bodies according to claim 10, it is characterized in that, in step 2, first by the first chip and the 3rd integrated chip in an integrated chip, then described integrated chip is arranged on the first lead frame.
12. according to the manufacture method of the Double-lead-frame multi-chip common package body described in claim 10 or 11, it is characterized in that, further comprising the steps of in step 6:
A) on the grid of the grid of the first chip, the second chip, Reflow Soldering pellet forms salient point;
B) connect respectively gate contact zone on the first chip and the second chip and the external pin of the first lead frame with lead-in wire.
The manufacture method of 13. Double-lead-frame multi-chip common package bodies according to claim 10, it is characterized in that, by adhesives, chip is arranged on chip carrier, and carry out being connected of brace and contact zone, chip top by adhesives, on described three-dimensional brace and top brace, multiple holes are set, by described multiple holes absorption adhesivess, make to stablize and be connected between the contact zone, top of brace and chip.
The manufacture method of 14. Double-lead-frame multi-chip common package bodies according to claim 10, it is characterized in that, described the first chip is upper pipe mos field effect transistor, described the second chip is lower pipe mos field effect transistor, and the 3rd described chip is shunt capacitance.
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