CN103646941B - A kind of encapsulating structure for DC-to-DC converter - Google Patents
A kind of encapsulating structure for DC-to-DC converter Download PDFInfo
- Publication number
- CN103646941B CN103646941B CN201310724835.7A CN201310724835A CN103646941B CN 103646941 B CN103646941 B CN 103646941B CN 201310724835 A CN201310724835 A CN 201310724835A CN 103646941 B CN103646941 B CN 103646941B
- Authority
- CN
- China
- Prior art keywords
- chip
- controller
- encapsulating structure
- metal layer
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention relates to a kind of encapsulating structure for DC-to-DC converter, belong to technical field of semiconductor encapsulation.It comprises the HS chip (200) of the formation DC-to-DC converter of the central authorities being arranged at (100) at the bottom of silicon wafer-based, LS chip (300) and controller (400), the surface of (100) at the bottom of silicon wafer-based arranges the interconnection metal layer again (500) of sensible HS chip (200), LS chip (300) and controller (400), described HS chip (200) and LS chip (300) are connected with interconnection metal layer (500) again by the mode of paster, controller (400) by metal coupling I (410) upside-down mounting on the interconnection metal layer again (500) of correspondence.The present invention adopts Wiring technique and upside-down mounting, mounting method again, and simplify encapsulating structure, reduce interconnection resistance, the package dimension of acquisition is less, thinner, improves chip interconnect reliability, enhances the stability of encapsulating structure.
Description
Technical field
The present invention relates to a kind of encapsulating structure for DC-to-DC converter, belong to technical field of semiconductor encapsulation.
Background technology
DC-to-DC converter is voltage regulator input direct voltage being converted to adjusted output dc voltage.Due to, the input voltage applied may change because of a variety of causes, and how DC-to-DC converter changes regardless of these in input voltage, be held in consistent level all will to the voltage of each internal circuitry.
The high side switch transistor be connected between input voltage and phase node and the low side switch transistor be connected between phase node and ground connection is generally included in DC-to-DC converter.As shown in Figure 1, be the circuit theory diagrams of DC-to-DC (DC-DC) transducer be connected to form by 2 N-type MOSFET (metal oxide semiconductor field effect tube).Its middle and high end MOSFET (is called for short: grid G 1 HS) and low side MOSFET (are called for short: grid G 2 LS) is all connected with an IC controller; The drain D 1 of high-end MOSFET connects Vin end, and its source S 1 connects the drain D 2 of low side MOSFET, and the source S 2 of low side MOSFET connects Gnd end.Generally between the Vin-Gnd two ends of DC-to-DC converter, be also provided with the components and parts such as electric capacity, inductance.
Traditional encapsulating structure for DC-to-DC converter, by HS chip (high-end MOSFET chip) 200, LS chip (low side MOSFET chip) 300 and controller 400 are formed, and be encapsulated on lead frame 100, as shown in Figure 2, three passes through QFN(QuadFlatNoLead, the semiconductor chip package of four limit flat non-pins) packaged type completes, QFN packing forms is based on lead frame, introduce the multi-level Ji Dao formed, Ji Dao carries HS chip 200 respectively, LS chip 300 and controller 400, wherein, HS chip 200, part between LS chip 300 and controller 400 connects by the realization of lead-in wire (lead-in wire 610) bonding pattern, the part annexation of HS chip 200 and LS chip 300 realizes from HS chip 200 and LS chip 300 top by having certain thickness metallic interconnect 500, is called band bonding packaging mode.This kind of encapsulating structure exists following not enough:
1, have employed the mixed form of wire bonding and band bonding, not only complex process, especially band bonding technology is difficult to control, and make traditional encapsulating structure stacked in multi-layers for DC-to-DC converter, also need the lead-in wire 610 for having loop height to retain enough guard spaces in addition, therefore, the whole encapsulating structure for DC-to-DC converter is complicated, size is thicker, general at about 1000um, do not meet the packaging trend of slimming, be unfavorable for the heat radiation of system yet;
The interconnected many places of the chip chamber of 2, traditional encapsulating structure for DC-to-DC converter adopt wire bonding, and go between 610 elongated shape often cause interconnection resistance larger, reduce final output current to a certain extent, have impact on interconnected reliability;
3, QFN encapsulation is based on copper lead frame, and production cost is high.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, the encapsulating structure for DC-to-DC converter that a kind of package dimension is less, thinner, reduce interconnection resistance, promote chip interconnect reliability, strengthen encapsulating structure stability is provided.
The present invention is achieved in that
A kind of encapsulating structure for DC-to-DC converter of the present invention, comprises DC-to-DC converter, and described DC-to-DC converter is made up of HS chip, LS chip and controller.
A kind of encapsulating structure for DC-to-DC converter of the present invention, also comprise at the bottom of silicon wafer-based, described HS chip, LS chip and controller are laid in the central authorities at the bottom of silicon wafer-based, surface at the bottom of described silicon wafer-based arranges the interconnection metal layer again of sensible HS chip, LS chip and controller, described HS chip and LS chip are electrically connected by the mode of paster and interconnection metal layer again
The pin of described controller arranges several metal couplings I, and described controller passes through metal coupling I upside-down mounting on the interconnection metal layer again of correspondence;
The grid of described HS chip passes through interconnection metal layer and controller again and is electrically connected, and the drain electrode that its source electrode passes through interconnection metal layer and LS chip is again electrically connected, its drain electrode access input voltage VIN;
The interconnection metal layer again of the periphery of described controller arranges metal coupling II, and soldered ball I is set on metal coupling II;
The grid of described LS chip is connected with controller by the internal wiring of external substrate or circuit board 800, its source ground.
Alternatively, described HS chip and controller are arranged at the side of LS chip.
Alternatively, the direction of described HS chip paster is contrary with the direction of LS chip paster.
Alternatively, the height after HS chip and LS chip paster keeps flushing, and keeps flushing with the height of soldered ball I after the backflow on interconnection metal layer again or a little less than the height of the soldered ball I afterwards of refluxing.
Alternatively, the height after described HS chip and LS chip paster is higher than the height after controller upside-down mounting.
Alternatively, the bottom space of the described controller after upside-down mounting is filled the end and is filled out agent.
Alternatively, described in adjacent, the line-spacing of interconnection metal layer is not less than 30um again.
Alternatively, described metal coupling I comprises copper post and tin cap.
Alternatively, the altitude range of described metal coupling I: 30-80um.
Alternatively, also comprise the soldered ball II being arranged at periphery, the interconnection metal layer again below described soldered ball II is discrete shape.
Structural advantage of the present invention be chip chamber interconnected be the use of connect up again and mount, the packaged type of upside-down mounting, instead of the packaged type that traditional QFN adds wire bonding and band bonding; Attachment or the packaged type of upside-down mounting increase the contact area of HS chip, LS chip and controller and wiring metal again, reduce interconnection resistance, expand heat dissipation channel; To replace copper lead frame at the bottom of the silicon wafer-based of super quality and competitive price, save production cost.
The invention has the beneficial effects as follows:
1, the present invention be used for the encapsulating structure of DC-to-DC converter HS chip, adopt between LS chip and controller connect up again and mount, the packaged type of upside-down mounting realizes interconnected, increase contact area, reduce interconnection resistance, expand heat dissipation channel, contribute to the stability and the reliability that improve encapsulating structure;
2, the present invention is used for the structural relation that the encapsulating structure of DC-to-DC converter simplifies interconnected, reduces and is thinned package dimension, being conducive to the integrated development of substrate or circuit structure, being more conducive to the development of portable type electronic product;
3, the present invention is used for being encapsulated in same packaging body by multiple component chip at the bottom of the silicon wafer-based of the encapsulating structure employing super quality and competitive price of DC-to-DC converter, simplifies encapsulation process, has saved cost.
Accompanying drawing explanation
Fig. 1 is the schematic block circuit diagram of DC-to-DC (DC-DC) transducer;
Fig. 2 is the schematic diagram of traditional encapsulating structure for DC-to-DC converter;
Fig. 3 is the total arrangement schematic diagram of a kind of encapsulating structure for DC-to-DC converter of the present invention;
Fig. 4 is the A-A generalized section of a kind of encapsulating structure for DC-to-DC converter of the present invention;
Fig. 5 is the enlarged diagram of the local I of Fig. 4;
The generalized section of the application of a kind of encapsulating structure for DC-to-DC converter of Fig. 6 the present invention;
Wherein:
At the bottom of silicon wafer-based 100
HS chip 200
LS chip 300
Controller 400
Metal coupling I 410
Metal coupling II 420
Interconnection metal layer 500 again
Agent 600 is filled out at the end
Soldered ball I 710
Soldered ball II 720
Circuit board 800
Soldering-tin layer 810.
Embodiment
See Fig. 3 to Fig. 6, a kind of encapsulating structure for DC-to-DC converter of the present invention, the DC-to-DC converter be made up of HS chip 200, LS chip 300 and controller 400 at the bottom of silicon wafer-based 100 plane central be arranged in parallel.The LS chip 300 that wherein individual size is slightly larger than HS chip 200 is positioned at the side of 100 central authorities at the bottom of silicon wafer-based, and HS chip 200 and controller 400 are positioned at the opposite side of 100 central authorities at the bottom of silicon wafer-based.HS chip 200, LS chip 300 all have bottom drain, top source electrode and top grid.The periphery of controller 400 is provided with the pin that several have function.
As shown in Figure 3, the surface employing semiconductor of 100 at the bottom of the silicon wafer-based of a kind of encapsulating structure for DC-to-DC converter of the present invention again Wiring technique arranges the interconnection metal layer again 500 of sensible HS chip 200, LS chip 300 and controller 400, then interconnection metal layer 500 is by single or multiple lift metal level Organic structure.The line-spacing of adjacent interconnection metal layer again 500 does not interfere with each other each other with adjacent interconnection metal layer again 500 and is as the criterion.HS chip 200 and LS chip 300 are formed by the mode of paster and interconnection metal layer 500 again and are electrically connected.Because HS chip 200, LS chip 300 all have bottom drain, top source electrode and top grid, in order to realize forming series relationship between the two after paster, the direction of HS chip 200 paster is contrary with the direction of LS chip 300 paster.Usually, source electrode and the grid of LS chip 300 face up, and source electrode and the grid of HS chip 200 face down.
Particularly, as shown in Figure 4, the pin of controller 400 arranges metal coupling I 410, metal coupling I 410 is generally copper post and tin cap, and tin cap strengthens the adhesion of controller 400 and copper post.The altitude range of metal coupling I 410: 30-80um, to control the height of the controller after upside-down mounting 400, makes it not higher than the height after HS chip 200 and LS chip 300 paster.Controller 400 forms electric connection by metal coupling I 410 upside-down mounting on the interconnection metal layer again 500 of correspondence, and agent 600 is filled out at the end such as bottom space filling gel, epoxy resin of the described controller 400 after upside-down mounting.
The interconnection metal layer again 500 of the periphery of controller 400 arranges metal coupling II 420, and soldered ball I 710 is set on metal coupling II 420, the inside pin function of controller 400 is transferred to external pin soldered ball I 710 place of encapsulating structure, as shown in Figure 3.
The source electrode of HS chip 200 and grid face down and are bondingly pasted on interconnection metal layer 500 again, the grid of HS chip 200 passes through interconnection metal layer 500 again and is connected with controller 400, formed and be electrically connected, its source electrode passes through interconnection metal layer 500 again and is connected with the drain electrode of LS chip 300, its drain electrode access input voltage VIN.
Source electrode and the grid of LS chip 300 face up, its drain electrode is bondingly pasted on interconnection metal layer 500 again, its drain electrode to be formed with the source electrode of HS chip 200 by interconnection metal layer again 500 and is electrically connected, its source ground, the grid of LS chip 300 is connected with controller 400 by the internal wiring of the circuit board such as external substrate or PCB 800, as shown in Figure 6.
The components and parts such as electric capacity, inductance are also provided with between the Vin-Gnd two ends of DC-to-DC converter.
The periphery of a kind of encapsulating structure for DC-to-DC converter of the present invention is also provided with some special soldered balls II 720, and as shown in Figure 3 and Figure 4, it is also supported by metal coupling II 420, but the interconnection metal layer again 500 below it is in discrete shape.When the encapsulating structure upside-down mounting for DC-to-DC converter is to substrate or circuit board 800, these soldered balls II 720 mainly work the balance maintaining the encapsulating structure being used for DC-to-DC converter, to improve package reliability.By legal layout, adjust again the inside cabling of interconnection metal layer 500, maximally utilise the soldered ball I 710 of periphery, the soldered ball II 720 that reasonable magnitude setting is suitable, to obtain the optimum size of the encapsulating structure for DC-to-DC converter.
As shown in Figure 4 and Figure 5, height after HS chip 200 and LS chip 300 paster keeps flushing, and higher than the height after controller 400 upside-down mounting, and keep flushing with the height of soldered ball I 710 after the backflow on interconnection metal layer 500 again and/or soldered ball II 720 or a little less than the height of soldered ball I 710 after refluxing and/or soldered ball II 720.It is good that the metal coupling II 420 of support soldered ball I 710 and soldered ball II 720 is generally copper post.
Invent a kind of encapsulating structure for DC-to-DC converter, when it uses, by overall for encapsulating structure upside-down mounting to the circuit board such as external substrate or PCB 800, as shown in Figure 6, wherein HS chip 200 and LS chip 300 are fixed by scolding tin (soldering-tin layer 810) with the circuit board such as external substrate or PCB 800, and the grid of LS chip 300 is connected with controller 400 by the internal wiring of the circuit board such as external substrate or PCB 800.Because the height after HS chip 200 and LS chip 300 paster is higher than controller 400, HS chip 200 and LS chip 300 and the circuit board such as external substrate or PCB 800 can plane-plane contacts, increase heat conduction channel, significantly improve the hot property of the encapsulating structure for DC-to-DC converter.
Rely on current semiconductor Wiring technique again, a kind of encapsulating structure for DC-to-DC converter of the present invention can by the line-spacing Optimal Control of adjacent interconnection metal layer again 500 to 30um.Due to effective control of the line-spacing of interconnection metal layer 500 again, compared with the encapsulating structure being conventionally used to DC-to-DC converter, the size of the encapsulating structure for DC-to-DC converter of the present invention can reduce 30% ~ 50%.
Structure of the present invention employ connect up again and mount, the packaged type of upside-down mounting realizes the interconnected of each chip chamber, instead of the packaged type that traditional QFN adds wire bonding and band bonding, make the thickness of whole encapsulating structure at about 550um, roughly can reduce 50% ~ 60%, as shown in Figures 3 to 5.Adopt the packaged type of attachment or upside-down mounting, be used in the reduction of the size of the encapsulating structure of DC-to-DC converter and thinning, and increase the contact area of HS chip, LS chip and controller and wiring metal again, reduce interconnection resistance, expand heat dissipation channel, be conducive to the improvement of hot property, be conducive to the integrated development of substrate or circuit structure, be more conducive to the development of portable type electronic product.
A kind of encapsulating structure for DC-to-DC converter of the present invention is not limited to above preferred embodiment; any those skilled in the art without departing from the spirit and scope of the present invention; the any amendment done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all fall in protection range that the claims in the present invention define.
Claims (10)
1. for an encapsulating structure for DC-to-DC converter, comprise DC-to-DC converter, described DC-to-DC converter is made up of HS chip (200), LS chip (300) and controller (400),
It is characterized in that: also comprise (100) at the bottom of silicon wafer-based, described HS chip (200), LS chip (300) and controller (400) are laid in the central authorities of (100) at the bottom of silicon wafer-based, the surface of (100) at the bottom of described silicon wafer-based arranges the interconnection metal layer again (500) of sensible HS chip (200), LS chip (300) and controller (400), described HS chip (200) and LS chip (300) are electrically connected by the mode of paster and interconnection metal layer (500) again
The pin of described controller (400) arranges several metal couplings I (410), described controller (400) by metal coupling I (410) upside-down mounting on the interconnection metal layer again (500) of correspondence;
The grid of described HS chip (200) passes through interconnection metal layer (500) again and is electrically connected with controller (400), and its source electrode passes through interconnection metal layer (500) again and is electrically connected with the drain electrode of LS chip (300), and its drain electrode accesses input voltage VIN;
The interconnection metal layer again (500) of the periphery of described controller (400) arranges metal coupling II (420), and soldered ball I (710) is set on metal coupling II (420);
The grid of described LS chip (300) is connected with controller (400) by the internal wiring of external substrate or circuit board, its source ground.
2. a kind of encapsulating structure for DC-to-DC converter according to claim 1, is characterized in that: described HS chip (200) and controller (400) are arranged at the side of LS chip (300).
3. a kind of encapsulating structure for DC-to-DC converter according to claim 1, is characterized in that: the direction of described HS chip (200) paster is contrary with the direction of LS chip (300) paster.
4. a kind of encapsulating structure for DC-to-DC converter according to claim 1, it is characterized in that: the height after HS chip (200) and LS chip (300) paster keeps flushing, and keeps flushing with the height of soldered ball I (710) after the backflow on interconnection metal layer (500) again or a little less than the height of the soldered ball I (710) afterwards of refluxing.
5. a kind of encapsulating structure for DC-to-DC converter according to claim 4, is characterized in that: the height after described HS chip (200) and LS chip (300) paster is higher than the height after controller (400) upside-down mounting.
6. a kind of encapsulating structure for DC-to-DC converter according to claim 5, is characterized in that: the bottom space of the described controller (400) after upside-down mounting is filled the end and filled out agent (600).
7. a kind of encapsulating structure for DC-to-DC converter according to any one of claim 1 to 5, is characterized in that: described in adjacent, the line-spacing of interconnection metal layer (500) is not less than 30um again.
8. a kind of encapsulating structure for DC-to-DC converter according to any one of claim 1 to 5, is characterized in that: described metal coupling I (410) comprises copper post and tin cap.
9. a kind of encapsulating structure for DC-to-DC converter according to claim 8, is characterized in that: the altitude range of described metal coupling I (410): 30-80um.
10. a kind of encapsulating structure for DC-to-DC converter according to any one of claim 1 to 5, it is characterized in that: also comprise the soldered ball II (720) being arranged at periphery, the interconnection metal layer again (500) of described soldered ball II (720) below is in discrete shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310724835.7A CN103646941B (en) | 2013-12-25 | 2013-12-25 | A kind of encapsulating structure for DC-to-DC converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310724835.7A CN103646941B (en) | 2013-12-25 | 2013-12-25 | A kind of encapsulating structure for DC-to-DC converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103646941A CN103646941A (en) | 2014-03-19 |
| CN103646941B true CN103646941B (en) | 2016-04-27 |
Family
ID=50252139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310724835.7A Active CN103646941B (en) | 2013-12-25 | 2013-12-25 | A kind of encapsulating structure for DC-to-DC converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103646941B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630093A (en) * | 2003-12-18 | 2005-06-22 | 株式会社东芝 | Built-in power MOS field effect transistor and semiconductor device of drive circuit |
| CN103325690A (en) * | 2012-03-19 | 2013-09-25 | 英飞凌科技股份有限公司 | Semiconductor package and methods of formation thereof |
-
2013
- 2013-12-25 CN CN201310724835.7A patent/CN103646941B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630093A (en) * | 2003-12-18 | 2005-06-22 | 株式会社东芝 | Built-in power MOS field effect transistor and semiconductor device of drive circuit |
| CN103325690A (en) * | 2012-03-19 | 2013-09-25 | 英飞凌科技股份有限公司 | Semiconductor package and methods of formation thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103646941A (en) | 2014-03-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102709282B (en) | Multi-chip packaging structure, converter module and packaging method | |
| US8294256B2 (en) | Chip package structure and method of making the same | |
| CN202454556U (en) | Stacked chip package structure, synchronous rectification module and converter module | |
| US8928138B2 (en) | Complete power management system implemented in a single surface mount package | |
| CN101976951B (en) | Multiphase Power Switch Mode Voltage Regulator | |
| US9129947B2 (en) | Multi-chip packaging structure and method | |
| US8154108B2 (en) | Dual-leadframe multi-chip package and method of manufacture | |
| TWI512937B (en) | Flip - mounted package for integrated switching power supply and its flip - chip packaging method | |
| US9136207B2 (en) | Chip packaging structure of a plurality of assemblies | |
| CN202042483U (en) | Package structure of power semiconductor device | |
| CN103107171B (en) | Semiconductor device of flip chip | |
| CN104637894A (en) | MOSFET pair with stack capacitor and manufacturing method thereof | |
| JP2008147604A (en) | Semiconductor device package featuring encapsulated leadframe with projecting bumps or balls | |
| US20210249952A1 (en) | Power delivery for multi-chip-package using in-package voltage regulator | |
| CN102637679A (en) | Semiconductor module | |
| US9379088B2 (en) | Stacked package of voltage regulator and method for fabricating the same | |
| CN102222660B (en) | Double-lead-frame multi-chip common package body and manufacturing method thereof | |
| CN105529916A (en) | Electronic module and the fabrication method thereof | |
| CN201479030U (en) | Thin three-phase bridge rectifier | |
| CN103646941B (en) | A kind of encapsulating structure for DC-to-DC converter | |
| CN103348471B (en) | Semiconductor chip, memory device | |
| CN108807306B (en) | Power module structure with input protection | |
| CN201282143Y (en) | Packaging structure for chip integrated circuit | |
| CN215815875U (en) | Radio frequency power chip packaging structure | |
| CN104681517A (en) | Multi-chip QFN (Quad Flat No Lead) package suitable for LED (Light Emitting Diode) illuminating application |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |