CN102208409B - 集成电路结构 - Google Patents

集成电路结构 Download PDF

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CN102208409B
CN102208409B CN2010105018499A CN201010501849A CN102208409B CN 102208409 B CN102208409 B CN 102208409B CN 2010105018499 A CN2010105018499 A CN 2010105018499A CN 201010501849 A CN201010501849 A CN 201010501849A CN 102208409 B CN102208409 B CN 102208409B
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pattern
metal
pseudo
puppet
integrated circuit
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CN102208409A (zh
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刘醇鸿
侯上勇
郑心圃
吴伟诚
魏修平
陈志华
郭正铮
陈承先
曾明鸿
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供集成电路结构，包括半导体芯片，金属垫在半导体芯片的主要表面上，以及凸块下金属层在金属垫之上与金属垫接触，金属凸块形成于凸块下金属层之上与凸块下金属层电性连接，伪图案形成在与金属垫相同的水平面上，且由与金属垫相同的金属材料形成。本发明对于改善芯片的可靠度具有显著的效果。

Description

集成电路结构
技术领域
本发明涉及一种集成电路，尤其涉及一种用于封装结构的伪金属设计。
背景技术
现代的集成电路都在半导体芯片上形成，为了增加制造生产率以及降低制造成本，集成电路通常在半导体晶片上制造。每个半导体晶片含有许多相同的半导体芯片，于集成电路制造完成之后，从晶片分割出半导体芯片，并且在半导体芯片被使用前进行封装。
在典型的封装工艺中，首先，半导体芯片(也称为裸片)被贴附至封装基底上，包含将半导体芯片物理性地牢固在封装基底上，以及将半导体芯片上的接合垫(bond pad)与封装基底上的接合垫连接，接着使用底部填胶，通常包括环氧树脂，使得半导体芯片与封装基底的接合更牢固。可使用倒装芯片接合(flip-chip bonding)或打线接合(wire bonding)的方式，将半导体芯片与封装基底接合，所完成的结构称为封装组件。
图1显示传统的芯片的剖面示意图，其包含基底10、电性连线8、铝垫2、铜柱4以及焊锡区6。焊锡区6用于与封装基底(未示出)接合，电性连线8则将铜柱4与位于基底10表面的集成电路电性连接。
在半导体芯片接合至封装基底之后，连接半导体芯片与封装基底的焊锡区常常会裂开，焊锡区会裂开是因为半导体芯片与封装基底之间的热膨胀系数不同所产生的应力所引起，此外，半导体芯片与封装基底的不同层之间的热膨胀系数差异也会产生应力。随着封装基底与半导体芯片的尺寸增加，其所产生的应力也会随之增加，应力增加的结果会使得焊锡裂开的问题变得更严重，并且在半导体芯片的不同层之间会发生脱层现象，特别是，在半导体芯片的低介电常数介电层之间更容易发生脱层现象。
发明内容
为了解决现有技术的问题，依据一实施例，集成电路结构包含半导体芯片，金属垫在半导体芯片的主要表面上，以及凸块下金属层在金属垫之上与金属垫接触，金属凸块形成于凸块下金属层之上与凸块下金属层电性连接，伪图案形成在与金属垫相同的水平面上，且由与金属垫相同的金属材料形成。
其他实施例也揭示如下。
一种集成电路结构，包括：一半导体芯片；一钝化层，设置于该半导体芯片的一主要表面上；多个金属垫，设置于该钝化层下方；多个凸块下金属层，每个凸块下金属层包括一第一部分设置于该钝化层之上，以及一第二部分延伸至该钝化层，与每一个金属垫接触；多个金属凸块，每个金属凸块设置于所述多个凸块下金属层之上，与所述多个凸块下金属层中的一个接触；以及多个伪图案，分布在整个该半导体芯片中，其中所述多个伪图案为设置在相同水平面上的平行伪金属条，且由与所述多个金属垫相同的材料制成。
本发明对于改善芯片的可靠度具有显著的效果。
为了让本发明的上述目的、特征、及优点能更明显易懂，以下配合所附附图，作详细说明如下：
附图说明
图1显示传统半导体芯片的一部分的剖面示意图；
图2A及图2B显示依据一实施例，半导体芯片的剖面示意图；
图2C显示在图2A以及/或图2B中所示的结构的俯视图；
图3A至图4B显示依据其他实施例，半导体芯片的剖面示意图与俯视图。
其中，附图标记说明如下：
2～铝垫；          4～铜柱；        6～焊锡区；      8～电性连线；
10、20～基底；     24～有源电路；   26～内连线结构； 26a～金属线；
26b、33～导孔；    30～金属垫；     34～介电层；     35～额外的介电层(钝化层)；
38～凸块下金属层； 40～金属凸块；   40’～焊锡凸块； 46～焊锡层；50、
50’～伪图案；     52、54、55、57～底下的伪图案；    100～芯片。
具体实施方式
以下详述各实施例的制造与使用，然而，可以理解的是，这些实施例提供许多可应用的发明概念，其可以在各种不同的特定背景中实施，在此所讨论的特定实施例仅用于说明，并非用以限定揭示的范围。
依据一实施例，在半导体芯片中存在新的封装结构，接着，讨论实施例的各种变化。在全部的说明实施例与各种示意图中，使用相似的标记来标示相似的元件。
图2A显示半导体芯片100的一部分，其也可以是晶片的一部分。芯片100包含基底20，有源电路24形成于其上。基底20可以是由常用的半导体材料所形成的半导体基底，例如硅、硅锗或类似的材料。有源电路24可包含互补式金属氧化物半导体(CMOS)晶体管、电阻器、电容器(未示出)，以及/或类似的电路。内连线结构26在有源电路24之上形成，与部分的有源电路24内连接，并连接有源电路24与上方的金属层及焊锡凸块。内连线结构26包含多层金属层，包括在多层介电层内的金属线26a与导孔26b，这些介电层通常称为金属层间介电层(IMD)，在内连线结构26内的介电层可以是低介电常数介电层。
金属垫30在内连线结构26之上形成，且可经由内连线结构26与有源电路24电性连接。金属垫30可包含铝，因此在以下描述中也称为铝垫30，虽然金属垫30也可包含或由其他金属材料形成，例如铜、银、金、镍、钨、前述的合金，以及/或前述组合的多层结构。在一实施例中，金属垫30由铝铜合金(AlCu)形成。
介电层34在内连线结构26之上形成，介电层34也可称为钝化层(passivation layer；passivation-1)，可由介电材料形成，例如氧化硅(siliconoxide)、氮化硅(silicon nitride)、未掺杂的硅玻璃(un-doped silicate glass；USG)，以及/或前述组合的多层结构。导孔33在介电层34内形成，电性连接金属垫30与内连线结构26。在一实施例中，介电层34位于金属垫30下方，在其他实施例中，介电层34可形成在与金属垫30相同的水平面上。
额外的介电层35(也称为passivation-2)可在介电层34之上形成，凸块下金属层(under-bump metallurgies；UBMs)38在介电层35上形成，每个凸块下金属层38的一部分延伸至介电层35内。介电层35可由聚亚酰胺(polyimide)或其他的介电材料形成，例如氧化硅(silicon oxide)、氮化硅(silicon nitride)，以及前述组合的多层结构。金属垫30可与凸块下金属层38物理性地接触。
在一实施例中，凸块下金属层38由复合层形成，包括钛层以及在钛层上的铜层。在其他实施例中，凸块下金属层38可包含其他金属层，例如镍层或金层。凸块下金属层38与其底下各自的金属垫30的结合称为凸块垫结构(bump pad structure)。
金属凸块40在凸块下金属层38之上形成，金属凸块40可借由在凸块下金属层38之上形成光致抗蚀剂，将光致抗蚀剂图案化(未示出)，以及电镀金属材料至图案化光致抗蚀剂的开口内而形成。金属材料可包括铜，因此所形成的金属凸块40也称为铜凸块40，虽然金属凸块40也可以使用其他金属制成。接着，可选择性地将额外的其他层，例如镍层(未示出)以及焊锡层46电镀在每个铜凸块40之上。然后，将光致抗蚀剂移除，并使用湿蚀刻移除未被铜凸块40覆盖的凸块下金属层38。
芯片100中还包括伪图案(dummy pattern)50形成在与金属垫30相同的水平面上，伪图案50与金属垫30可以同时形成，并且可由相同的材料形成，例如AlCu。在一实施例中，伪图案50与金属垫30的形成包含全面性地沉积金属层，然后进行蚀刻工艺，蚀刻工艺可以是使用Cl2与BCl3(chloride)作为蚀刻剂的干蚀刻。伪图案50可不具有电性功能，并且可以不与基底20上的任何有源电路24，以及/或任何金属凸块40电性连接。
在一实施例中，只有伪图案50形成，在伪图案50底下并没有形成伪金属图案与伪图案50连接。在其他实施例中，如图2A所示，可形成额外的伪图案，其可包含伪重分布导孔(dummy redistribution via)52以及/或伪金属线/垫54。额外伪图案的形成可改善伪图案50与介电层34及35的粘着力，并且可改善在芯片100内的应力重分布，使得区域应力可以重新分布至芯片100中的较大区域。在其他实施例中，可以在伪金属线/垫54底下形成更多的伪图案55及57，并且延伸至更下方的层间介电层内。
在其他实施例中，如图2B所示，使用焊锡凸块40’取代铜凸块40，形成或固定在凸块下金属层38上。同样地，在图3A及图4A中，铜凸块40也可以被焊锡凸块40’置换。
图2C显示依据一实施例，在图2A以及/或图2B中所示的结构的一部分的俯视图。图2A及图2B所显示的剖面示意图可由图2C中的平面剖面线2-2得到，为了简化附图，铜凸块40与凸块下金属层38未示出。在俯视图中，金属垫30具有八边形的形状，然而金属垫30也可以有其他形状，例如六边形、正方形、圆形以及其他类似的形状。伪图案50的分布大抵上遍及整个芯片100，在一实施例中，如图2C所示，伪图案50可以是伪条(dummy strip)的形式，由接近芯片100的一边100_A延伸至接近一相对边100_B，除非金属垫30在伪图案50的沟道上形成，在此情况下，伪图案50会断裂成比较小的片段。因此，一些伪图案50的长度L1可能大于例如芯片100的个别长度L2的约50百分比或更多。在金属垫30与伪图案50之间的间隙S 1可能大于约2μm，或甚至大于约3μm，以避免伪图案50与金属垫30发生短路。然而，可以理解的是，在说明书中所提及的尺寸仅作为示范用，并且可以改成其他适合的数值。在一示范性的实施例中，当伪图案50的宽度W介于约5μm至35μm之间时，平行的伪图案50之间的间隙S2可约为10μm及20μm。因此，在芯片100中，包含所有的金属垫30与伪图案50的图案密度可大于约50百分比，并且可介于约50百分比至80百分比之间。
图3A及图3B分别显示依据另一实施例，半导体芯片100的剖面示意图与俯视图，图3A图显示图3B所示的结构的一部分的剖面示意图，其中图3A所示的剖面示意图是由图3B中的平面剖面线3A-3A得到。除了伪图案50具有不同的形状之外，此实施例与图2A-图2C所示的实施例相似。参阅图3B，在一实施例中，伪图案50为正方形(或具有接近的长与宽的矩形)，其具有的长度以及/或宽度介于例如约1μm至约5μm之间，然而不同的尺寸也可以使用。在金属垫30与邻近的伪图案50之间的间隙S1可大于约2μm，或甚至大于约3μm。在一示范性的实施例中，邻近的伪图案50之间的间隙S2可约为2μm及3μm。因此，包含金属垫30与伪图案50的图案密度可介于约20百分比至50百分比之间。
再参阅图3A，伪图案52及54可以在伪图案50底下形成或不形成。此外，因为层间介电层可用于电性布线(electrical routing)，当一些其他伪图案(例如伪图案50’)可能不具有底下的伪图案52以及/或54时，一些伪图案50可具有底下的伪图案52以及/或54，其取决于是否有可利用的空间。
图4A及图4B分别显示依据另一实施例，半导体芯片100的剖面示意图与俯视图，图4A显示图4B所示的结构的一部分的剖面示意图，其中图4A所示的剖面示意图是由图4B中的平面剖面线4A-4A得到。参阅图4B，伪图案50可以是伪图案保护物(dummy pattern shield)的形式，其围绕芯片100中一个以上，以及可能全部的金属垫30。在一实施例中，只有一个连续的伪图案50在芯片100内形成，换言之，所有的伪图案50或者大抵上在芯片100内所有的伪图案50互相连接，形成一个连续的伪图案。因此，伪图案50的面积可大于芯片100面积的约80百分比。另一方面，金属垫30可借由伪图案50互相分开。在其他实施例中，在芯片100内的伪图案50只包含限定数量(例如小于约10)的伪图案保护物，这些伪图案保护物互相分开。在一实施例中，伪图案50延伸至遍及大抵上整个的芯片100，伪图案50中接近芯片100的一边100_A的部分50_1可以与伪图案50中接近芯片100的一相对边100_B的部分50_2电性连接。此外，伪图案50中接近芯片100的一角100_C的部分50_3可以与伪图案50中接近芯片100的一相对角100_D的部分50_4电性连接。此外，在金属垫30与邻近的部分伪图案50之间的间隙S1可能大于约2μm，或甚至大于约3μm。在整个芯片100中，包含金属垫30与伪图案50的图案密度可大于约90百分比。同样地，可以在伪图案(伪图案保护物)50底下形成多个伪图案52与54。
借由在与金属垫30相同的水平面上形成伪图案，可以改善芯片/晶片的可靠度，这是因为伪图案50造成应力重分布(stress-redistribution)的结果。可进行许多实验来评估伪图案对于个别芯片可靠度的影响，在第一群组与第二群组的样品晶片中，分别依据图2A与图4A所示的结构制成伪图案，其中只形成伪图案50，但是没有形成伪图案52与54。可以观察得到，第一群组与第二群组的样品晶片的失效率都约为20百分比。然而，当没有形成伪图案50时，在相同的测试条件下，芯片的失效率增加至约83百分比，此结果显示伪图案50对于改善芯片的可靠度具有显著的效果。
另外，第三群组的样品芯片是依据图4A所示的结构制成，其具有伪图案50、52及54，可以观察得到，第三群组的样品芯片的失效率更降低至0百分比。
虽然本发明已揭示优选实施例如上，然其并非用以限定本发明，在本领域普通技术人员当可了解，在不脱离本发明的精神和范围内，当可做些许更动与润饰。因此，本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (8)

1.一种集成电路结构，包括：
一半导体芯片；
一金属垫，设置于该半导体芯片的一主要表面上；
一凸块下金属层，设置于该金属垫之上，与该金属垫接触；
一金属凸块，设置于该凸块下金属层之上，与该凸块下金属层电性连接；以及
一伪图案，设置在与该金属垫相同的水平面上，且由与该金属垫相同的金属材料制成，其中该伪图案包括一连续的伪金属保护物，完全地围绕该金属垫。
2.如权利要求1所述的集成电路结构，其中在该半导体芯片内无金属凸块在该伪图案之上形成，且无金属凸块与该伪图案电性连接，其中该伪图案与全部的金属凸块以及该半导体芯片内的有源集成电路电性隔绝。
3.如权利要求1所述的集成电路结构，其中该金属凸块为铜凸块或焊锡凸块。
4.如权利要求1所述的集成电路结构，其中该连续的伪金属保护物由该半导体芯片的一边连续地延伸至一相对边。
5.如权利要求1所述的集成电路结构，其中该连续的伪金属保护物由该半导体芯片的一角连续地延伸至一相对角。
6.如权利要求1所述的集成电路结构，还包括:
一伪重分布导孔，设置于该伪图案底下，与该伪图案物理性地接触;以及
一伪金属特征，设置于该伪重分布导孔底下，其中该伪金属特征与该伪重分布导孔及该伪图案电性连接。
7.如权利要求1所述的集成电路结构，其中在相同的水平面上，且由与该伪金属保护物图案相同的材料形成的全部金属特征的图案密度大于80百分比。
8.如权利要求1所述的集成电路结构，其中在相同的水平面上，且由与该伪图案相同的材料形成的全部金属特征的图案密度大于90百分比。
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