CN102201445A - Partial silicon on insulator (PSOI) lateral super-junction power semiconductor device - Google Patents
Partial silicon on insulator (PSOI) lateral super-junction power semiconductor device Download PDFInfo
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- CN102201445A CN102201445A CN2011100938437A CN201110093843A CN102201445A CN 102201445 A CN102201445 A CN 102201445A CN 2011100938437 A CN2011100938437 A CN 2011100938437A CN 201110093843 A CN201110093843 A CN 201110093843A CN 102201445 A CN102201445 A CN 102201445A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 title abstract description 5
- 239000010703 silicon Substances 0.000 title abstract description 5
- 239000012212 insulator Substances 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 12
- 238000009826 distribution Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 210000000746 body region Anatomy 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000012010 growth Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
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Abstract
The invention discloses a PSOI lateral super-junction power semiconductor device. The PSOI lateral super-junction power semiconductor device comprises a semiconductor body, an insulation buried layer, a gate and an electrode, wherein the gate and the electrode are arranged on the semiconductor body, a super-junction structure is arranged above the insulation buried layer, consists of super-junction n regions and super-junction p regions in alternate distribution, and is connected with a p-type body region. An n-type compensation region arranged in a direction vertical to the super-junction structure is connected with the super-junction structure and the insulation buried layer, and extends into a substrate. By the invention, the substrate-assisted depletion effect existing in the lateral super-junction power device can be effectively inhibited so as to improve the voltage resistance of the device. Compared with the conventional charge-compensation lateral super-junction device, the PSOI lateral super-junction power semiconductor device can better keep the super-junction voltage resistance property without increasing the thickness of the top silicon because the n-type compensation region is vertical to the super-junction structure.
Description
Technical field
The invention belongs to the power semiconductor field, particularly SOI(Semiconductor On Insulator) horizontal Superjunction power semiconductor device.
Background technology
Power semiconductor has irreplaceable key effect in national economy and social life, it is used for consumer electronics, Industry Control and defence equipment in a large number.Power semiconductor also is that the key technology and the basic technology, particularly China of energy-saving and emission-reduction will be saved energy and reduce the cost as one of fundamental state policy of country, the development of semiconductor power device and to apply be energy-conservation important technical.
In power semiconductor, MOS type power device (Power MOSFETs) can reduce switching time significantly, improves the switching frequency of device.But when high-voltage applications, the on-resistance per unit of power MOS (Metal Oxide Semiconductor) device is along with withstand voltage 2.5 powers increase, for the development of device has brought obstruction.The theoretical limit of conventional power MOS device has been broken in the proposition of super knot (Superjunction), has improved the withstand voltage of device, has reduced conducting resistance, and document sees reference: Chen Xingbi, " super junction device ", power electronic technology, 2008,42 (12): 2-7; Or, Tatsuhiko Fujihira, " Theory of semiconductor superjunction devices ", J. Appl. Phys., 1997,36 (10): 6254-6262.In recent years, along with the improvement of super knot technology, vertically super junction device moves towards system optimization from the device development.But the application of super knot technology in the lateral MOS power device but run into very big difficulty.Up to the present, laterally the puncture voltage of super junction device still can not reach desirable effect.Chief reason is, laterally super knot is made on the substrate of certain resistivity, can be subjected to the influence of longitudinal electric field, has broken the charge balance of super knot, the withstand voltage rapid reduction of device, and this is called as " substrate-assisted depletion effect ".The visible list of references of the content of this respect: Tl-Yong Park and C. Andre T. Salama, " Super Junction LDMOS Transistors – Implementing super junction LDMOS transistors to overcome substrate depletion effects ", IEEE Circuits and Devices Magazine, November/December 2006:10-15.
In the SOI device, insulating buried layer provides separator longitudinally, makes it have natural isolation advantage.All separate fully by oxygen buried layer between high-low pressure unit, active layer and the substrate of SOI device, being electrically connected of each several part eliminated fully.So the SOI device has that ghost effect is little, speed is fast, low in energy consumption, many advantages such as integrated level is high, anti-irradiation ability is strong.Super knot on the SOI substrate suffers the influence of longitudinal electric field equally, but this longitudinal electric field derives from the capacitance structure (be also referred to as the field and cause effect) that " silicon-insulating buried layer-silicon " forms.The longitudinal electric field that produces can be destroyed the charge balance of super knot equally, reduces the puncture voltage of device.Substrate-assisted depletion effect on this and the body silicon has similar influence, they are collectively referred to as " substrate-assisted depletion effect ", document sees reference: Sameh G. Nassif-Khalil, and C. Andre T. Salama, " Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST) ", Proc. ISPSD, 2002:81-84.The N district of super knot and the charge unbalance between the P district have reduced laterally super junction device withstand voltage of SOI.The low problem of withstand voltage that the present invention is directed to the laterally super knot power device of SOI has proposed a kind of new device architecture, has suppressed substrate-assisted depletion effect, has improved the withstand voltage of device.
Summary of the invention
The purpose of this invention is to provide the horizontal Superjunction power semiconductor device of a kind of PSOI, can alleviate the substrate-assisted depletion effect that exists in the laterally super knot power device, improve the withstand voltage of device.
For achieving the above object, the technical solution used in the present invention is: the horizontal Superjunction power semiconductor device of a kind of PSOI, comprise p type substrate, p type substrate upper surface is provided with insulating buried layer, be provided with p type tagma and super-junction structure in the insulating buried layer upper surface, super-junction structure is by laterally alternatively distributed super knot n district and super knot p district form, p type tagma contacts with a side end face of super-junction structure, p type tagma is provided with n type source region, p type body contact zone and gate oxide, the gate oxide upper end is provided with polysilicon gate, n type source region and p type body contact zone are provided with the source electrode, the opposite side of super-junction structure is provided with n type drain region, n type drain region is provided with drain electrode, a side that is provided with n type drain region on super-junction structure is provided with and the vertical n type compensating basin of super knot, n type compensating basin respectively with the super-junction structure end face, insulating buried layer and the contact of p type substrate, n type drain region is arranged on the n type compensating basin.
Compared with prior art, the present invention has following beneficial effect:
1. the horizontal Superjunction power semiconductor device of PSOI of the present invention has adopted new construction, promptly be provided with n type compensating basin 13 super the knot on the vertical direction, and be deep in the p type substrate 1, with respect to the SOI of routine laterally super knot power device (Fig. 2) can effectively eliminate substrate-assisted depletion effect, improve the charge balance of super knot, improve the withstand voltage of device.
2. the horizontal Superjunction power semiconductor device of PSOI of the present invention has adopted the n type electric charge compensating region 13 of vertical super-junction, adopt the n type electric charge compensating region 14 of parallel super knot with respect to other the horizontal Superjunction power semiconductor device of charge compensation type SOI (Fig. 3), the n type electric charge compensating region of parallel super knot has been introduced unnecessary electric charge at the source end when realizing charge compensation, reduced the voltage endurance of super knot.13 of the n type electric charge compensating regions of the vertical super-junction that the present invention adopts exist at drain terminal, can protect the voltage endurance of super knot.
Description of drawings
Fig. 1 is the three-dimensional structure schematic diagram of the horizontal Superjunction power semiconductor device of PSOI of the present invention.
Fig. 2 is the three-dimensional structure schematic diagram of the horizontal Superjunction power semiconductor device of SOI of routine.
Fig. 3 is the three-dimensional structure schematic diagram with horizontal Superjunction power semiconductor device of charge compensation type SOI of parallel super knot.
Fig. 4 is three-dimension device analog simulation result, illustrates the surface field distribution curve of three kinds of device architectures, and device of the present invention as can be seen has very straight Electric Field Distribution, and device withstand voltage is higher.
Wherein: 1 is p type substrate, and 2 is insulating buried layer, and 3 is p type tagma, 4 is n type source region, and 5 is p type body contact zone, and 6 is the source electrode, 7 is gate oxide, 8 is polysilicon gate, and 9 are super knot n district, and 10 are super knot p district, 11 is drain electrode, 12 is n type drain region, and 13 is the n type compensating basin of vertical super-junction, and 14 is the n type compensating basin of parallel super knot.
Embodiment
1 couple of the present invention elaborates below in conjunction with accompanying drawing.
The horizontal Superjunction power semiconductor device of a kind of PSOI of the present invention, comprise p type substrate 1, p type substrate 1 upper surface is provided with insulating buried layer 2, be provided with p type tagma 3 and super-junction structure in insulating buried layer 2 upper surfaces, super-junction structure is by laterally alternatively distributed super knot n district 9 and super knot p district 10 form, p type tagma 3 contacts with a side end face of super-junction structure, p type tagma 3 is provided with n type source region 4, p type body contact zone 5 and gate oxide 7, gate oxide 7 upper ends are provided with polysilicon gate 8, n type source region 4 and p type body contact zone 5 are provided with source electrode 6, the opposite side of super-junction structure is provided with n type drain region 12, n type drain region 12 is provided with drain electrode 11, a side that is provided with n type drain region on super-junction structure is provided with and the vertical n type compensating basin 13 of super knot, n type compensating basin 13 respectively with the super-junction structure end face, insulating buried layer 2 and 1 contact of p type substrate, n type drain region 12 is arranged on the n type compensating basin 13.
Insulating buried layer 2 can adopt different dielectric materials, as the insulating material of silicon dioxide, silicon nitride, sapphire or other different dielectric coefficients.N type compensating basin 13 can form by the mode of selective epitaxial.Super knot n district 9 is suitable with the width in super knot p district 10 in the described super-junction structure, need and decide according to actual design, super knot n district 9 is suitable with the doping content in super knot p district 10, need and decide according to actual design, the super n of knot district 9 and super knot p district 10 can form by the mode that ion injects or spreads, and need and decide according to actual design.N type compensating basin links to each other with insulating buried layer with super knot, and is deep in the substrate.
The present invention adopts following method preparation:
The first step, get the SOI backing material, it is carried out prerinse, form p type tagma 3 by the photoetching of p trap, injection, annealing, make mask etch silicon and insulating buried layer with silicon nitride, form n type compensating basin 13 by the selective epitaxial technology then, inject the super knot of formation p district 10 by ion, inject the super knot of formation n district 9 by ion, then carry out an oxide growth, adjust channel threshold voltage and inject, gate oxide 7 growths, the deposit polysilicon forms polysilicon gate 8, forms n type source region 4 and n type drain region 12 by injecting, and forms p type body contact zone 5 by injecting.
Second step, the etching oxidation layer forms the ohmic contact in p type body contact zone 5, n type source region 4 and n type drain region 12, forms the electrode fairlead of polysilicon gate 8, and depositing metal, etching metal form source electrode, drain electrode and gate electrode, carry out Passivation Treatment, pressure welding point at last.
Claims (2)
1. horizontal Superjunction power semiconductor device of PSOI, comprise p type substrate (1), p type substrate (1) upper surface is provided with insulating buried layer (2), be provided with p type tagma (3) and super-junction structure in insulating buried layer (2) upper surface, super-junction structure is by laterally alternatively distributed super knot n district (9) and super knot p district (10) form, p type tagma (3) contacts with a side end face of super-junction structure, p type tagma (3) is provided with n type source region (4), p type body contact zone (5) and gate oxide (7), gate oxide (7) upper end is provided with polysilicon gate (8), n type source region (4) and p type body contact zone (5) are provided with source electrode (6), the opposite side of super-junction structure is provided with n type drain region (12), n type drain region (12) is provided with drain electrode (11), it is characterized in that: a side that is provided with n type drain region (12) on super-junction structure is provided with and the vertical n type compensating basin (13) of super knot, n type compensating basin (13) respectively with the super-junction structure end face, insulating buried layer (2) and p type substrate (1) contact, n type drain region (12) is arranged on the n type compensating basin (13).
2. the horizontal Superjunction power semiconductor device of PSOI according to claim 1 is characterized in that: insulating buried layer (2) can adopt different dielectric materials, as the insulating material of silicon dioxide, silicon nitride, sapphire or other different dielectric coefficients.
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| CN201110093843A CN102201445B (en) | 2011-04-14 | 2011-04-14 | Partial silicon on insulator (PSOI) lateral super-junction power semiconductor device |
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| CN102201445B CN102201445B (en) | 2012-10-03 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102637744A (en) * | 2012-05-08 | 2012-08-15 | 中北大学 | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device |
| CN103426913A (en) * | 2013-08-09 | 2013-12-04 | 电子科技大学 | Partial SOI (silicon on insulator) super junction high-voltage power semiconductor device |
| CN103745996A (en) * | 2013-12-31 | 2014-04-23 | 上海新傲科技股份有限公司 | Lateral power device with partially insulated buried layer and manufacturing method |
| CN107785414A (en) * | 2017-10-27 | 2018-03-09 | 电子科技大学 | Lateral power with hybrid conductive pattern and preparation method thereof |
| CN107851614A (en) * | 2015-02-27 | 2018-03-27 | D3半导体有限公司 | Surface device in vertical power device |
| CN108447787A (en) * | 2018-03-20 | 2018-08-24 | 重庆大学 | A kind of transverse direction super-junction structure gallium nitride HEMT device and its manufacturing method |
| CN108511528A (en) * | 2018-04-11 | 2018-09-07 | 西安电子科技大学 | Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof |
| CN114613843A (en) * | 2022-03-14 | 2022-06-10 | 杭州电子科技大学 | SOI LDMOS device reinforcing structure capable of resisting total dose radiation effect |
| CN114628496A (en) * | 2022-05-13 | 2022-06-14 | 江苏游隼微电子有限公司 | Multi-groove power MOSFET structure and manufacturing method thereof |
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| US20030183858A1 (en) * | 2002-03-27 | 2003-10-02 | Kabushiki Kaisha Toshiba | Field effect transistor and application device thereof |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微***与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
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2011
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Patent Citations (3)
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| US20030183858A1 (en) * | 2002-03-27 | 2003-10-02 | Kabushiki Kaisha Toshiba | Field effect transistor and application device thereof |
| CN101771082A (en) * | 2009-12-30 | 2010-07-07 | 四川长虹电器股份有限公司 | Silicon-based lateral double-diffused metal-oxide semiconductor device on insulating substrate |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微***与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102637744B (en) * | 2012-05-08 | 2014-08-20 | 中北大学 | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device |
| CN102637744A (en) * | 2012-05-08 | 2012-08-15 | 中北大学 | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device |
| CN103426913A (en) * | 2013-08-09 | 2013-12-04 | 电子科技大学 | Partial SOI (silicon on insulator) super junction high-voltage power semiconductor device |
| CN103426913B (en) * | 2013-08-09 | 2016-08-31 | 电子科技大学 | A kind of partial SOI ultra-junction high-voltage power semiconductor device |
| CN103745996A (en) * | 2013-12-31 | 2014-04-23 | 上海新傲科技股份有限公司 | Lateral power device with partially insulated buried layer and manufacturing method |
| CN103745996B (en) * | 2013-12-31 | 2016-06-01 | 上海新傲科技股份有限公司 | With lateral power and the making method of part insulation buried regions |
| CN107851614A (en) * | 2015-02-27 | 2018-03-27 | D3半导体有限公司 | Surface device in vertical power device |
| CN107785414A (en) * | 2017-10-27 | 2018-03-09 | 电子科技大学 | Lateral power with hybrid conductive pattern and preparation method thereof |
| CN107785414B (en) * | 2017-10-27 | 2020-10-02 | 电子科技大学 | Lateral power device with mixed conduction mode and preparation method thereof |
| CN108447787A (en) * | 2018-03-20 | 2018-08-24 | 重庆大学 | A kind of transverse direction super-junction structure gallium nitride HEMT device and its manufacturing method |
| CN108511528A (en) * | 2018-04-11 | 2018-09-07 | 西安电子科技大学 | Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof |
| CN108511528B (en) * | 2018-04-11 | 2020-11-06 | 西安电子科技大学 | Transverse double-diffusion metal oxide composite semiconductor field effect transistor with deep drain region and manufacturing method thereof |
| CN114613843A (en) * | 2022-03-14 | 2022-06-10 | 杭州电子科技大学 | SOI LDMOS device reinforcing structure capable of resisting total dose radiation effect |
| CN114628496A (en) * | 2022-05-13 | 2022-06-14 | 江苏游隼微电子有限公司 | Multi-groove power MOSFET structure and manufacturing method thereof |
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| CN102201445B (en) | 2012-10-03 |
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