CN101488526A - N type SOI lateral double-diffused metal-oxide semiconductor transistor - Google Patents
N type SOI lateral double-diffused metal-oxide semiconductor transistor Download PDFInfo
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- CN101488526A CN101488526A CNA2009100249634A CN200910024963A CN101488526A CN 101488526 A CN101488526 A CN 101488526A CN A2009100249634 A CNA2009100249634 A CN A2009100249634A CN 200910024963 A CN200910024963 A CN 200910024963A CN 101488526 A CN101488526 A CN 101488526A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 238000007667 floating Methods 0.000 claims abstract description 29
- 239000012212 insulator Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000009826 distribution Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 9
- 239000012774 insulation material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 108010063955 thrombin receptor peptide (42-47) Proteins 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- -1 oxonium ion Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
A laterally double diffused metal oxide semiconductor transistor of an N-shaped silicon-on-insulator (SOI) comprises a semiconductor substrate. A buried oxide is arranged on the semiconductor substrate, an N-shaped doped semiconductor drift region is arranged on the buried oxide and a P-shaped well region is arranged above the N-shaped doped semiconductor drift region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the transistor. An N-shaped source region and a P-shaped contact region are arranged in a P-shaped well. The transistor is characterized in that the transistor also comprises at least a layer of floating oxide structure which is positioned in the N-shaped doped semiconductor drift region between a drain region and the buried oxide; moreover, a plurality of layers of floating oxide structure are allowed to further optimize the distribution of longitudinal electric fields in the drain region, thereby increasing the entire breakdown voltage of the transistor.
Description
Technical field
The present invention relates to the power semiconductor field, in particular, is the new construction that is applicable to the lateral double-diffused metal-oxide-semiconductor transistor (SOI LDMOS) of the silicon-on-insulator of high-voltage applications about a kind of.
Background technology
Because the device that adopts silicon-on-insulator material to make can be realized full dielectric isolation, its parasitic capacitance and leakage current are little, and drive current is big, so be well suited for making power IC device and circuit.For making SOI device that better effect be arranged, the puncture voltage that improves SOI device is an important research project.As everyone knows, withstand voltage its laterally withstand voltage and vertical withstand voltage reckling that depends on of silicon-on-insulator power device, the horizontal withstand voltage of device can be adopted field plate techniques, falls a layer technology, and the knot terminal technology of body silicon such as RESURF technology solves.But, become a difficult point in the research of silicon-on-insulator lateral power device because how the restriction of technology and structure improves the vertically withstand voltage of device.
Vertical puncture voltage of conventional soi structure is mainly born jointly by insulating barrier and active semiconductor layer, and the vertically withstand voltage V that is is arranged
B=E (3D
1+ 0.5D
2), wherein E is the critical breakdown electric field of semiconductor layer, D
1And D
2Be respectively the thickness of insulation material layer and silicon epitaxial layers, obviously vertically withstand voltage with D
1And D
2Increase and improve.But if insulation material layer do too thick, one side process implementing difficulty is big and be unfavorable for that device dispels the heat, can cause the silicon warp distortion on the other hand, integrity problem appears in the high accuracy photoetching, if it is too thick that silicon epitaxial layers is done, then similar with the body silicon device, bring difficulty for simultaneously follow-up dielectric isolation technology.
Abroad the someone proposes to insert one deck N between insulation material layer and silicon epitaxial layers
+Withstand voltage layer, the electric field that it can the shielding insulation material layer, the electric field of device silicon epitaxial layers subcritical breakdown electric field still when making electric field on insulation material layer reach very high, thus avoided device to cross as far back as Si/SiO
2Puncture on the interface, but on technology to N
+When heat-treating, Withstand voltage layer has serious anti-expansion phenomenon.
The domestic people of having proposes the channel insulation structure of voltage-sustaining layer in a kind of silicon-on-insulator power device, it can introduce interface charge on the interface of silicon epitaxial layers and insulation material layer, full continuity according to electric displacement increases substantially the insulating barrier internal electric field, thereby it is vertically withstand voltage to improve device.But it makes most of zone of insulation material layer have bigger thickness, is unfavorable for the heat radiation of device, has also reduced bond strength, and the etching of required big measuring tank has also been brought the complexity of whole manufacture craft in addition.
Summary of the invention
The invention provides and a kind ofly can effectively improve vertically withstand voltagely, and help improving the lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator of the heat dispersion of power device.
The present invention adopts following technical scheme:
A kind of lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator, comprise: Semiconductor substrate, on Semiconductor substrate, be provided with and bury oxide layer, be provided with N type doped semiconductor area on the oxide layer burying, on N type doped semiconductor area, be provided with P trap and N type drain region, on the P trap, be provided with N type source region and P type contact zone, be provided with gate oxide and gate oxide on the surface of P trap and extend to N type doped semiconductor area from the P trap, N type source region on P trap surface, the N type drain region with exterior domain and N type doped semiconductor area surface of P type contact zone and gate oxide is provided with field oxide with exterior domain, be provided with the surface that polysilicon gate and polysilicon gate extend to field oxide on the surface of gate oxide, at field oxide, P type contact zone, N type source region, the surface in polysilicon gate and N type drain region is provided with oxide layer, in N type source region, P type contact zone, be connected with metal level respectively on polysilicon gate and the N type drain region, in N type doped semiconductor area, be provided with first oxide layer of floating, and first oxide layer of floating is positioned at the below in N type drain region.
Compared with prior art, the present invention has following advantage:
(1) structure of the present invention has the first oxide layer structure 121 of floating below drain region 10, the horizontal withstand voltage employing RESURF technical optimization of device is handled, only need to consider vertical pressure drop, reduce gradually and device is vertically anti-from drain terminal to the source end, first of the face that the leaks down oxide layer 121 of floating can be born higher field intensity, thus improve the whole withstand voltage of device.With reference to accompanying drawing 4, to float after the oxide layer structure 121 having added first, the electric field strength that oxide layer 8 is buried in the below, drain region obviously reduces, and first float and shared part electric field strength on the oxide layer 121, the area that curve enclosed is also bigger, and with reference to accompanying drawing 5, puncture voltage has improved greatly as can be seen.
(2) in the structure of the present invention, the first oxide layer structure 121 of floating is arranged under the drain terminal, reduced charge carrier ionization integration lengths, make disruptive critical voltage increase in silicon and the silicon dioxide, thereby can reduce to bury the thickness of oxide layer 8 greatly, certainly also reduce the technology difficulty that cutting in the silicon epitaxial layers and dielectric isolation realize.
(3) structure of the present invention only need be carried out the injection of window oxygen on the lateral double-diffused metal-oxide-semiconductor transistor surface of N type silicon-on-insulator, and do not need its lower zone is done any processing, this has just been avoided making buried structure or the special photoetching contraposition problem that can occur when burying oxide structure, has highly also kept heat dispersion preferably in withstand voltage bearing.
(4) structure of the present invention is except that window oxygen injects, and other processing step is compatible mutually with complementary bilateral diffusion metal oxide transistor (CDMOS) technology of standard, does not therefore need to revise intrinsic technological process.
Description of drawings
Fig. 1 is the lateral double-diffused metal-oxide-semiconductor transistor structural representation of high voltage N type SOI that does not add the conventional structure of the oxide layer structure of floating.
Fig. 2 has added the first lateral double-diffused metal-oxide-semiconductor transistor structural representation of high voltage N type SOI of oxide layer structure 121 of floating among the present invention.
Fig. 3 is the lateral double-diffused metal-oxide-semiconductor transistor structural representation that has added the high voltage N type SOI of two-layer float oxide layer 121 and 122 among the present invention.(allowing more multi-layered)
Fig. 4 does not add to have added first below, the drain region longitudinal electric field distribution comparison diagram of lateral double-diffused metal-oxide-semiconductor transistor of high voltage N type SOI of oxide layer 121 of floating among the lateral double-diffused metal-oxide-semiconductor transistor of high voltage N type SOI of conventional structure of the oxide layer of floating and the present invention, interpreting blueprints for convenience, the part of below, device drain region is placed the left side of longitudinal electric field distribution comparison diagram among the figure, the ordinate and the device lengthwise position of longitudinal electric field distribution comparison diagram are one to one.
Fig. 5 does not float to have added first the float puncture voltage of lateral double-diffused metal-oxide-semiconductor transistor of high voltage N type SOI of oxide layer 121 and the analog result figure of epitaxial silicon layer thickness relation among the lateral double-diffused metal-oxide-semiconductor transistor of high voltage N type SOI of conventional structure of oxide layer and the present invention.
Embodiment
With reference to Fig. 2, a kind of lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator, comprise: Semiconductor substrate 9, on Semiconductor substrate 9, be provided with and bury oxide layer 8, be provided with N type doped semiconductor area 7 on the oxide layer 8 burying, on N type doped semiconductor area 7, be provided with P trap 6 and N type drain region 10, on P trap 6, be provided with N type source region 11 and P type contact zone 13, be provided with gate oxide 3 and gate oxide 3 on the surface of P trap 6 and extend to N type doped semiconductor area 7 from P trap 6, N type source region 11 on P trap 6 surfaces, the N type drain region 10 with exterior domain and N type doped semiconductor area 7 surfaces of P type contact zone 13 and gate oxide 3 is provided with field oxide 1 with exterior domain, be provided with the surface that polysilicon gate 4 and polysilicon gate 4 extend to field oxide 1 on the surface of gate oxide 3, at field oxide 1, P type contact zone 13, N type source region 11, the surface in polysilicon gate 4 and N type drain region 10 is provided with oxide layer 5, in N type source region 11, P type contact zone 13, be connected with metal level 2 respectively on polysilicon gate 4 and the N type drain region 10, in N type doped semiconductor area 7, be provided with first float oxide layer 121 and first float oxide layer 121 be positioned at N type drain region 10 below.
Present embodiment also adopts following technical measures further to improve performance of the present invention:
With reference to Fig. 3, in N type doped semiconductor area 7, be provided with second oxide layer 122 of floating, and second oxide layer 122 of floating is positioned at first below of floating oxide layer 121.
First float the upper surface of oxide layer 121 apart from the lower surface in N type drain region 10 between 0.5 micron to 1 micron.
First floats oxide layer 121 thickness between 0.2 micron to 0.5 micron.
Second oxide layer 122 and first distance of floating between the oxide layer 121 of floating is no more than 0.5 micron.
First length of floating oxide layer 121 is 1 to 1.5 times of drain region 10 width.
Though present embodiment has adopted the two-layer oxide layer of floating, in the reality, allow below the drain region, to be provided with the multilayer oxide layer of floating, make the longitudinal electric field in device drain region further optimize, thereby further improve device electric breakdown strength.
The present invention adopts following method to prepare:
1, make needed silicon-on-insulator SOI substrate, it can adopt and annotate the oxygen partition method, other methods such as wafer bonding method (following is example to annotate the oxygen isolation method).Can adopt the special-purpose oxonium ion implanter of big line that oxonium ion is injected in the Silicon Wafer, implantation dosage is about 1E18/cm
2, in inert gas, carried out 〉=1300 ℃ of high annealings then 3 to 5 hours, thereby form thickness silicon epitaxial layers and insulation material layer as thin as a wafer uniformly at the Silicon Wafer top.
2, make buried oxide layer, it need cover the part that does not need to carry out the oxygen atom injection with a mask, adopts the high concentration oxygen atom to inject with the energy of counting million-electron-volt again.For one deck lateral double-diffused metal-oxide-semiconductor transistor of high voltage N type SOI of oxide layer structure of floating only is set, only need carry out an oxygen atom and inject (1Mev is to 2Mev), in inert gas, carried out 〉=1300 ℃ of high annealings then 3 to 5 hours, thereby form continuous oxide layer in vivo, and for the two-layer or multilayer lateral double-diffused metal-oxide-semiconductor transistor of high voltage N type SOI of oxide layer of floating is set, then need to carry out twice or the injection of oxygen atom repeatedly, note twice or repeatedly inject the difference (3Mev is to 4Mev for the first time, and 1Mev is to 2Mev for the second time) of energy.Then carry out high annealing,, polish, make it the thickness that reaches required then with wafer thinning.
3, be the making of the lateral double-diffused metal-oxide-semiconductor transistor of routine, it comprises that P type trap injects, the preparation of field oxygen, the growth of grid oxygen, etching, the deposit of polysilicon, etching are exactly that leakage injection region, high concentration source contacts the injection region preparation with substrate then, be fairlead at last, the preparation of aluminum lead and Passivation Treatment.
Claims (6)
1, a kind of lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator, comprise: Semiconductor substrate (9), on Semiconductor substrate (9), be provided with and bury oxide layer (8), be provided with N type doped semiconductor area (7) on the oxide layer (8) burying, on N type doped semiconductor area (7), be provided with P trap (6) and N type drain region (10), on P trap (6), be provided with N type source region (11) and P type contact zone (13), be provided with gate oxide (3) on the surface of P trap (6) and gate oxide (3) extends to N type doped semiconductor area (7) from P trap (6), N type source region (11) on P trap (6) surface, the N type drain region (10) with exterior domain and N type doped semiconductor area (7) surface of P type contact zone (13) and gate oxide (3) is provided with field oxide (1) with exterior domain, be provided with the surface that polysilicon gate (4) and polysilicon gate (4) extend to field oxide (1) on the surface of gate oxide (3), in field oxide (1), P type contact zone (13), N type source region (11), the surface in polysilicon gate (4) and N type drain region (10) is provided with oxide layer (5), in N type source region (11), P type contact zone (13), be connected with metal level (2) respectively on polysilicon gate (4) and the N type drain region (10), it is characterized in that in N type doped semiconductor area (7), being provided with first oxide layer (121) and first oxide layer (121) of floating of floating and be positioned at the below in N type drain region (10).
2. the lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator according to claim 1 is characterized in that being provided with second oxide layer (122) and second oxide layer (122) of floating of floating and is positioned at first below of floating oxide layer (121) in N type doped semiconductor area (7).
3. the lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator according to claim 1 and 2, it is characterized in that first float the upper surface of oxide layer (121) apart from the lower surface in N type drain region (10) between 0.5 micron to 1 micron.
4. the lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator according to claim 3 is characterized in that first floats oxide layer (121) thickness between 0.2 micron to 0.5 micron.
5. the lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator according to claim 3 is characterized in that second oxide layer (122) and first distance of floating between the oxide layer (121) of floating is no more than 0.5 micron.
6. the lateral double-diffused metal-oxide-semiconductor transistor of N type silicon-on-insulator according to claim 3 is characterized in that first length of floating oxide layer (121) is 1 to 1.5 times of drain region (10) width.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100249634A CN101488526A (en) | 2009-02-27 | 2009-02-27 | N type SOI lateral double-diffused metal-oxide semiconductor transistor |
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|---|---|---|---|
| CNA2009100249634A CN101488526A (en) | 2009-02-27 | 2009-02-27 | N type SOI lateral double-diffused metal-oxide semiconductor transistor |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102082169A (en) * | 2010-12-08 | 2011-06-01 | 四川长虹电器股份有限公司 | Partial SOI (silicon on insulator) traverse double-diffused device |
| CN102088031A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof |
| CN102176469A (en) * | 2011-03-10 | 2011-09-07 | 杭州电子科技大学 | SOI (Silicon on Insulator) nLDMOS (n-Channel Lateral Diffused Metal Oxide Semiconductor) device unit with p buried layer |
| CN102280472A (en) * | 2011-08-07 | 2011-12-14 | 东南大学 | N-type electrostatic protection semiconductor device with high maintaining voltage |
| CN102412162A (en) * | 2011-11-23 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS) |
| CN102637736A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | High-voltage LDMOS (high-voltage-lateral diffused metal oxide semiconductor) component |
| CN103268890A (en) * | 2013-05-28 | 2013-08-28 | 电子科技大学 | Power LDMOS device with junction field plate |
| CN103296063A (en) * | 2012-03-01 | 2013-09-11 | 台湾积体电路制造股份有限公司 | Apparatus and method for high voltage MOS transistor |
| CN103325835A (en) * | 2013-05-28 | 2013-09-25 | 电子科技大学 | SOI power LDMOS device provided with junction type field plate |
| CN105870189A (en) * | 2016-04-21 | 2016-08-17 | 西安电子科技大学 | Lateral super-junction double-diffusion metal oxide semiconductor field effect transistor having bulk electric field modulation effect |
| CN107123681A (en) * | 2016-02-25 | 2017-09-01 | 瑞萨电子株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN112420824A (en) * | 2020-12-09 | 2021-02-26 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor capable of eliminating negative resistance effect |
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- 2009-02-27 CN CNA2009100249634A patent/CN101488526A/en active Pending
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088031A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof |
| WO2011066802A1 (en) * | 2009-12-03 | 2011-06-09 | Csmc Technologies Fab1 Co., Ltd. | N type lateral double diffused metal oxide semiconductor device and manufacturing method thereof |
| CN102082169B (en) * | 2010-12-08 | 2012-07-25 | 四川长虹电器股份有限公司 | Partial SOI (silicon on insulator) traverse double-diffusion device |
| CN102082169A (en) * | 2010-12-08 | 2011-06-01 | 四川长虹电器股份有限公司 | Partial SOI (silicon on insulator) traverse double-diffused device |
| CN102637736A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | High-voltage LDMOS (high-voltage-lateral diffused metal oxide semiconductor) component |
| CN102637736B (en) * | 2011-02-10 | 2014-06-25 | 上海华虹宏力半导体制造有限公司 | High-voltage LDMOS (high-voltage-lateral diffused metal oxide semiconductor) component |
| CN102176469A (en) * | 2011-03-10 | 2011-09-07 | 杭州电子科技大学 | SOI (Silicon on Insulator) nLDMOS (n-Channel Lateral Diffused Metal Oxide Semiconductor) device unit with p buried layer |
| CN102280472A (en) * | 2011-08-07 | 2011-12-14 | 东南大学 | N-type electrostatic protection semiconductor device with high maintaining voltage |
| CN102412162B (en) * | 2011-11-23 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS) |
| CN102412162A (en) * | 2011-11-23 | 2012-04-11 | 上海华虹Nec电子有限公司 | Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS) |
| CN103296063B (en) * | 2012-03-01 | 2016-05-25 | 台湾积体电路制造股份有限公司 | For the apparatus and method of high voltage MOS transistor |
| CN103296063A (en) * | 2012-03-01 | 2013-09-11 | 台湾积体电路制造股份有限公司 | Apparatus and method for high voltage MOS transistor |
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| CN107123681B (en) * | 2016-02-25 | 2022-03-01 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN105870189A (en) * | 2016-04-21 | 2016-08-17 | 西安电子科技大学 | Lateral super-junction double-diffusion metal oxide semiconductor field effect transistor having bulk electric field modulation effect |
| CN105870189B (en) * | 2016-04-21 | 2019-07-19 | 西安电子科技大学 | A kind of lateral super-junction bilateral diffusion metal oxide semiconductor field-effect tube with bulk electric field mudulation effect |
| CN112420824A (en) * | 2020-12-09 | 2021-02-26 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor capable of eliminating negative resistance effect |
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