CN102194756A - 鳍式场效晶体管及其制法 - Google Patents

鳍式场效晶体管及其制法 Download PDF

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CN102194756A
CN102194756A CN2010102510922A CN201010251092A CN102194756A CN 102194756 A CN102194756 A CN 102194756A CN 2010102510922 A CN2010102510922 A CN 2010102510922A CN 201010251092 A CN201010251092 A CN 201010251092A CN 102194756 A CN102194756 A CN 102194756A
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fin
effect transistor
formula field
isolating trough
shallow isolating
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CN102194756B (zh
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林家彬
詹前泰
林献钦
林学仕
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种鳍式场效晶体管(FinFET)及其制法，该晶体管制法包括：从半导体基材之上延伸形成鳍式场效晶体管的第一与第二鳍，其中浅沟隔离(shallow trench isolation，STI)区域位于第一与第二鳍之间，且与第一、第二鳍上表面之间具有一距离；提供第一与第二鳍延伸部分于高于浅沟隔离区域的上表面之上的第一与第二鳍的上表面与侧表面之上；从浅沟隔离区域移除部分材料，以增加介于浅沟隔离区域上表面与第一、第二鳍上表面之间的距离；沉积顺应性应力介电材料于第一、第二鳍与浅沟隔离区域之上；回焊顺应性应力介电材料。本发明可减少桥接现象并提高鳍式场效晶体管的选择性外延成长技术效率。

Description

鳍式场效晶体管及其制法
技术领域
本发明涉及一种半导体元件的制法，且特别涉及一种鳍式场效晶体管(finFETs)与其制法。
背景技术
随着半导体工艺技术的发展，互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)与鳍式场效晶体管(FinFET)元件有助于许多逻辑元件与其他应用，且其被整合成各种不同的半导体元件。鳍式场效晶体管(FinFET)元件一般包括具有高深宽比(high aspect ratio)的鳍，且具有半导体晶体管的沟道与源极/漏极区域。栅极形成于鳍之上且沿着鳍侧壁而形成，借由增加沟道及源极/漏极区域的表面，以产生更快速、更可靠与更易控制的半导体晶体管元件。
于鳍式场效晶体管(FinFET)与传统的平面晶体管元件中，压缩应力(compressive stress)施加于PMOS元件，将有助于提高空穴迁移率。同样地，伸张应力(tensile stress)施加于NMOS元件，将有助于提高电子迁移率。对于平面CMOS元件而言，复合的应力层(complex stressors)将有助于提升整体元件的性能表现，例如选择性的硅锗(SiGe)源极/漏极结构，用于增加PMOS元件的空穴迁移率；伸张接触蚀刻停止层(tensile contact etch stop layer)、接触蚀刻停止层(contact etch stop layer，CESL)与其他介电薄膜应力层用于增加NMOS元件的电子迁移率。将上述有利于增加空穴或电子迁移率的工艺整合到鳍式场效晶体管(FinFET)时，需要额外的操作与成本，因而成为一种新的挑战。
图1显示公知鳍式场效晶体管(FinFET)的等比例剖面图。鳍106包括高于半导体基材101(显示于图1C与图1D中)的凸起氧化定义区(raised oxide defined，OD)106。每一个鳍106皆被浅沟隔离(shallow trench isolation，STI)区域102所隔开，且位于一对浅沟隔离区域之间。鳍106具有高于浅沟隔离(STI)区域102上表面的高度107。多晶硅栅极电极108形成于鳍106之上，且一薄的栅极介电层(图中未显示)介于鳍106与多晶硅栅极电极108之间。侧壁间隙壁(sidewall spacers)110形成于每一个栅极电极108的两侧上，是为了形成轻掺杂源极(lightly doped drain，LDD)注入区域(图中未显示)。
图1B显示经过外延成长步骤之后的鳍106，其中鳍106的上表面106e面积增加。鳍106的上部分106e为近似于五角形的形状，其具有侧向延伸部分(lateral extensions)106L，且其延伸一距离109，此距离109平行于基材101上表面的方向。
图1C与图1D显示图1A的鳍式场效晶体管(FinFET)100的X轴方向(前侧)与Y轴方向(旁侧)的剖面图，此图为形成氧化硅硬掩模112与虚设侧壁间隙壁110之后，形成外延硅锗(SiGe)工艺之前。
图1E与图1F显示图1A的鳍式场效晶体管(FinFET)100的X轴方向(前侧)与Y轴方向(旁侧)的剖面图，此图为进行外延工艺之后。对鳍106进行外延工艺，以形成硅锗(SiGe)层106e于鳍式场效晶体管(FinFET)的鳍106之上。
如图1E所示，鳍硅锗(SiGe)层106e的外延硅锗侧向延伸部分106L从侧向向彼此延伸，因而减少相邻的鳍侧向延伸部分106L的宽度106w。
发明内容
为克服上述现有技术的缺陷，本发明提供一种鳍式场效晶体管(FinFET)的制法，包括以下步骤：从一半导体基材之上延伸形成一鳍式场效晶体管(FinFET)的第一鳍与第二鳍，其中一浅沟隔离(shallow trench isolation，STI)区域位于该第一鳍与该第二鳍之间，且该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间具有一距离；提供一第一与第二鳍延伸部分(fin extensions)于高于该浅沟隔离区域的上表面之上的该第一鳍与该第二鳍的上表面与侧表面之上；从该浅沟隔离区域移除部分材料，以增加介于该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间的该距离；沉积一顺应性应力介电材料(conformal stressor dielectric material)于该第一鳍、该第二鳍与该浅沟隔离区域之上；回焊该顺应性应力介电材料，以使其流入介于该第一鳍与该第二鳍之间且高于该浅沟隔离区域上表面之上的一空间，以施加应力到该鳍式场效晶体管的一沟道。
本发明也提供一种鳍式场效晶体管(FinFET)的制法，包括以下步骤：从一半导体基材之上延伸提供一鳍式场效晶体管(FinFET)的一第一鳍与一第二鳍，其中一浅沟隔离(shallow trench isolation，STI)区域位于该第一鳍与该第二鳍之间，且该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间具有一距离；形成一栅极电极于该第一鳍与该第二鳍之上；提供一第一与第二硅锗鳍延伸部分(SiGe fin extensions)于高于该浅沟隔离区域的上表面之上的该第一鳍与该第二鳍的上表面与侧表面之上；从该浅沟隔离区域移除部分材料，以增加介于该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间的该距离；沉积一顺应性应力介电材料(conformal stressor dielectric material)于该第一鳍、该第二鳍、该栅极电极与该浅沟隔离区域之上；回焊该顺应性应力介电材料，以使其流入介于该第一鳍与该第二鳍之间且高于该浅沟隔离区域上表面之上的一空间，以施加应力到该鳍式场效晶体管的一沟道，且同时于相邻于该栅极电极之处留下该顺应性应力介电材料的一薄膜，以形成侧壁间隙壁(sidewall spacers)；以及于回焊步骤之后，进行源极与漏极的掺杂注入。
本发明又提供一种鳍式场效晶体管(FinFET)，包括：一鳍式场效晶体管(FinFET)的一第一鳍与一第二鳍从一半导体基材之上延伸，其中一浅沟隔离(shallow trench isolation，STI)区域具有一浅沟隔离介电材料且位于该第一鳍与该第二鳍之间，且该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间具有一距离；一栅极电极位于该第一鳍与该第二鳍之上；一第一与第二硅锗鳍延伸部分(SiGe fin extensions)位在高于该浅沟隔离区域的上表面之上的该第一鳍与该第二鳍的上表面与侧表面之上；一顺应性应力介电材料(conformal stressor dielectric material)位于该第一鳍与该第二鳍之间且高于该浅沟隔离区域上表面之上的一空间，以施加应力到该鳍式场效晶体管的一沟道；以及该顺应性应力介电材料的一薄膜相邻于该栅极电极，以形成侧壁间隙壁(sidewall spacers)。
本发明可减少桥接现象的产生，并提高了鳍式场效晶体管的选择性外延成长技术效率。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下：
附图说明
图1A为一剖面图，用以说明公知鳍式场效晶体管(FinFET)的等比例剖面图。
图1B为一剖面图，用以说明图1A的其中之一鳍，经由外延成长硅锗(SiGe)之后。
图1C～图1F为一系列剖面图，用以说明鳍式场效晶体管(FinFET)的鳍经过外延硅锗(SuGe)成长之前与之后。
图2A～图2B为一系列剖面图，用以说明基材经过鳍与栅极电极形成工艺之后。
图3A～图3B为一系列剖面图，用以说明基材经过轻掺杂源极注入工艺之后。
图4A～图4B为一系列剖面图，用以说明基材经过虚设侧壁间隙壁之后。
图5A～图5B为一系列剖面图，用以说明基材经过外延硅锗(SuGe)鳍延伸部分沉积工艺之后。
图6A～图6B为一系列剖面图，用以说明基材经过降低浅沟隔离介电材料的高度之后。
图7A～图7B为一系列剖面图，用以说明基材经过沉积应力薄膜之后。
图8A～图8B为一系列剖面图，用以说明基材经过回焊应力材料之后。
图9A～图9B为一系列剖面图，用以说明源极/漏极注入工艺。
图10为一照片，用以说明图9A与图9B的鳍式场效晶体管的实施例。
图11为一函数关系图，用以说明沟道应力与各种参数的关系。
图12为一函数关系图，用以说明图11的源极饱和电流(Idsat)的增加比率。
其中，附图标记说明如下：
100～鳍式场效晶体管(FinFET)
101～半导体基材
102～浅沟隔离(STI)区域
106～鳍
106e～硅锗(SiGe)层
106L～侧向延伸部分
106w～间隔距离(window)
107～高度
108～栅极电极
109～距离
110～侧壁间隙壁
112～硬掩模
200～鳍式场效晶体管
201～半导体基材
202～浅沟隔离(STI)区域
203～轻掺杂源极(LDD)/环状注入步骤
206～鳍
206e～鳍延伸部分
206L～侧向延伸部分
206w～间隔距离(window)
207a～第一距离
207b～第二距离
208～栅极电极
210，211～虚设侧壁
212～硬掩模
214～顺应性应力介电材料
214r～应力层
214s～垂直薄膜(或侧壁间隙壁)
217～源极与漏极掺杂注入
220～接触蚀刻停止层
230～层间介电层(ILD)
H1、H2～距离
T1～应力材料薄膜的厚度
T2～T3与T4的厚度总合
T3～高于硅锗延伸部分底部的应力材料的厚度
T4～低于硅锗延伸部分底部的应力材料的厚度
1101-1106、1201-1206～曲线
具体实施方式
以下的示范实施例配合附图，这些实施例为说明书的一部分。于说明书中的相对用语，例如”较低(lower)”、”较高(upper)”、”水平的(horizontal)”、”垂直的(vertical)”、”高于(above)”、”低于(below)”、”上(up)”、”下(down)”、”顶部(top)”与”底部(bottom)”意指下述讨论或显示于图中的方向(orientation)。这些相对用语是为了帮助说明，并不表示必须以特定的方向操作元件。关于附着(attachments)、耦合(coupling)或类似的用语，例如”连接(connected)”与”内连接(interconnected)”，也指结构被固定或附着于另一个元件，借由直接或间接穿过中介结构，除非特别表示，其可以是可动的(movable)或固定(rigid)的关系。
图形并非依据实际尺寸绘制。
发明人发现，随着技术节点(technology nodes)的进步(例如22nm)，于鳍式场效晶体管(FinFET)的鳍上外延成长硅锗(SiGe)，会缩短介于相邻NMOS与PMOS鳍的水平延伸部分的间隔距离(window)，因此，可能造成桥接(bridging)现象的产生。桥接现象会干扰切割芯片的能力(singulate the dies)。即使没有完全的桥接，窄化相邻鳍延伸部分的间隔距离(window)可能会使第一金属层间介电层(inter metal dielectric layer，IMD)中形成孔洞(void)，此第一金属层间介电层(IMD)于有源元件工艺完成之后形成。此种孔洞(void)可能产生于相邻PMOS与NMOS鳍延伸部分之间与之下的空间中。
发明人发现的另一个问题在于，于目前先进的技术设计中，具有超窄鳍宽度(小体积)的鳍式场效晶体管(FinFET)的选择性外延成长技术效率太低。于一些设计(例如，具有狗骨头形状的鳍式场效晶体管(FinFET))中，难以进行栅极虚设侧壁间隙壁(gate dummy sidewall spacer)的工艺。
于本发明的实施例中，硅锗(SiGe)外延层形成于鳍的顶部，同时浅沟隔离介电材料的表面具有一第一高度接近鳍的顶部。因为鳍顶部与浅沟隔离材料顶部的距离缩短，使得硅锗(SiGe)薄膜具有较短的侧向延伸部分。如此一来，相邻鳍延伸部分的宽度的缩短较不严重，且相邻鳍延伸部分并不会合并(merge)在一起。经由外延硅锗沉积之后，浅沟隔离介电材料的高度会降低至一第二高度，且一应力材料层以顺性性薄膜的形式施加到元件上。此应力材料被回焊到介于相邻鳍与高于浅沟隔离介电材料之间的空间，以部分地填充此空间。于一些实施例中，一部分顺应性形成的薄膜会残留相邻于鳍式场效晶体管(FinFET)的栅极电极，以形成侧壁间隙壁。
图2A～图9B显示制作一鳍式场效晶体管(FinFET)200的制法。此制法可使沟道的应力增加，而不需要额外的掩模或光微影步骤。每一对相邻的图(图2A与图2B、图3A与图3B、图4A与图4B、图5A与图5B、图6A与图6B、图7A与图7B、图8A与图8B、图9A与图9B)显示鳍式场效晶体管(FinFET)于各个工艺阶段的X轴方向(前侧)与Y轴方向(旁侧)的剖面图。X轴与Y轴方向标示于图1A中。
请参见图2A与图2B，图中显示形成鳍式场效晶体管(FinFET)200的第一鳍与第二鳍206延伸位于半导体基材201上。栅极介电层(图中未显示)与栅极电极208形成于鳍206上。硬掩模212形成于栅极电极208上。浅沟隔离(STI)区域202形成于鳍206之间。介于浅沟隔离区域202上表面与第一鳍与第二鳍206上表面之间定义出第一距离207a。第一距离207a小于图1C中的高度107约15～20nm。换言之，浅沟隔离(STI)区域202上表面的高度(相对于鳍206的上表面)高于浅沟隔离(STI)区域102(相对于鳍106的上表面)约15～20nm。举例而言，于一些实施例中，第一距离207a可以为约80nm(对应于图1C中的距离107为约100nm)。
半导体基材201可以是块状硅、块状硅锗(bulk SiGe)、或其他III-V族化合物基材。基材包括数个鳍206，以及复数个位于成对的鳍206间的浅沟隔离(STI)区域202，虽然只有单一个浅沟隔离(STI)区域202显示于图中。
浅沟隔离(STI)区域的形成包括形成凹口(recess)于硅基材上，与利用化学气相沉积法(chemical vapor deposition，CVD)(例如低压化学气相沉积法(LPCVD)或等离子体增强型化学气相沉积法(PECVD))形成介电薄膜，之后利用化学机械研磨法(chemical mechanical polishing，CMP)移除多余的浅沟隔离介电材料薄膜。浅沟隔离(STI)区域可以填充四乙氧基硅烷(TEOS)、氧化硅(SiO)、氮化硅(SiN)或类似的材料。浅沟隔离(STI)区域可以由各种工艺形成。于一实施例中，在大于500℃的温度下，借由低压化学气相沉积法沉积浅沟隔离(STI)介电材料。
图3A与图3B显示轻掺杂源极(lightly doped drain，LDD)/环状注入步骤(pocket implant step)203，其中借由注入少量的杂质至相邻于沟道区域的源极/漏极区域中。杂质例如磷、硼或类似的材料。进行轻掺杂源极(lightly doped drain，LDD)注入之后，对基材进行退火。
图4A与图4B显示形成虚设侧壁(dummy side walls，DSW)210，211。虚设侧壁(dummy side walls，DSW)210，211的形成是借由连续沉积氧化物与氮化物的顺应层，以及使用非等向性蚀刻(例如干式蚀刻)从水平表面移除氧化物与氮化物，同时保留两种材料于相邻于栅极电极的垂直表面上。
图5A与图5B显示外延硅锗(SiGe)延伸层206e沉积于高于浅沟隔离(STI)区域202上表面的第一鳍与第二鳍上表面与侧表面之上。如此一来，得到一较小第二高度207a介于浅沟隔离(STI)区域202上表面与第一鳍与第二鳍206的上表面之间，鳍延伸部分206e的侧向延伸206L并不会像图1D中鳍延伸部分106e的侧向延伸一样靠近。因此，介于鳍延伸部分206e的间隔距离(window)206w大于鳍延伸部分106e的间隔距离(window)106w。接着，由于虚设侧壁(dummy side walls，DSW)211被移除，因此未显示于图5A与图5B中。
图6A与图6B显示从浅沟隔离(STI)区域202中移除部分材料的工艺，以增加浅沟隔离(STI)区域202上表面与第一鳍与第二鳍206上表面的距离，从第一距离207a变成第二距离207b，其中第二距离207b大于第一距离207a约15～20nm。于一些实施例中，借由将基材浸入稀释的氢氟酸(HF)溶液中以移除浅沟隔离(STI)介电材料。也可使用其他蚀刻剂，以选择性地移除浅沟隔离(STI)介电材料，而不蚀刻栅极结构或硅锗延伸部分206e。从浅沟隔离(STI)区域202移除部分材料的步骤包括降低浅沟隔离(STI)区域的上表面至低于鳍延伸部分206e一段距离(H1-H2)。
图7A与图7B显示沉积一顺应性应力介电材料214于鳍206、浅沟隔离(STI)区域202与鳍式场效晶体管(FinFET)200的栅极电极之上。顺应性应力介电材料214具有一不同于底下浅沟隔离(STI)介电材料202的晶格间距(lattice spacing)，因此可对沟道产生压缩或伸张应力。举例而言，于PMOS晶体管中，需要使用应力层，例如SiNx，以产生压缩应力。于其他实施例中，于NMOS晶体管中，可使用应力层材料对沟道产生伸张应力。可使用SiOx层以于NMOS中产生伸张应力。可借由各种等向性方法(isotropic method)沉积应力薄膜，包括原子层沉积法(atomic layer deposition，ALD)、化学气相沉积法(chemical vapor deposition，CVD)、低压化学气相沉积法(low pressure CVD，LPCVD)、等离子体增强型化学气相沉积法(plasma enhanced CVD，PECVD)或类似的方法。于图7A与图7B中的实施例中，应力材料214为氮化硅薄膜，借由等离子体增强型化学气相沉积法(PECVD)沉积而得。于沉积的同时，选定应力材料薄膜214的厚度T1，因此经由如图8A与图8B的回焊步骤之后，位于浅沟隔离(STI)区域202之上的应力材料214r即可具有一所需厚度T2，以注入所需应力材料的量。举例而言，顺应的薄膜214的厚度T1可大约表示为T1＝T2＊(A2/A1)，
其中T1为顺应性薄膜的沉积厚度，
T2为应力薄膜所需的最后厚度，
A2为浅沟隔离(STI)区域的表面积，以及
A1为顺应性薄膜214初始的水平表面积。
图8A与图8B显示回焊顺应性应力介电材料214的工艺，将应力介电材料导入一高于浅沟隔离(STI)区域202且介于第一鳍与第二鳍之间的空间中，以形成一应力层214r用于施加应力到鳍式场效晶体管(FinFET)的沟道中。于一些实施例中，回焊步骤会留下相邻于栅极电极208的应力材料垂直薄膜214s，以形成侧壁间隙壁。当回焊后的应力材料214r(例如SiNx)形成于浅沟隔离介电(例如SiOx)202上表面之上时，会对接触蚀刻停止层(contact etch stop layer)施加一约1GPa～3GPa的压缩应力。于一些实施例中，对对接触蚀刻停止层(contact etch stop layer)的压缩应力会调整成1.5GPa～3GPa。于一些实施例中，应力为约2.3GPa。显示于图8A中的距离T3与T4(凹口深度)是可变的，将会于图11与图12中进行讨论。
于一些实施例中，借由等离子体增强型化学气相沉积法(PECVD)沉积应力材料214，接着于约300℃下加热基材进行回焊。于其他实施例中，可借由非等向性(anisotropic)等离子体蚀刻步骤进行回焊。回焊的步骤包括将充足的应力材料214从鳍206上表面与硬掩模212导入到介于鳍206之间与高于浅沟隔离(STI)区域202之上的空间，以部分地填充此空间而达到一高于鳍延伸部分206e底部的高度T2。
图9A与图9B显示形成侧壁间隙壁214s之后，进行源极与漏极掺杂注入217的工艺。
图10显示依据上述的制法形成的鳍式场效晶体管(FinFET)的照片。图中也显示接触蚀刻停止层(contact etch stop layer)220与层间介电层(interlayer dielectric，ILD)230。由于浅沟隔离(STI)区域202的上表面为约100nm宽，鳍硅锗(SiGe)延伸部分206e在介于相邻鳍延伸部分之间具有足够的间隔距离(ample window)，以避免在介于鳍延伸部分206e之间或位于鳍延伸部分206e之上的层间介电层(ILD)230中形成孔洞(voids)。介于鳍延伸部分之间的间隔距离(window)是足够的，以利于切割(singulation)。
图11与图12使用此处所述的尺寸的模拟数据。图11显示沟道应力与高于硅锗延伸部分底部的应力材料T3的厚度和低于硅锗延伸部分底部的应力材料T4的厚度的函数关系图(对应到图6A与图6B中移除浅沟隔离介电材料的厚度)。曲线1101显示当应力薄膜具有T3＝15nm厚度与1.5GPa应力时，凹口深度T4(图8A与图9A)与鳍式场效晶体管(FinFET)的沟道应力的关系。曲线1102显示当应力薄膜具有T3＝15nm厚度与3GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的沟道应力的关系。曲线1103显示当应力薄膜具有T3＝7nm厚度与1.5GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的沟道应力的关系。曲线1104显示当应力薄膜具有T3＝5nm厚度与1.5GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的沟道应力的关系。曲线1105显示当应力薄膜具有T3＝7nm厚度与3GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的沟道应力的关系。曲线1106显示当应力薄膜具有T3＝5nm厚度与3GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的沟道应力的关系。
图12显示图11中所述的六种情形的PMOS漏极饱和电流(Idsat)的增加比率。曲线1201-1206的标号对应到曲线1101-1106的标号。曲线1201显示当应力薄膜具有T3＝15nm厚度与1.5GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的漏极饱和电流(Idsat)变化的关系。曲线1202显示当应力薄膜具有T3＝15nm厚度与3GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的漏极饱和电流(Idsat)变化的关系。曲线1203显示当应力薄膜具有T3＝7nm厚度与1.5GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的漏极饱和电流(Idsat)变化的关系。曲线1204显示当应力薄膜具有T3＝5nm厚度与1.5GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的漏极饱和电流(Idsat)变化的关系。曲线1205显示当应力薄膜具有T3＝7nm厚度与3GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的漏极饱和电流(Idsat)变化的关系。曲线1206显示当应力薄膜具有T3＝5nm厚度与3GPa应力时，凹口深度T4与鳍式场效晶体管(FinFET)的漏极饱和电流(Idsat)变化的关系。曲线1202、1205与1206显示接触蚀刻停止层的压缩应力为约3GPa与凹口深度T4为约20nm时，漏极饱和电流(Idsat)会增加约8％。
虽然本发明已以数个优选实施例揭示如上，然而其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (10)

1.一种鳍式场效晶体管的制法，包括以下步骤：
从一半导体基材之上延伸形成一鳍式场效晶体管的第一鳍与第二鳍，其中一浅沟隔离区域位于该第一鳍与该第二鳍之间，且该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间具有一距离；
提供一第一与第二鳍延伸部分于高于该浅沟隔离区域的上表面之上的该第一鳍与该第二鳍的上表面与侧表面之上；
从该浅沟隔离区域移除部分材料，以增加介于该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间的该距离；
沉积一顺应性应力介电材料于该第一鳍、该第二鳍与该浅沟隔离区域之上；
回焊该顺应性应力介电材料，以使其流入介于该第一鳍与该第二鳍之间且高于该浅沟隔离区域上表面之上的一空间，以施加应力到该鳍式场效晶体管的一沟道。
2.如权利要求1所述的鳍式场效晶体管的制法，其中该沉积步骤包括沉积该顺应性应力介电材料于该鳍式场效晶体管的一栅极电极之上。
3.如权利要求2所述的鳍式场效晶体管的制法，其中该回焊步骤包括于相邻该栅极电极之处留下该顺应性应力介电材料的一薄膜，以形成侧壁间隙壁。
4.如权利要求3所述的鳍式场效晶体管的制法，形成该侧壁间隙壁之后，尚包括：进行源极与漏极掺杂注入。
5.如权利要求1所述的鳍式场效晶体管的制法，其中提供一第一与第二鳍延伸部分的步骤包括沉积一硅锗薄膜于该第一鳍、该第二鳍的上表面与侧壁表面之上。
6.如权利要求1所述的鳍式场效晶体管的制法，其中从该浅沟隔离区域移除部分材料的步骤包括降低该浅沟隔离区域的上表面至低于该鳍延伸部分一距离。
7.如权利要求6所述的鳍式场效晶体管的制法，其中该回焊步骤包括将充足的应力介电材料导入一高于该浅沟隔离区域之上的空间，以至少部分地填充该空间至高于该鳍延伸部分的底部一高度。
8.如权利要求1所述的鳍式场效晶体管的制法，其中该顺应性应力介电材料对位于该鳍延伸部分之上的接触蚀刻停止层施加一约1GPa～3GPa的压缩应力。
9.一种鳍式场效晶体管，包括：
一鳍式场效晶体管的一第一鳍与一第二鳍从一半导体基材之上延伸，其中一浅沟隔离区域具有一浅沟隔离介电材料且位于该第一鳍与该第二鳍之间，且该浅沟隔离区域上表面与该第一鳍、该第二鳍上表面之间具有一距离；
一栅极电极位于该第一鳍与该第二鳍之上；
一第一与第二硅锗鳍延伸部分位在高于该浅沟隔离区域的上表面之上的该第一鳍与该第二鳍的上表面与侧表面之上；
一顺应性应力介电材料位于该第一鳍与该第二鳍之间且高于该浅沟隔离区域上表面之上的一空间，以施加应力到该鳍式场效晶体管的一沟道；以及
该顺应性应力介电材料的一薄膜相邻于该栅极电极，以形成侧壁间隙壁。
10.如权利要求9所述的鳍式场效晶体管，其中该顺应性应力介电材料的一上表面高于该硅锗鳍延伸部分的底部。
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