CN110047926B - 半导体装置以及其制作方法 - Google Patents

半导体装置以及其制作方法 Download PDF

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CN110047926B
CN110047926B CN201810035934.7A CN201810035934A CN110047926B CN 110047926 B CN110047926 B CN 110047926B CN 201810035934 A CN201810035934 A CN 201810035934A CN 110047926 B CN110047926 B CN 110047926B
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fin
cladding layer
semiconductor device
gate structure
fin structures
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CN110047926A (zh
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丁煦
林猷颖
陈彦兴
陈俊仁
游峻伟
林耿任
王俞仁
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United Microelectronics Corp
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Abstract

本发明公开一种半导体装置以及其制作方法。半导体装置包括半导体基底、隔离结构、包覆层与栅极结构。半导体基底包括多个鳍状结构。隔离结构设置于多个鳍状结构之间。各鳍状结构包括第一部分与第二部分。第一部分设置于隔离结构的上表面之上。第二部分设置于第一部分上。第二部分的宽度小于第一部分的宽度。包覆层设置于各鳍状结构的第一部分与第二部分上，且包覆层具有一曲面。栅极结构跨设于多个鳍状结构上。

Description

半导体装置以及其制作方法
技术领域
本发明涉及一种半导体装置以及其制作方法，尤其是涉及一种包括鳍状结构的半导体装置以及其制作方法。
背景技术
半导体集成电路的技术随着时间不断地进步成长，每个新世代制作工艺下的产品都较前一个世代具有更小且更复杂的电路设计。在各芯片区域上的功能元件因产品革新需求而必须使其数量与密度不断地提升，当然也就使得各元件几何尺寸需越来越小。在集成电路中，晶体管为很重要的半导体元件。近年来，相关业界提出以立体或非平面(non-planar)多栅极晶体管元件如鳍式场效晶体管(fin field effect transistor，FinFET)元件来取代平面晶体管元件。然而，为了满足元件几何尺寸持续微缩的设计要求，仍需持续改良鳍式场效晶体管的结构或/及材料设计，达到兼顾制作工艺良率以及提升元件效能的效果。
发明内容
本发明提供了一种半导体装置以及其制作方法，形成具有位于隔离结构的上表面之上的第一部分以及位于第一部分上的第二部分的鳍状结构，且第二部分的宽度小于第一部分的宽度，并于鳍状结构的第一部分与第二部分上形成具有曲面的包覆层，由此提升半导体装置的电性表现。
本发明的一实施例提供一种半导体装置，半导体装置包括一半导体基底、一隔离结构、一包覆层与一栅极结构。半导体基底包括多个鳍状结构。隔离结构设置于多个鳍状结构之间。各鳍状结构包括一第一部分与一第二部分。第一部分设置于隔离结构的一上表面之上。第二部分设置于第一部分上。第二部分的宽度小于第一部分的宽度。包覆层设置于各鳍状结构的第一部分与第二部分上，且包覆层具有一曲面。栅极结构跨设于多个鳍状结构上。
本发明的一实施例提供一种半导体装置的制作方法，包括下列步骤。首先，提供一半导体基底，且半导体基底包括多个鳍状结构。在多个鳍状结构之间形成一隔离结构。各鳍状结构包括一第一部分与一第二部分。第一部分位于隔离结构的一上表面之上，而第二部分位于第一部分上。第二部分的宽度小于第一部分的宽度。在各鳍状结构的第一部分与第二部分上形成一包覆层，且包覆层具有一曲面。形成一栅极结构跨过多个鳍状结构。
附图说明
图1为本发明第一实施例的半导体装置的示意图；
图2为本发明第一实施例的半导体装置的立体示意图；
图3至图5为本发明第一实施例的半导体装置的制作方法示意图，其中
图4为图3之后的状况示意图；
图5为图4之后的状况示意图；
图6为本发明第二实施例的半导体装置的示意图；
图7至图11为本发明第三实施例的半导体装置的制作方法示意图，其中
图8为图7之后的状况示意图；
图9为图8之后的状况示意图；
图10为图9之后的状况示意图；
图11为图10之后的状况示意图。
主要元件符号说明
10 半导体基底
10F 鳍状结构
20 隔离结构
30 包覆层
40D 虚置栅极结构
40G 栅极结构
40M 金属栅极结构
50 间隙子
60 介电层
91 蚀刻制作工艺
92 选择性外延成长制作工艺
101-103 半导体装置
CS 曲面
D1 第一方向
D2 第二方向
D3 第三方向
P1 第一部分
P2 第二部分
P3 第三部分
S1 第一上表面
S2 第二上表面
SW1 第一侧壁
SW2 第二侧壁
TR 栅极沟槽
W1 第一宽度
W2 第二宽度
W3 第三宽度
具体实施方式
请参阅图1与图2。图1所绘示为本发明第一实施例的半导体装置的示意图，而图2所绘示为本实施例的半导体装置的立体示意图。如图1与图2所示，本实施例提供一半导体装置101，半导体装置101包括一半导体基底10、一隔离结构20、一包覆层30与一栅极结构40G。在一些实施例中，半导体基底10可包括硅基底、外延硅基底、硅锗基底、碳化硅基底或绝缘层覆硅(silicon-on-insulator，SOI)基底，但并不以此为限。半导体基底10包括至少一鳍状结构10F，而鳍状结构10F可包括一半导体材料的鳍状结构，例如硅半导体鳍状结构。在本实施例中，半导体基底10可包括多个鳍状结构10F，各鳍状结构10F可沿一第一方向D1延伸，且多个鳍状结构10F可沿一第二方向D2重复排列，而第一方向D1可大体上与第二方向D2正交，但并不以此为限。鳍状结构10F可经由对半导体基底10进行图案化制作工艺(例如多重曝光制作工艺与蚀刻制作工艺)而形成。隔离结构20设置于多个鳍状结构10F之间。
隔离结构20可被视为一浅沟槽隔离结构，且隔离结构20可包括单层或多层的绝缘材料例如氧化物绝缘材料，但并不以此为限。各鳍状结构10F可部分被隔离结构20覆盖而部分未被隔离结构20覆盖，而各鳍状结构10F未被隔离结构20覆盖的部分可于半导体基底10的厚度方向(例如图1与图2中所示的第三方向D3)上位于隔离结构20的一上表面(例如图1中所示的第一上表面S1)之上，而第一上表面S1可为隔离结构20于第三方向D3上的最上表面，但并不以此为限。更明确地说，各鳍状结构10F可包括一第三部分P3、一第一部分P1以及一第二部分P2依序于第三方向D3上排列设置。各鳍状结构10F的第三部分P3可被隔离结构20覆盖，而各鳍状结构10F的第一部分P1与第二部分P2则未被隔离结构20覆盖。换句话说，各鳍状结构10F的第一部分P1与第二部分P2可于第三方向D3上设置于隔离结构20的第一上表面S1之上，而第二部分P2于第三方向D3上设置于第一部分P1上。第二部分P2的宽度(例如图1中所示的第二宽度W2)小于第一部分P1的宽度(例如图1中所示的第一宽度W1)。此外，第一部分P1的第一宽度W1以及第二部分P2的第二宽度W2也可被视为于第二方向D2上的长度，但并不以此为限。
包覆层30设置于各鳍状结构10F的第一部分P1与第二部分P2上，且包覆层30具有一曲面CS。更明确地说，包覆层30的曲面CS可为包覆层30未与鳍状结构10F接触的一表面，但并不以此为限。由于覆盖于鳍状结构10F的第一部分P1与第二部分P2的包覆层30具有向外凸出的曲面CS，且包覆层30可分别设置于各鳍状结构10F的第一部分P1与第二部分P2于第二方向D2上的相对两侧，故设置于多个鳍状结构10F中的一个上的包覆层30的宽度(例如图1中所示的第三宽度W3)可大于鳍状结构10F的第一部分P1的第一宽度W1。上述的第一宽度W1、第二宽度W2以及第三宽度W3可分别为第一部分P1、第二部分P2以及一个鳍状结构10F上的包覆层30的最大宽度，但并不以此为限。在一些实施例中，包覆层30的晶格常数可不同于鳍状结构10F的晶格常数，例如包覆层30的材料可包括锗(Ge)、硅锗(SiGe)、磷化硅(SiP)或其他适合的半导体材料，而包覆层30以及鳍状结构10F的第一部分P1与第二部分P2可被视为半导体装置101中的通道区。此外，相邻的两个鳍状结构10F上的包覆层30可彼此互相分离，但并不以此为限。在一些实施例中，设置于各鳍状结构10F的第一部分P1与第二部分P2两侧的包覆层30可对各鳍状结构10F的第一部分P1与第二部分P2产生压缩应力，进而可增加通道的载流子迁移率，但并不以此为限。
在一些实施例中，包覆层30可设置于各鳍状结构10F的第一部分P1的一侧壁(例如图1中所示的第一侧壁SW1)上以及各鳍状结构10F的第二部分P2的一侧壁(例如图1中所示的第二侧壁SW2)上，且各鳍状结构10F的第一部分P1的侧壁的斜率可小于各鳍状结构10F的第二部分P2的侧壁的斜率。上述的第一侧壁SW1的斜率与第二侧壁SW2的斜率可基于一水平面(例如由第一方向D1与第二方向D2所构成的一平面)而计算出，但并不以此为限。换句话说，各鳍状结构10F的第二部分P2的第二侧壁SW2可比第一部分P1的第一侧壁SW1陡峭，而此第一侧壁SW1与第二侧壁SW2的分布状况可通过蚀刻制作工艺所形成，但并不以此为限。
如图1与图2所示，栅极结构40G跨设于多个鳍状结构10F上。在一些实施例中，栅极结构40G可沿第二方向D2延伸，但并不以此为限。此外，栅极结构40G可包括一虚置栅极结构、一金属栅极结构或其他适合型态的栅极结构。上述的虚置栅极结构可为金属栅极(replacement metal gate，RMG)制作工艺中的虚置栅极结构，而此虚置栅极结构的材料可包括例如多晶硅、非晶硅等半导体材料，但并不以此为限。在一些实施例中，栅极结构40G也可视需要包括导电材料与绝缘材料，例如金属栅极结构中的低电阻率金属导电材料、功函数金属层以及高介电常数介电层等，但并不以此为限。此外，各栅极结构40G的侧壁上可设置一间隙子50。间隙子50的材料可包括氧化物、氮化物、氮氧化物或其他适合的绝缘材料，且间隙子50可由单层或多层的上述的材料层所形成。在一些实施例中，间隙子50也可部分设置于包覆层30上，但并不以此为限。此外，栅极结构40G可部分设置于包覆层30上，而栅极结构40G与包覆层30之间可因为包覆层30具有的向外凸出的曲面CS而使得栅极结构40G与包覆层30之间的接触面积增加，进而可提升半导体装置101的电性表现。此外，在一些实施例中，各鳍状结构10F的第二部分P2的一上表面(例如图1中所示的第二上表面S2)可未被包覆层30覆盖，但并不以此为限。
请参阅图3至图5以及图1。图3至图5所绘示为本发明第一实施例的半导体装置的制作方法示意图，而图1可被视为绘示了图5之后的状况示意图。如图1所示，本实施例的半导体装置101的制作方法可包括下列步骤，首先，提供半导体基底10，且半导体基底10包括多个鳍状结构10F。在多个鳍状结构10F之间形成一隔离结构20。各鳍状结构10F包括第一部分P1与第二部分P2。第一部分P1于第三方向D3上位于隔离结构20的第一上表面S1之上，而第二部分P2位于第一部分P1上。第二部分P2的第二宽度W2小于第一部分P1的第一宽度W1。然后，在各鳍状结构10F的第一部分P1与第二部分P2上形成包覆层30，且包覆层30具有曲面CS。形成栅极结构40G跨过多个鳍状结构10F。
进一步说明，本实施例的半导体装置101的制作方法可包括但并不限于下列步骤。首先，如图3所示，通过对半导体基底10进行图案化制作工艺而形成鳍状结构10F之后，形于半导体基底10以及鳍状结构10F上形成隔离材料，并对此隔离材料进行回蚀刻(etchingback)而将各鳍状结构10F的上部暴露出且形成隔离结构20。换句话说，隔离结构20的第一上表面S1于第三方向D3上低于各鳍状结构10F的最上表面。接着，如图4所示，对未被隔离结构20覆盖的鳍状结构10F进行一蚀刻制作工艺91，用以形成上述的第一部分P1与第二部分P2。换句话说，在一些实施例中，各鳍状结构10F的第一部分P1以及第二部分P2可于形成隔离结构20之后对多个鳍状结构10F进行蚀刻制作工艺91所形成，但并不以此为限。值得说明的是，蚀刻制作工艺91可包括一各向同性蚀刻制作工艺，例如一使用四甲基氢氧化铵(tetramethylammonium hydroxide，TMAH)的湿式蚀刻制作工艺或使用其他适合的蚀刻剂的湿式蚀刻制作工艺。通过湿式蚀刻的蚀刻剂对于鳍状结构10F中不同晶格方向的蚀刻率差异，可获得上述各鳍状结构10F的第一部分P1与第二部分P2的宽度与侧壁状况的差异。举例来说，当鳍状结构10F为硅鳍状结构时，四甲基氢氧化铵对于硅的<111>晶面的蚀刻率会低于<100>晶面的蚀刻率，由此可形成宽度较大的第一部分P1且使得第一部分P1的第一侧壁SW1的斜率小于第二部分P2的第二侧壁SW2的斜率。
接着，如图5所示，在各鳍状结构10F的第一部分P1与第二部分P2上形成包覆层30。在一些实施例中，形成包覆层30的步骤可包括一选择性外延成长(selective epitaxialgrowth，SEG)制作工艺92，但本发明并不以此为限。在一些实施例中，一可视需要使用其他制作工艺例如沉积制作工艺与图案化制作工艺来形成包覆层30。由于覆盖于鳍状结构10F的第一部分P1与第二部分P2的包覆层30具有向外凸出的曲面CS，且包覆层30可分别形成于各鳍状结构10F的第一部分P1与第二部分P2于第二方向D2上的相对两侧，故形成于多个鳍状结构10F中的一个上的包覆层30的第三宽度W3可大于鳍状结构10F的第一部分P1的第一宽度W1。此外，包覆层30可形成于各鳍状结构10F的第一部分P1的第一侧壁SW1上以及各鳍状结构10F的第二部分P2的第二侧壁SW2上，且第一侧壁SW1的斜率可小于第二侧壁SW2。然后，如图1所示，形成栅极结构40G与间隙子50。换句话说，在一些实施例中，栅极结构40G可于形成包覆层30的步骤之后形成，且栅极结构40G可包括一虚置栅极结构、一金属栅极结构或其他适合型态的栅极结构。此外，栅极结构40G可部分形成于包覆层30上，且栅极结构40G可于第二方向D2上位于相邻的两鳍状结构10F上的包覆层30之间。
如图1与图2所示，在一些实施例中，未被栅极结构40G覆盖的鳍状结构10F与包覆层30的部分区域可形成源极/漏极区，而源极/漏极区可通过对未被栅极结构40G覆盖的鳍状结构10F与包覆层30的部分区域进行掺杂制作工艺而形成，或者也可将未被栅极结构40G覆盖的鳍状结构10F与包覆层30的部分区域部分移除以再形成源极/漏极区所需的外延层。换句话说，在一些实施例中，源极/漏极区的外延层可与通道区的包覆层30一并形成，由此达到简化制作工艺的效果，但并不以此为限。
下文将针对本发明的不同实施例进行说明，且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件是以相同的标号进行标示，以利于各实施例间互相对照。
请参阅图6。图6所绘示为本发明第二实施例的半导体装置102的示意图。如图6所示，与上述第一实施例不同的地方在于，在半导体装置102中，包覆层30可还设置于各鳍状结构10F的第二部分P2的第二上表面S2上。换句话说，在半导体装置102的制作方法中，可通过调整形成包覆层30的制作工艺条件(例如选择性外延成长的制作工艺条件)，使得包覆层30可还形成于各鳍状结构10F的第二部分P2的第二上表面S2上。
请参阅图7至图11。图7至图11所绘示为本发明第三实施例的半导体装置的制作方法示意图。与上述第一实施例不同的地方在于，如图7所示，可形成一虚置栅极结构40D跨过多个鳍状结构10F。在一些实施例中，虚置栅极结构40D的材料可包括例如多晶硅、非晶硅等半导体材料，但并不以此为限。此外，间隙子50可形成于虚置栅极结构40D的侧壁上，而一层间介电层60可形成而覆盖虚置栅极结构40D与间隙子50，并通过一平坦化制作工艺例如化学机械研磨(chemical mechanical polishing)制作工艺将虚置栅极结构40D上的层间介电层60移除而暴露出虚置栅极结构40D。接着，如图8所示，将虚置栅极结构40D移除而形成被间隙子50围绕的栅极沟槽TR，用以暴露出各鳍状结构10F的一部分。换句话说，栅极沟槽TR可暴露出未被隔离结构20覆盖的鳍状结构10F的上部。然后，如图9所示，进行蚀刻制作工艺91，用以形成鳍状结构10F的第一部分P1以及第二部分P2。换句话说，在一些实施例中，如图7至图9所示，虚置栅极结构40D可于蚀刻制作工艺91之前形成，且虚置栅极结构40D可于蚀刻制作工艺91之前被移除，但并不以此为限。接着，如图10所示，可利用一制作工艺例如选择性外延成长制作工艺92于被栅极沟槽TR暴露出的各鳍状结构10F的第一部分P1与第二部分P2上形成包覆层30。之后如图9与图10所示，在栅极沟槽TR中形成栅极结构40G，而此栅极结构40G可包括一金属栅极结构40M。在一些实施例中，金属栅极结构40M可由高介电常数介电层、功函数金属层、阻障层以极低电阻率金属导电材料等所构成，但并不以此为限。换句话说，本实施例的半导体装置103可包括金属栅极结构40M跨设于多个鳍状结构10F以及包覆层30上。
综上所述，在本发明的半导体装置以及其制作方法中，可通过蚀刻制作工艺形成鳍状结构位于隔离结构的上表面之上的第一部分与第二部分，且第二部分的宽度小于第一部分的宽度，并于鳍状结构的第一部分与第二部分上形成具有曲面的包覆层。包覆层以及鳍状结构的第一部分与第二部分可形成半导体装置的通道区，而位于鳍状结构的第一部分与第二部分两侧的包覆层可对鳍状结构的产生压缩应力，进而可增加通道的载流子迁移率。此外，栅极结构与包覆层之间可因为包覆层具有的向外凸出的曲面而使得栅极结构与包覆层之间的接触面积增加，由此可更进一步提升半导体装置的电性表现。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种半导体装置，其特征在于，包括：
半导体基底，其中该半导体基底包括多个鳍状结构；
隔离结构，设置于该多个鳍状结构之间，其中各该鳍状结构包括：
第一部分，设置于该隔离结构的一上表面之上；以及
第二部分，设置于该第一部分上，其中该第二部分的宽度小于该第一部分的宽度；
包覆层，设置于各该鳍状结构的该第一部分与该第二部分上，其中该包覆层具有一曲面，且各该鳍状结构的该第二部分的上表面未被该包覆层覆盖；
栅极结构，跨设于该多个鳍状结构上，其中该栅极结构部分位于相邻的两个该鳍状结构上的该包覆层之间，该包覆层的该曲面的一部分面对并接触该栅极结构，且该包覆层以及该鳍状结构的该第一部分与该第二部分为该半导体装置的通道区；以及
间隙子，设置于该包覆层上。
2.如权利要求1所述的半导体装置，其中该栅极结构部分设置于该包覆层上。
3.如权利要求1所述的半导体装置，其中各该鳍状结构的该第一部分与该第二部分未被该隔离结构覆盖。
4.如权利要求1所述的半导体装置，其中设置于该多个鳍状结构中的一个上的该包覆层的宽度大于该鳍状结构的该第一部分的该宽度。
5.如权利要求1所述的半导体装置，其中该包覆层设置于各该鳍状结构的该第一部分的一侧壁上以及各该鳍状结构的该第二部分的一侧壁上。
6.如权利要求5所述的半导体装置，其中各该鳍状结构的该第一部分的该侧壁的斜率小于各该鳍状结构的该第二部分的该侧壁的斜率。
7.如权利要求1所述的半导体装置，其中该包覆层的晶格常数不同于各该鳍状结构的晶格常数。
8.一种半导体装置的制作方法，其特征在于，包括：
提供一半导体基底，其中该半导体基底包括多个鳍状结构；
在该多个鳍状结构之间形成一隔离结构，其中各该鳍状结构包括：
第一部分，位于该隔离结构的一上表面之上；以及
第二部分，位于该第一部分上，其中该第二部分的宽度小于该第一部分的宽度；
在各该鳍状结构的该第一部分与该第二部分上形成一包覆层，其中该包覆层具有一曲面，且各该鳍状结构的该第二部分的上表面未被该包覆层覆盖；
形成一栅极结构跨过该多个鳍状结构，其中该栅极结构部分位于相邻的两个该鳍状结构上的该包覆层之间，该包覆层的该曲面的一部分面对并接触该栅极结构，且该包覆层以及该鳍状结构的该第一部分与该第二部分为该半导体装置的通道区；以及
在该包覆层上形成间隙子。
9.如权利要求8所述的半导体装置的制作方法，其中该栅极结构部分形成于该包覆层上。
10.如权利要求8所述的半导体装置的制作方法，其中各该鳍状结构的该第一部分以及该第二部分是在形成该隔离结构之后进行一蚀刻制作工艺所形成。
11.如权利要求10所述的半导体装置的制作方法，其中该蚀刻制作工艺包括一使用四甲基氢氧化铵的湿式蚀刻制作工艺。
12.如权利要求8所述的半导体装置的制作方法，其中该栅极结构于形成该包覆层的步骤之后形成，且该栅极结构包括一虚置栅极结构或一金属栅极结构。
13.如权利要求8所述的半导体装置的制作方法，其中形成于该多个鳍状结构中的一个上的该包覆层的宽度大于该鳍状结构的该第一部分的该宽度。
14.如权利要求8所述的半导体装置的制作方法，其中该包覆层形成于各该鳍状结构的该第一部分的一侧壁上以及各该鳍状结构的该第二部分的一侧壁上。
15.如权利要求14所述的半导体装置的制作方法，其中各该鳍状结构的该第一部分的该侧壁的斜率小于各该鳍状结构的该第二部分的该侧壁的斜率。
16.如权利要求8所述的半导体装置的制作方法，其中形成该包覆层的步骤包括一选择性外延成长制作工艺。
17.如权利要求8所述的半导体装置的制作方法，其中该包覆层的晶格常数不同于各该鳍状结构的晶格常数。
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