CN102169887A - 在沟道与漏极区之间包括掺杂区的电子器件及其形成方法 - Google Patents
在沟道与漏极区之间包括掺杂区的电子器件及其形成方法 Download PDFInfo
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- CN102169887A CN102169887A CN2011100335158A CN201110033515A CN102169887A CN 102169887 A CN102169887 A CN 102169887A CN 2011100335158 A CN2011100335158 A CN 2011100335158A CN 201110033515 A CN201110033515 A CN 201110033515A CN 102169887 A CN102169887 A CN 102169887A
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Abstract
本发明涉及在沟道与漏极区之间包括掺杂区的电子器件及其形成方法。电子器件可以包括晶体管的漏极区,其中,该漏极区具有第一导电类型。所述电子器件还可以包括晶体管的沟道区,其中,该沟道区具有与第一导电类型相反的第二导电类型。该电子器件还可以包括具有第一导电类型的第一掺杂区,其中,该第一掺杂区从漏极区向沟道区延伸。该电子器件还可以包括具有第一导电类型的第二掺杂区,其中,该第二掺杂区设置在第一掺杂区与沟道区之间。
Description
技术领域
本公开涉及电子器件和形成电子器件的方法,并且更具体地说,涉及在沟道区与漏极区之间包括掺杂区的电子器件及其形成方法。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是普通类型的功率切换器件。MOSFET包括:源极区、漏极区、在源极区与漏极区之间延伸的沟道区、以及靠近沟道区设置的栅极结构。该栅极结构包括栅电极层,该栅电极层靠近沟道区设置,并且通过薄电介质层与沟道区分离。
当MOSFET处于接通状态时,将电压施加至栅极结构,以在源极区与漏极区之间形成导电沟道区,这允许电流流过该器件。在关断状态下,施加至栅极结构的任何电压都足够低,使得没有显著电流流过晶体管的沟道。在关断状态期间,该器件应当支持源极区与漏极区之间的高电压。
在特定的应用中,可以使用一对功率晶体管,以允许在两个不同的电压之间切换输出。该输出可以连接至高压侧功率晶体管(high-sidetransistor)的源极并连接至低压侧功率晶体管(low-side transistor)的漏极。当高压侧功率晶体管激活时,输出将处于与高压侧功率晶体管的漏极上的电压相对应的电压,而当低压侧功率晶体管激活时,输出将处于与低压侧功率晶体管的源极相对应的电压。在特定的实际实施例中,高压侧功率晶体管和低压侧功率晶体管典型地为在通过接合导线或其它类似互连部彼此互连的分离的管芯(die)上的分立晶体管。互连部增加了电子器件(包括高压侧和低压侧功率晶体管)的寄生特性,这是不希望的。
附图说明
通过示例的方式例示了实施例,并且实施例并不限制于附图中。
图1包括电子器件的一部分的电路图。
图2包括工件的一部分的例示截面图,该工件包括埋入导电区、埋入绝缘层、以及半导体层。
图3包括图2的工件在形成焊盘层、停止层以及将沟槽蚀刻到工件中之后的例示截面图。
图4包括图3的工件在将垂直导电结构形成在沟槽内之后的例示截面图。
图5包括图4的工件在将导电插头形成在垂直导电结构上之后的例示截面图。
图6和7包括图5的工件在将注入物屏蔽(implant screen)层、水平取向掺杂区以及漏极区形成在该工件的形成有高压侧和低压侧功率晶体管的部分内之后的例示截面图。
图8包括图6和7的工件在形成绝缘部件之后的例示截面图。
图9包括图8的工件在形成构图导电层之后的例示截面图。
图10包括图9的工件在形成绝缘部件并且从构图导电层形成导电电极之后的例示截面图。
图11包括图10的工件在形成牺牲间隔体和牺牲部件之后的例示截面图。
图12包括图11的工件在去除了牺牲间隔体之后的注入步骤期间的例示截面图。
图13包括图12的工件在去除牺牲部件并且形成绝缘间隔体之后的例示截面图。
图14包括图13的工件在形成沟道区和深主体掺杂区之后的例示截面图。
图15包括图14的工件在形成栅电极、源极扩展区以及主体区之后的例示截面图。
图16包括该工件在图15所标注的位置处的例示放大图。
图17包括图15的工件在形成间隔体和重掺杂源极区之后的例示截面图。
图18包括该工件在图17所标注的位置处的例示放大图。
图19包括图17的工件在形成另一组间隔体、蚀刻重掺杂源极区的多个部分以及形成重掺杂主体接触区之后的例示截面图。
图20包括该工件在图19所标注的位置处的例示放大图。
图21包括图19的工件在形成硅化物部件之后的例示截面图。
图22和23包括图21的工件在形成高压侧和低压侧晶体管的晶体管结构的第一级互连部之后的例示截面图。
图24包括图14的工件的放大部分的例示截面图,以例示因注入物散乱(implant straggle)而造成的可能的掺杂轮廓。
本领域技术人员清楚图中部件出于简化和清楚目的而例示,并且不必按比例绘制。例如,图中一些部件的尺寸可以相对于其它部件放大,以帮助提高对本发明实施例的理解。
具体实施方式
结合附图提供以下描述,以帮助理解在此公开的教导。以下讨论聚焦在本教导的特定实现例和实施例上。提供这种聚焦以帮助对本教导的描述,而不应被解释为对本教导的范围或可应用性的限制。然而,可以基于本申请中公开的教导来使用其它实施例。
如在此使用的,针对区域或结构的术语“水平取向”和“垂直取向”指电流流过这种区域或结构的主要方向。更具体地说,电流可以沿垂直方向、水平方向或垂直方向与水平方向的组合流过区域或结构。如果电流沿垂直方向或组合方向(其中,垂直分量大于水平分量)流过区域或结构,则将这种区域或结构称为垂直取向。类似的是,如果电流沿水平方向或组合方向(其中,水平分量大于垂直分量)流过区域或结构,则将这种区域或结构称为水平取向。
术语“金属”或其任何变体意指包括处于1族至12族中的任一族内、13族至16族内的元素,沿原子序数13(Al)、31(Ga)、50(Sn)、51(Sb)以及84(Pb)所定义的线和线下的元素的材料。金属不包括Si或Ge。
术语“正常操作”和“正常操作状态”指设计操作电子组件或器件的条件。这些条件可以从有关电压、电流、电容、电阻或其它电气参数的数据表或其它信息来获取。因而,正常操作不包括完全超出其设计极限地操作电气组件或器件。
术语“功率晶体管”意指以下的晶体管,其被设计成正常操作使得在晶体管的源极与漏极或发射极与集电极之间保持至少10V电压差。例如,当晶体管处于关断状态时,可以在源极与漏极之间保持10V,而不会出现结击穿或其它不希望的状况。
术语“包括”、“包含”、“具有”、“具备”或其任何其它变体都旨在覆盖非排它性的包含。例如,包括一系列特征的方法、物品或装置不必仅限于那些特征,而可以包括未明确列举或这种方法、物品或装置所固有的其它特征。而且,除非明确地相反规定,“或者”指包含性或,而非异或。例如,条件A或B按照以下中的任一种来满足;A为真(或存在)并且B为假(或不存在),A为假(或不存在)并且B为真(或存在),以及A和B都为真(或存在)。
此外,使用“一”或“一个”来描述在此描述的部件和组件。这仅仅出于方便的目的,并且赋予本发明的范围的一般性意义。这种描述应当被理解成包括一个、至少一个、或单个(也包括多个),或反之亦然,除非很明显其具有另外的解释。例如,当在此描述单个项目时,可以使用多于一个的项目代替单个项目。类似的是,在此描述多于一个的项目的情况下,可以用单个项目代替该多于一个的项目。
与元素周期表内的列相对应的族序数使用“新符号”约定,如在CRC Handbook of Chemistry and Physics,81stEdition(2000-2001)中看到的。
除非另外定义,在此使用的所有技术和科学术语都具有本发明所属技术领域的普通技术人员一般理解的含义。材料、方法以及示例仅仅是例示性的而非旨在进行限制。对于在此未描述到的范围,有关特定材料和处理行为的许多细节是常规的,并且可以在半导体和电子领域内的教科书和其它来源中找到。
图1包括电子器件10的一部分的电路图。在如图1所示实施例中,电子器件10可以包括功率切换电路。电子器件10包括晶体管12,其中,该晶体管12的漏极区耦接至诸如VD的端子,而该晶体管12的源极区耦接至诸如VOUT的端子。电子器件10还包括晶体管14,其中,晶体管14的漏极区耦接至晶体管12的源极,而晶体管14的源极区耦接至诸如VS的端子。晶体管12和14的栅电极可以耦接至控制单元16的控制端子162和164。在一具体实施例中,控制单元16可以被设置成在任意特定时间点仅使晶体管12和14中的一个启动。当晶体管12启动(而晶体管14禁用)时,VOUT大致为VD,而当晶体管14启动(而晶体管12禁用)时,VOUT大致为VS。控制单元16可以用于确定VOUT何时从VS切换到VD及其频繁程度,反之亦然。在更特定的实施例中,晶体管12和14可以是高频电压调节器内的功率切换晶体管。
下面对与晶体管12和14相对应的物理结构和形成这种物理结构的方法进行描述。在下面的描述中,晶体管12可以被称为高压侧功率晶体管,而晶体管14可以被称为低压侧功率晶体管。大部分描述将聚焦在形成高压侧功率晶体管的物理结构上,然而,形成低压侧功率晶体管是类似的。在实施例中,晶体管12和14是同一集成电路的一部分。在一具体实施例中,控制单元16和晶体管12与14在同一集成电路上。
图2包括工件200的一部分的例示截面图,该工件包括:埋入导电区202、埋入绝缘层204、以及半导体层206。埋入导电区202可以包括14族元素(即,碳、硅、锗,或其任何组合),并且可以重n型或P型掺杂。出于本说明书的目的,重掺杂意指至少大约1x1019个原子/cm3的峰值掺杂物浓度,而轻掺杂意指小于大约1x1019个原子/cm3的峰值掺杂物浓度。埋入导电区202可以是重掺杂衬底(例如,重n型掺杂晶片)的一部分,或者可以是设置在具有相反导电类型的衬底上或设置在衬底与埋入导电区202之间的另一埋入绝缘层(未例示)上的埋入掺杂区。在实施例中,埋入导电区202通过n型掺杂物(如磷、砷、锑,或其任何组合)重掺杂。在一具体实施例中,如果埋入导电区202的扩散要保持较低,则埋入导电区202包括砷或锑,并且在一具体实施例中,埋入导电区202包括锑以在形成随后形成的半导体层期间减少自动掺杂的程度(与砷相比)。埋入导电区202被用于将高压侧功率晶体管的源极和低压侧功率晶体管的漏极电连接在一起,并且成为电子器件的输出节点的一部分。
埋入绝缘层204设置在埋入导电区202上。在正常操作期间,埋入绝缘层204帮助将埋入导电区202上的电压与半导体层206的多个部分隔离。埋入绝缘层204可以包括氧化物、氮化物、或氮氧化物。埋入绝缘层204可以包括单一膜或具有相同或不同组分的多个膜。埋入绝缘层204可以具有至少大约0.2微米或至少大约0.3微米的范围中的厚度。而且,埋入绝缘层可以具有不大于大约5.0微米或不大于大约2.0微米的厚度。在一具体实施例中,埋入绝缘层204具有大约0.5微米至大约0.9微米的范围中的厚度。
半导体层206设置在埋入绝缘层204上并且具有形成晶体管和其它电子组件(未例示)的主表面205。半导体层206可以包括14族元素(即,碳、硅、锗,或其任何组合)和如关于埋入导电区202所述的任何掺杂物或具有相反导电类型的掺杂物。在实施例中,半导体层206是具有大约0.2微米至大约5.0微米的范围中的厚度的轻掺杂n型或p型外延硅层,其中掺杂浓度不大于大约1×1017个原子/cm3,而在另一实施例中,掺杂浓度为至少大约1×1014个原子/cm3。半导体层206可以设置在整个工件200上。所形成的半导体层206内的或在选择性地掺杂该半导体层206内的区域之前的掺杂物浓度将被称为背景掺杂物浓度。
工件200可以利用多种制造技术来形成。在一实施例中,可以使用晶片结合技术。例如,埋入导电区202和半导体层206可以是结合在一起的不同衬底的部分。可以从一个或两个衬底以热方式生长氧化物。在一具体实施例中,埋入导电区202可以包括靠近生长氧化物的表面的较低掺杂。埋入导电区202内的掺杂浓度可能因在与氧化物的界面处的掺杂物堆积而稍高。因而,埋入导电区202除了靠近氧化物界面的部分外可以重掺杂,并且所述部分可以具有与氧化物层隔开的最低掺杂物浓度。在结合之后,可以去除所述衬底中的一个衬底的大部分,以剩下半导体层206。从所述衬底中的一个或两个以热方式生长的氧化物层可以形成埋入绝缘层204的至少一部分。在另一实施例中,埋入导电区202可以采用重掺杂晶片的形式。半导体层206可以从埋入导电区202外延生长。可以执行氧注入和退火,以从埋入导电区202、半导体层206或两者的部分形成埋入绝缘层204。在阅读本说明书后,本领域技术人员将认识到工件200可以利用其它技术形成。
参照图3,焊盘层302和停止层304(例如,抛光停止层或蚀刻停止层)利用热生长技术、淀积技术,或其组合顺序地形成在半导体层206上。焊盘层302和停止层304中的每一个层都可以包括氧化物、氮化物、氮氧化物、或其任何组合。在一实施例中,焊盘层302与停止层304相比具有不同组分。在一具体实施例中,焊盘层302包括氧化物,而停止层304包括氮化物。
将构图掩模层(未例示)形成在停止层304上。形成半导体层206和埋入绝缘层204内的沟槽322,其中,将形成垂直导电结构。在一具体实施例中,去除焊盘层302、停止层304、半导体206以及埋入绝缘层204的暴露部分。使用各向异性蚀刻技术来形成图3的实施例所示的结构。在另一实施例中,基本上不去除埋入绝缘层204的任何部分,而在另一实施例中,仅去除设置在开口之下的埋入绝缘层204的部分厚度或大致全部厚度。在一具体实施例中,每一个沟槽322的宽度至少大约0.05微米或大约0.1微米,而在另一具体实施例中,每一个沟槽322的宽度不大于大约2微米或大约1微米。可以在形成沟槽322之后去除构图掩模层。
绝缘间隔体324可以形成在沟槽322内。绝缘间隔体324(也可以称为绝缘衬里)可以帮助电隔离半导体层206与顺序地形成在沟槽322内的垂直导电结构。在所示实施例中,可以执行热氧化,以形成绝缘间隔体324。在另一实施例中(未例示),可以共形地淀积以及各向异性蚀刻绝缘层以形成绝缘间隔体。绝缘间隔体324具有大约20nm至大约200nm的范围中的宽度。
图4包括在延伸沟槽并且形成垂直导电结构422之后的例示图。可以去除沿沟槽322的底部的任何剩余绝缘材料(如氧化物)(如图3所示),并且沟槽322可以延伸到埋入导电区202中,以形成沟槽延伸部402。在一实施例中,沟槽延伸部402可以为至少大约0.2微米到埋入导电区202中,而在另一实施例中,沟槽延伸部402可以为至少大约0.3微米。在另一的实施例中,沟槽延伸部402可以为不大于大约5.0微米,而在又一实施例中,不大于大约2.0微米。在另一实施例中,沟槽延伸部可以比上述更深或更浅。去除绝缘材料并且形成沟槽延伸部402可以利用各向异性蚀刻技术来执行。
在停止层304上和沟槽322内形成导电层,并且在一具体实施例中,导电层基本上充满沟槽322。导电层可以是多晶的,并且包括含金属或含半导体层材料。在一实施例中,导电层可以包括重掺杂半导体材料,如非晶硅或多晶硅。在另一实施例中,导电层包括多个膜,如粘附膜、阻挡膜、以及导电填充材料。在一具体实施例中,粘附膜可以包括难熔金属,如钛、钽、钨等;阻挡膜可以包括难熔金属氮化物(如氮化钛、氮化钽、氮化钨等)或者难熔金属半导体氮化物(如TaSiN);而导电填充材料可以包括钨或硅化钨。在一更具体实施例中,导电层可以包括Ti/TiN/Si。选择膜的数量和这些膜的组分取决于电气性能、后续热循环的温度、另一标准、或其任何组合。难熔金属和难熔含金属化合物可以经得起高温(例如,难熔金属的熔点可以为至少1400℃),可以共形地淀积,并且具有比重掺杂n型硅更低的体电阻率。在阅读本说明书之后,本领域技术人员能够确定导电层的组分满足他们对于特定应用的需要或者希望。在形成导电层期间,可以在沟槽322内形成空隙424(void)。如果形成空隙424,则它们典型地位于埋入绝缘层204的区域附近。因而,在图4所示的实施例中,基本上全部空隙424都设置在与半导体层206的主表面205的高度(elevation)隔开的高度处。具体来说,基本上全部空隙424都设置在不高于半导体层206的厚度的大约一半的高度处。
去除导电层的、设置在停止层304上的一部分以在沟槽322内形成垂直导电结构422,如图4的实施例所示。这种去除可以利用化学机械抛光或毯式蚀刻技术来执行。停止层304可以被用作抛光停止层或蚀刻停止层。抛光或蚀刻可以在到达停止层304之后持续相对较短时间,以解决横跨工件的关于导电层的厚度的不均匀性、抛光或蚀刻操作的不均匀性或其任何组合。若需要或希望的话,可以使用连续蚀刻或其它去除操作以使垂直导电结构422进一步凹进到沟槽322中,如图4中箭头426所示。这种凹进可以允许随后形成的高压侧晶体管结构的源极区和低压侧晶体管结构的漏极区电连接至垂直导电结构422。当采用完成的电子器件的形式时,垂直导电结构422和埋入导电区202的组合将高压侧功率晶体管的源极电连接至低压侧功率晶体管的漏极。
参照图5,当存在停止层304的多个部分时(图5中未例示),蚀刻焊盘层302并且底切停止层304的一部分以暴露半导体层206的靠近沟槽322的部分。在图4所示实施例中的这点上,可以执行对沟槽填充材料的附加蚀刻,以暴露沟槽衬里材料324的上表面。接着去除停止层304的多个部分。将导电插头522形成在沟槽内并且帮助将垂直导电结构422电连接至随后形成在半导体层206内的掺杂区。除了导电插头522可以凹进到沟槽322内或可以不凹进到沟槽322内以外,导电插头522可以利用形成垂直导电结构422的任何材料和任何方法来形成。导电插头522和垂直导电结构422可以包括相同或不同材料并且可以利用相同技术或不同技术来形成。导电插头522和垂直导电结构422的组合可以形成垂直取向导电区542。下面,垂直取向导电区542可以指垂直导电结构422、导电插头522,或垂直导电结构422与导电插头522的组合。在该方法中的这点上可以去除焊盘层302。
图6和7例示了在形成注入物屏蔽层602、水平取向掺杂区622、以及漏极区624之后的工件。图6包括高压侧功率晶体管12的晶体管结构的部分,而图7包括低压侧功率晶体管14的晶体管结构的部分。注入物屏蔽层602形成在主表面205上并且可以包括氧化物、氮化物,或氮氧化物,以及可以具有大约2nm至大约90nm的范围的厚度。注入物屏蔽层602可以通过热生长或淀积技术来形成。
在图6和7所示的实施例中,水平取向掺杂区622可以形成在形成高压侧和低压侧功率晶体管的晶体管结构的大致所有区域上。在功率晶体管内,水平取向掺杂区622可以是形成功率晶体管的漂移区的主要部分。在正常操作状态下,电荷载体(例如,电子)或电流主要沿水平方向流过水平取向掺杂区622。如果集成电路包括控制单元16,则可以形成掩模层(未例示)以保护形成控制单元16的电子组件的部分或全部半导体层。水平取向掺杂区622可以具有小于大约1x1019个原子/cm3和至少大约1x1016个原子/cm3的掺杂物浓度,并且在一个实施例中,具有小于大约0.9微米的深度,以及在另一实施例中,具有小于大约0.5微米的深度。
可以形成掩模层(未例示)并构图以限定半导体层206的、形成漏极区624的部分上的开口。在图6中,高压侧晶体管12的漏极区624形成在半导体层206内。漏极区624包括比水平取向掺杂区622相对更高的掺杂物浓度。漏极区624可以具有至少大约1x1019个原子/cm3的掺杂物浓度,并且在一个实施例中,具有小于大约0.9微米的深度,以及在另一实施例中,具有小于大约0.5微米的深度。
在图7中,低压侧晶体管14的漏极区可以包括垂直取向导电区542的上部。在一个实施例中,该上部可以对应于图5中的导电插头522。因而,掩模层可以完全覆盖形成低压侧功率晶体管14的晶体管的半导体层206。在另一实施例中(未例示),如图7所示,可以靠近垂直取向导电区542形成开口,并且可以掺杂该开口下面的半导体层206的部分,以形成与漏极区624相似的漏极区。
在一实施例中,水平取向掺杂区622可以在漏极区624之前形成。在另一实施例中,水平取向掺杂区622可以在漏极区624之后形成。
图8包括在绝缘部件802形成在漏极区624上之后的例示图。尽管图8中未例示,但随着靠近垂直取向导电区542形成低压侧功率晶体管14的晶体管结构的漏极区,绝缘部件802也形成在低压侧晶体管14的垂直取向导电区542上(图7)。绝缘部件802可以帮助减少漏极区与随后形成的导电电极之间的电容耦合,并且提高漏极区624与随后形成的导电电极之间的击穿电压。绝缘部件802可以包括单一绝缘层或多个绝缘层。在图8所示的实施例中,将绝缘层812和814顺序地形成在工件上,其中,绝缘层812和814具有不同组分。例如,绝缘层812可以包括氮化物,而绝缘层814可以包括氧化物。绝缘层814可以帮助减少电容耦合,而绝缘层812可以是漏极接触形成期间的蚀刻停止部。绝缘层812可以具有大约20nm至大约90nm的范围的厚度,而绝缘层814可以具有大约50nm至大约500nm的范围的厚度。
可以将掩模层(未例示)形成在绝缘层814上并且构图以包括设置在形成了晶体管结构的漏极区的部分上的掩模特征。可以将绝缘层814蚀刻成提供锥状轮廓,而绝缘层812可以蚀刻成具有或没有锥状轮廓。掩模层可以在蚀刻绝缘层814之后并且在蚀刻绝缘层812之前或之后去除。
在其它实施例中,绝缘层814的锥状边缘可以利用多种技术来形成。在一实施例中,绝缘层814的组分可以在淀积期间或淀积之间改变。例如,绝缘层814可以包括具有不同组分的多个绝缘膜。在另一实施例中,在淀积的稍后部分期间,可以按增加的浓度来并入诸如磷的掺杂物。在又一实施例中,即使在绝缘层814的整个厚度上组分大致相同,也可以通过改变淀积参数(例如,射频功率、压力等)来改变绝缘层814内的应力。在进一步的实施例中,可以使用前述组合。针对绝缘层814的特定蚀刻技术可以包括:以各向同性方式蚀刻绝缘层814;交替蚀刻绝缘层814的一部分以及蚀刻覆盖掩模特征的侧壁边缘、蚀刻绝缘材料的另一部分并且蚀刻覆盖掩模特征的侧壁的更多部分等;利用不同组分(掺杂氧化物比未掺杂氧化物蚀刻更快速),或其任何组合。
在图9中,导电层902淀积在绝缘部件802上并且构图以形成诸如开口904的开口,其中,漏极接触结构随后制成高压侧功率晶体管12的晶体管结构的漏极区624。导电层902包括导电材料或者例如可以通过掺杂使得其可导电。更具体地说,导电层902可以包括掺杂半导体材料(例如,重掺杂非晶硅、多晶硅等)、含金属材料(难熔金属、难熔金属氮化物、难熔金属硅化物等)、或其任何组合。导电层902具有大约0.05微米至大约0.5微米的范围中的厚度。在一具体实施例中,导电层902用于形成导电电极。
图10包括形成在漏极区624和水平取向掺杂区622的部分上的绝缘部件1002。该绝缘部件1002可以通过形成一个或多个构图绝缘层来形成。在图10所示的实施例中,绝缘层1012和绝缘层1014淀积在导电层902上。绝缘层1012和1014可以包括:氧化物、氮化物、或任何氮氧化物,并且在一具体实施例中,相对于彼此具有不同的组分。例如,绝缘层1012可以包括氧化物,而绝缘层1014可以包括氮化物。绝缘层1012具有大约0.2微米至大约2.0微米的范围中的厚度,而绝缘层1014具有大约20nm至大约900nm的范围中的厚度。
掩模层(未例示)形成在绝缘层1014上并且构图以形成设置在绝缘层1014上、形成绝缘部件1002的位置处的掩模特征。将导电层902和绝缘层1012与1014的部分构图,并且去除掩模特征。构图导电层902形成用于高压侧功率晶体管12和低压侧功率晶体管14的分开的导电电极1032。用于高压侧功率晶体管12的导电电极1032电连接至随后形成的高压侧功率晶体管12的源极区,而用于低压侧功率晶体管14的导电电极1032(图10中未例示)电连接至随后形成的低压侧功率晶体管14的源极区。
绝缘间隔体1022沿绝缘层1012与1014和导电电极1032的侧壁形成。在一具体实施例中,绝缘间隔体1022包括氮化物并且通过将氮化物层淀积至大约20nm至90nm的范围中的厚度接着各向异性蚀刻该氮化物层以形成绝缘间隔体1022来形成。开口1042设置在半导体层206的将形成源极区和沟道区的部分上。
图11包括形成在开口1042内的牺牲间隔体1102和牺牲部件1122。牺牲间隔体1102的宽度对应于将至少部分地形成在水平取向掺杂区622内的掺杂区的宽度。随后形成的掺杂区的重要性后面将在本说明书中进行描述。牺牲间隔体1102的、在牺牲间隔体1102的基部测量出的宽度(下面,称为“间隔体宽度”)可以为水平取向掺杂区622的深度的至少大约0.11倍。该间隔体宽度可以不大于水平取向掺杂区622的深度的大约5倍。在一实施例中,该间隔体宽度可以处于水平取向掺杂区622的深度的大约0.3倍至大约2倍的范围中。在另一实施例中,间隔体宽度为至少大约0.05微米,而在又一实施例中,该间隔体宽度不大于大约0.3微米。
牺牲部件1122设置在开口1042的靠近水平取向掺杂区622的部分处。牺牲部件1122具有当在去除牺牲间隔体1102之后执行掺杂时足以基本上防止掺杂下层区域的厚度。在一实施例中,牺牲部件1122具有至少大约100nm的厚度。在另一实施例中,牺牲部件1122可以填充开口1042的深度的大约百分之十至百分之七十。随着选择性地去除牺牲间隔体1102,牺牲部件1122不覆盖牺牲间隔体1102的整个顶部。
牺牲间隔体1102与绝缘层1014、绝缘部件1002的绝缘间隔体1022、以及牺牲部件1122相比具有不同的材料。牺牲部件1122与绝缘层1014和绝缘部件1002的绝缘间隔体1022相比具有不同的材料。
在一具体实施例中,绝缘层1014和绝缘间隔体1022包括氮化物,牺牲间隔体1102包括非晶硅或多晶硅,而牺牲部件1122包括有机抗蚀剂材料。牺牲间隔体1102通过将包括非晶硅或多晶硅的层淀积至与间隔体宽度(如前所讨论的)相对应的厚度并且各向异性蚀刻该层来形成。牺牲部件1122可以通过将有机抗蚀剂材料涂覆在工件上和开口1042内来形成。有机抗蚀剂材料可以被反向蚀刻以剩下牺牲部件1122。在一具体实施例中,有机抗蚀剂材料可以利用在检测绝缘层1014、绝缘间隔体1022或牺牲间隔体1102时设置的端点检测来蚀刻。接着,可以使用定时蚀刻来获得牺牲部件1122的希望厚度。
在另一实施例中,牺牲间隔体1102或牺牲部件1122的组分可以改变。例如,牺牲间隔体1102或牺牲间隔体1122可以包括含金属材料。例如,牺牲间隔体1102或牺牲间隔体1122可以包括钨。在又一实施例中,牺牲部件1122可以包括氧化物。例如,重掺杂的、非致密化淀积氧化物与热氧化物或由四乙基原硅酸盐(tetraethylorthosilicate)制成的致密化氧化物相比具有相对高的蚀刻速率。
若需要或希望,牺牲部件1122可以回流。可以执行该回流以减少与牺牲部件1122的、设置在牺牲间隔体1102的多个部分上的多个部分相对的注入物遮蔽(implant shadowing)的似然性。
图12包括工件在掺杂行动以形成掺杂区1222期间的例示图。该掺杂行动可以随着注入而执行。在一实施例中,将离子(箭头1202所示)按大致0°的倾斜注入角(即,大致垂直于半导体层206的主表面205)引导至工件的暴露表面。在另一实施例中,可以使用另一角度,并且在注入期间或注入的多个部分之间旋转工件以减少因绝缘部件而造成的遮蔽影响。如果关注沟道化,则可以以大约7°的倾斜角来执行注入。可以以四个部分执行注入,其中,在每一个部分之间旋转工件大约90°。
掺杂区1222的掺杂物浓度大于水平取向掺杂区622的掺杂物浓度。在一实施例中,掺杂区1222的掺杂物浓度不大于水平取向掺杂区622的掺杂物浓度的大约9倍。在一具体实施例中,掺杂区1222的掺杂物浓度处于水平取向掺杂区622的掺杂物浓度的大约2倍至大约5倍的范围中。在另一具体实施例中,当使用注入时,剂量可以处于大约2x1012个离子/cm2至大约2x1012个离子/cm2的范围中。
掺杂区1222的深度可以不具有具体限定。在一实施例中,掺杂区1222的深度可以比水平取向掺杂区622深不多于大约0.2微米。如果掺杂区1222更深,则它们可能干扰随后形成的深注入区域。如果不形成深注入区域,则掺杂区1222可以更深。在另一实施例中,掺杂区1222可以具有与流过高压侧和低压侧功率晶体管12和14的晶体管结构的主电流相对应的深度。在正常操作期间,如果流过沟道区的电子主要在沟道区的漏极侧的主表面的0.05微米内,则掺杂区1222的深度可以为大约0.05微米深。在另一实施例中,掺杂区1222的深度可以处于水平取向掺杂区622的深度的大约0.5倍至大约2倍的范围中。在又一实施例中,掺杂区1222的深度可以处于牺牲间隔体1102的宽度的大约0.5倍至大约2倍的范围中。
注入的能量可以基于所选掺杂物种类来改变。例如,当注入种类为P+(磷离子)时,该能量可以处于大约40KeV至大约150KeV的范围中,而当注入种类为As+时,该能量可以处于大约100KeV至大约350KeV的范围中。如果高压侧和低压侧功率晶体管是p沟道晶体管(而非n沟道晶体管),在注入种类是B+时,该能量可以处于大约15KeV至大约50KeV的范围中,而当注入种类是BF2 +时,该能量可以处于大约50KeV至大约180KeV的范围中。
在形成掺杂区1222之后,可以去除牺牲部件1122。掺杂区1222的宽度可以是如先前关于牺牲间隔体1102的间隔体宽度描述的任何宽度尺寸。
图13包括在形成另一组绝缘间隔体之后的例示图。这些绝缘间隔体覆盖掺杂区1222,以使它们在随后执行沟道注入时不被逆掺杂(counter dope)。因而,这些绝缘间隔体可以具有如先前关于牺牲间隔体1102的间隔体宽度描述的任何宽度尺寸。在一具体实施例中,绝缘间隔体的宽度处于掺杂区1222的宽度的大约0.8倍至大约1.2倍的范围中。绝缘部件1302和添加了绝缘间隔体的绝缘部件1002大致相同。为简化图13,将另一组绝缘间隔体和绝缘间隔体1022的组合例示为绝缘间隔体1304。该绝缘间隔体1304可以包括与注入物屏蔽层602不同的材料。在一具体实施例中,绝缘间隔体1304可以包括氮化物。在形成绝缘部件之后,通过绝缘部件1302来限定开口1306。
图14包括形成在开口1306之下的沟道区1402和深主体掺杂区1404。沟道区1402靠近半导体层206的主表面205形成,而深主体掺杂区1404与主表面205间隔开。与漏极区624与沟道区1402之间的雪崩击穿相对地,深主体掺杂区1404可以在漏极区624与深主体掺杂区1404之间的雪崩击穿期间提供另选路径。因而,如果发生涉及漏极区624的雪崩击穿,则电流流过深主体掺杂区1404,优先于流过沟道区1402。因此,如果发生雪崩击穿,则沟道区1402永久性地改变的可能性较小。深主体掺杂区1404的深度和浓度可以与沟道区1402的深度和浓度有关。
如果深主体掺杂区1404的深度较浅,则在雪崩击穿期间流动的电流可以包括沟道区1402的多个部分。更具体地说,如果深主体掺杂区1404的最高深度非常深,则将在漏极区624与沟道区1402之间发生雪崩击穿,因此深主体掺杂区1404无法有效地保护沟道区1402。在一实施例中,深主体掺杂区1404的峰值浓度比沟道区1402的峰值浓度深至少大约0.1微米,而在另一实施例中,深主体掺杂区1404的峰值浓度与沟道区1402的峰值浓度相比深不大于大约0.9微米。在另一实施例中,深主体掺杂区1404的峰值浓度处于主表面205下面大约0.6微米至大约1.1微米的范围中。
在一实施例中,深主体掺杂区1404与沟道区1402相比,具有更大的掺杂物浓度。在一具体实施例中,深主体掺杂区1404的峰值浓度可以处于沟道区1402的峰值掺杂物浓度的大约2倍至大约10倍的范围中。
深主体掺杂区1404的宽度可以比绝缘部件1302之间的开口1306宽。深主体掺杂区1404可以通过注入形成,其可以通过突出范围(Rp)和散乱(straggle)(ΔRp)来表征。可以将ΔRp用于近似注入期间掺杂物在半导体层206内的横向侵入(encroachment)。因而,深主体掺杂区1404的显著部分设置在掺杂区1222之下。
深主体掺杂区1404可以利用单一注入或组合注入来形成。深主体掺杂区1404可以接触埋入绝缘层204或可以不接触埋入绝缘层204。随着深主体掺杂区1404的深度的范围增加,在雪崩击穿期间的电流可以在较大区域分布。在一具体实施例中,深主体掺杂区1404可以与埋入绝缘层204间隔开,以减少对埋入导电区202的电容耦合。在另一实施例中,深主体掺杂区1404可以与埋入绝缘层204相接触,以便抑制寄生场效应晶体管,其中,栅极电介质包括埋入绝缘层204。针对单一注入或针对具有最低Rp的注入(组合注入),剂量可以处于大约5x1013个离子/cm2至大约5x1014个离子/cm2的范围中。
沟道区1402可以通过以大约5x1012个离子/cm2至大约5x1013个离子/cm2的范围的剂量进行离子注入来形成。可以选择能量以获得大约0.05微米至大约0.3微米的范围中的Rx。
深主体掺杂区1404可以在沟道区1402之前或之后形成。在一具体实施例中,形成深主体掺杂区1404,并且去除开口1306内所暴露的注入物屏蔽层602的部分。可以在形成沟道区1402之前形成另一注入物屏蔽层(未例示)。该另一注入物屏蔽层可以是氧化物或氮化物。该另一注入物屏蔽层可以比注入物屏蔽层602薄。在一具体实施例中,将该另一注入物屏蔽层热生长至大约11nm至大约50nm的范围中的厚度。针对沟道区1402的离子可以注入通过该另一注入物屏蔽层。
图15包括工件在形成栅极电介质层1502、栅电极1522、沿栅电极1522的暴露表面的绝缘层1524、源极延伸区1542以及主体区1562之后的例示图。注入物屏蔽层602和其它注入物屏蔽层的暴露部分(若存在)通过蚀刻来去除,接着在沿开口1306的底部的暴露表面上形成栅极电介质层1502。在一具体实施例中,栅极电介质层1502包括氧化物、氮化物、氮氧化物或其任何组合,并且具有大约5nm至大约100nm的范围中的厚度。将栅电极1522设置在栅极电介质层1502上。栅电极1522可以通过淀积某材料层来形成,该材料在淀积时是导电的或者可以随后制成导电的。该材料层可以包括含金属或含半导体材料。在一实施例中,将该层淀积至大约0.1微米至大约0.5微米的厚度。蚀刻该材料层以形成栅电极1522。在所示实施例中,栅电极1522在不利用掩模的情况下形成,并且具有侧壁间隔体的形状。
绝缘层1524可以从栅电极1522热生长,或者可以在工件上淀积。绝缘层1524的厚度可以处于大约10nm至大约30nm的范围中。源极延伸区1542可以具有高于大约5x1017个原子/cm3并且小于大约5x1019个原子/cm3的掺杂物浓度。与没有主体区1562相比,主体区1562可以允许沟道区1402和深主体掺杂区1404电结合并且减少在沟道区1402与深主体掺杂区1404之间具有更多电阻的区域的可能性。主体区1562还可以减少晶体管结构的源极与漏极之间的穿通可能性。主体区1562具有与沟道区1402和深主体掺杂区1404相同的导电类型,并且具有至少大约1x1018个原子/cm3的峰值掺杂物浓度。
图16例示了图15中的工件的特征之间的方位关系。距离1582对应于栅电极1522与导电电极1032之间的距离,而宽度1584对应于掺杂区1222的宽度。如图16的实施例所示,掺杂区1222的右侧边缘可以横向延伸至绝缘间隔体1304与导电电极1032之间的分界面之下的点。在另选实施例中,掺杂区1222的右侧边缘可以横向延伸至导电电极1032之下的点。在一具体实施例中,掺杂区1222的横向延伸的右侧边缘不位于绝缘层812和814中的任一个之下。掺杂区1222的左侧边缘可以横向延伸至沟道区1402内的点。宽度1584可以高达距离1582的大约1.5倍,并且在一具体实施例中,宽度1584可以高达距离1582的大约1.2倍。宽度1584没有已知下限。在一实施例中,宽度1584可以是距离1582的至少大约0.2倍,而在另一实施例中,宽度1584可以是距离1582的至少大约0.4倍。
图17包括绝缘间隔体1602和重掺杂源极区1642。图18包括图17的一部分的放大图,以更好地例示工件的特征之间的方位关系。形成绝缘间隔体1602以覆盖源极延伸区1542的多个部分。绝缘间隔体1602可以通过淀积绝缘层并各向异性蚀刻该绝缘层来形成。绝缘间隔体1602可以包括氧化物、氮化物、氮氧化物或其任何组合,并且在绝缘间隔体1602的基部处具有大约50nm至大约200nm的范围中的宽度。重掺杂源极区1642允许随后进行欧姆接触并且具有至少大约1x1019个原子/cm3的掺杂物浓度。重掺杂源极区1642可以利用离子注入来形成。与沟道区1402相比,重掺杂源极区1642具有相反导电类型,并且具有与漏极区624和埋入导电区202相同的导电类型。
图19包括:间隔体1702、开口1704以及重掺杂主体接触区1722。图20包括图19的一部分的放大图,以更好地例示工件的特征之间的方位关系。与图17相比,图19和20未例示图17的中央附近的垂直取向导电区542。在一实施例中,垂直取向导电区542的位置可以相对于彼此偏移,以允许晶体管的更紧凑布局。例如,图19和20的中部附近的、接触重掺杂源极区1642的对应垂直取向导电区542可以进一步向后定位,而不沿图19和20的平面布置。在另一实施例中,高压侧晶体管结构的重掺杂源极区1642可以采用单一重掺杂源极区的形式,而低压侧晶体管结构的重掺杂源极区1642(图19和20未例示)可以采用不同的重掺杂单一源极区的形式。因而,垂直取向导电区542不需要延伸通过同一晶体管结构的对应栅电极1522之间的重掺杂源极区1642的每一个部分。
在图19和20中,形成间隔体1702以限定将形成重掺杂主体接触区1722的多个部分。间隔体1702可以通过淀积绝缘层并且各向异性蚀刻该绝缘层来形成。间隔体1702可以包括氧化物、氮化物、氮氧化物或其任何组合。在一具体实施例中,间隔体1702可以是在形成重掺杂主体接触区之后去除的牺牲间隔体。因而,间隔体1702不必是绝缘材料。开口1704通过彼此面对的间隔体1702的侧面局部地限定。
沿着开口1704的底部,蚀刻栅极电介质层1502和重掺杂源极区1642的多个部分。接着,沿开口1704的底部形成重掺杂主体接触区1722。重掺杂主体接触区1722具有与沟道区1402和深主体掺杂区1404相同的导电类型,并且具有至少大约1x1019个原子/cm3的掺杂物浓度,以允许随后形成欧姆接触。
主体区1562和重掺杂主体接触区1722帮助确保与垂直取向导电区542(当垂直取向导电区542包括含金属的材料时)以及随后形成的金属硅化物区进行良好电气接触。在另一实施例中,可以形成主体区1562,而不形成重掺杂主体接触区1722。在另一实施例中,形成重掺杂主体接触区1722,而不形成主体区1562。在阅读本说明书之后,本领域技术人员能够确定他们需要或希望的电气性能并且确定主体区1562、重掺杂主体接触区1722、或主体区1562和重掺杂主体接触区1722的组合是否被注入。
图21包括导电部件1822和1824。在一实施例中,去除部分或全部间隔体1702,以暴露更多的重掺杂源极区1642。导电部件1822形成在栅电极1522上,并且允许更好的接触和更低的电阻。导电部件1824将重掺杂源极区1642、重掺杂主体接触区1722以及垂直取向导电区542(在存在的情况下)彼此电连接。在一具体实施例中,可以将难熔金属(如Ti、Ta、W、Co、Pt等)淀积在工件上,并且与暴露的硅(如基本上单晶硅或多晶硅)选择性地反应,以形成金属硅化物。去除难熔金属的、覆盖绝缘材料的未反应部分,由此剩下导电部件1822和1824。在该方法的这一点上,形成高压侧和低压侧功率晶体管12和14的晶体管结构。
图22和23包括高压侧功率晶体管12(图22)和低压侧功率晶体管内的晶体管结构在形成第一级互连部之后的例示图。形成中间级电介质(ILD)层1902,并且其可以包括氧化物、氮化物、氮氧化物、或其任何组合。ILD层1902可以包括具有大致恒定或改变的组分(例如远离半导体层206的高磷含量)的单一膜或多个离散膜。可以在ILD层1902内或之上使用蚀刻停止膜、防反射膜或组合以帮助进行处理。可以将ILD层1902平坦化以改进后续处理操作(例如,光刻、后续抛光等)期间的处理裕度。
在图22和23所示的实施例中,将ILD层1902构图,以限定接触开口,并且在接触开口内形成导电插头1922、1924、1926、1928、1932、1934以及1938。导电插头1922和1932分别接触高压侧和低压侧晶体管内的导电电极1032。导电插头1924和1934接触导电部件1824,该导电部件接触重掺杂源极区1642和重掺杂主体接触区1722。导电插头1924和1934分别在高压侧和低压侧晶体管内。导电插头1926接触高压侧晶体管12内的漏极区624。应注意到,没有导电插头接触低压侧晶体管14内的漏极区624。导电插头1928和1938分别接触设置在高压侧和低压侧晶体管内的栅电极1522上的导电部件1822。
形成许多其它导电插头,并且这种其它导电插头在其它视图中可见。尽管图22和23未例示,但高压侧晶体管12内的基本上所有的导电电极1032电连接至导电插头1922,而低压侧晶体管14内的基本上所有的导电电极1032电连接至导电插头1932。高压侧晶体管12内的基本上所有的导电部件1824电连接至导电插头1924或者垂直取向导电区542,而低压侧晶体管14内的基本上所有的导电部件1824电连接至导电插头1934。高压侧晶体管12内的基本上所有的导电部件1822电连接至导电插头1928,而低压侧晶体管14内的基本上所有的导电部件1822电连接至导电插头1938。因而,高压侧晶体管12内的基本上所有的栅电极1522电连接至导电插头1928,而低压侧晶体管14内的基本上所有的栅电极1522电连接至导电插头1938。高压侧晶体管12内的基本上所有的漏极区624电连接至导电插头1926,而低压侧晶体管14内的基本上所有的水平取向掺杂区622电连接至垂直取向导电区542。
形成另一中间级电介质(ILD)层2002,并且其可以包括氧化物、氮化物、氮氧化物或其任何组合。ILD层2002可以包括如先前关于ILD层1902描述的任何组分。与ILD层1902相比,ILD层2002可以具有大致相同的组分或不同的组分。将ILD层2002构图以限定接触开口。
形成互连部2022、2026、2032以及2038,它们至少部分地在ILD层2002内的接触开口内延伸。互连部2022电连接高压侧晶体管12内的导电电极1032和导电部件1824。互连部2032电连接低压侧晶体管14内的导电电极1032、导电部件1824、以及Vs端子(图1)。互连部2026(图22中例示了其中一个)电连接高压侧晶体管12内的漏极区624和VD端子(图1)。互连部2038(图23中例示了其中一个)电连接低压侧晶体管14内的栅电极和控制单元16(图1)。尽管未例示,但其它互连部电连接高压侧晶体管12内的栅电极1522和控制单元16。
尽管未例示,若需要或希望的话,可以使用附加的层或特征或较少的层或特征来形成电子器件。未例示场隔离区,但它可以用来帮助电气隔离高压侧功率晶体管的部分与低压侧功率晶体管的部分。在另一实施例中,可以使用更多绝缘和互连级。可以将钝化层形成在工件上或互连级内。在阅读本说明书之后,本领域技术人员能够确定针对其特定应用的层和特征。
电子器件可以包括和图22和23所示晶体管结构大致相同的许多其它晶体管结构。图22中的晶体管结构可以彼此并联连接以形成高压侧功率晶体管12,而图23中的晶体管结构可以彼此并联连接以形成低压侧功率晶体管14。这种构造可以赋予能够支持在电子器件正常操作期间使用的相对较高电流的电子器件的足够有效的沟道宽度。在一具体实施例中,每一个功率晶体管都可以被设计成具有大约30V的最大源极至漏极电压差,和大约20V的最大源极至栅极电压差。在正常操作期间,该源极至漏极电压差不大于大约20V,而该源极至栅极电压差不大于大约9V。
在又一实施例中,可以使用一个或多个双极晶体管代替场效应晶体管。在这个实施例中,电流运送电极可以包括代替源极区和漏极区的发射极区和集电极区,而控制电极可以包括代替栅电极的基极区。高压侧双极晶体管的发射极可以电连接至低压侧双极晶体管的集电极。如果使用埋入集电极,则可以将该埋入集电极构图以允许对埋入导电区202进行适当的隔离连接。
在此描述的实施例可以包括具有小于大约1×1019个原子/cm3的峰值掺杂物浓度的区域。若需要或希望与含金属材料进行欧姆接触,则可以将这种掺杂区的一部分局部掺杂成具有至少大约1×1019个原子/cm3的峰值掺杂物浓度。在非限制例中,埋入导电区202可以具有小于大约1×1019个原子/cm3的峰值掺杂物浓度。如果垂直导电结构422包括W或WSi,则可以对埋入导电区202的、靠近该垂直导电结构422的部分进行注入,以局部地将峰值掺杂物浓度增加至至少大约1×1019个原子/cm3,从而帮助形成埋入导电区202与垂直导电结构422之间的欧姆接触。在其它实施例中,可以将导电类型颠倒。如在此所述,例示了n沟道晶体管结构。在另选实施例中,可以形成p沟道晶体管结构。
掺杂区1222可以帮助减少因在形成沟道区1402、深主体掺杂区1404、或沟道区1402与深主体掺杂区1404的组合时的注入散乱所造成的逆掺杂的可能性。散乱因离子与半导体层206内的材料(例如,硅原子、锗原子等)碰撞而造成,并且以与注入倾斜角不同的角度偏转。图24包括以下的例示图,该例示图可以示出散乱如何影响沟道区1402附近的掺杂,并且将在说明注入能量如何影响作为Rp的函数的ΔRp之后进行描述。
当表达为分数ΔRp/Rp时,该分数随着注入能量的增加而减小。对B+来说,在20keV下,ΔRp/Rp大约为0.39,在100KeV下,ΔRp/Rp大约为0.22,而在200KeV下,ΔRp/Rp大约为0.18。与深主体掺杂区1404相比,沟道区1402可以以显著较低的注入能量来形成。换句话说,在20KeV下,显著数量的掺杂物可以在绝缘间隔体1304下在大约71nm的深度处横向延伸大约28nm。在100keV下,该横向尺寸在大约330nm的深度可以大约为73nm,而在200KeV下,该横向尺寸在大约560nm的深度可以大约为100nm。
因而,显著数量的掺杂物可以在绝缘间隔体1304下横向延伸。在图24中,散乱可以用虚线2102概念性地表示,而掺杂区1222的受散乱影响的部分可以用掺杂区1222的阴影部分来表示。在不存在掺杂区1222的情况下,对于水平取向掺杂区622将产生类似效果。由于掺杂程度的原因,可能部分地或完全地逆掺杂水平取向掺杂区622的一部分。从电的角度来看,水平取向掺杂区622中的有效掺杂较低,而如果在水平取向掺杂区622内发生完全逆掺杂,则晶体管结构的阈值电压和有效沟道长度增加。在任一情况下,Rdson可以变得无法接受地高。
在形成沟道区1402、深主体掺杂区1404、或沟道区1402与深主体掺杂区1404的组合时,掺杂区122的存在减少了沟道区1402附近的净逆掺杂量。因而,仍可以获得可接受的Rdson区,而不必增加水平取向掺杂区622的与沟道区1402进一步远离的位置处的掺杂浓度。因而,可以基本上不影响漂移区的主要部分(水平取向掺杂区622的、漏极区624与掺杂区1222之间的部分)。掺杂区1222的宽度相对较窄,使得通过漂移区的电阻主要受水平取向区622设置在漏极区624与掺杂区1222之间的部分支配。
存在改变漂移区与沟道区相邻的部分中的掺杂浓度(独立于漂移区的其余部分)的益处。当掺杂区1222靠近沟道区1402的漏极边缘定位时,对击穿电压和阈值电压两者的影响可以降低,而同时仍实现对控制这个区域中的净掺杂浓度的改进。与掺杂整个漂移区相比,在此描述的实施例可以在沟道区1402附近具有数量减少的逆掺杂,因此,晶体管结构的漏极区与沟道区之间的击穿电压不太可能减小,并且输出电容不太可能增加。而且,在此描述的实施例减少了漂移区交叠沟道区的可能性。因而,沟道区也不太可能被逆掺杂,这可以减小阈值电压。因此,形成沟道区的注入物的相应剂量不需要增加,注入物具有还增加漂移区的逆掺杂的不希望的效果。因而,具有掺杂区1222的实施例帮助提供对掺杂物浓度的改进控制,而不会不利地影响晶体管结构的电气性能。
许多不同方面和实施例都是可能的。下面,描述那些方面和实施例中的一些。在阅读本说明书之后,本领域技术人员将认识到那些方面和实施例仅仅是例示性的,而不是限制本发明的范围。
在第一方面,电子器件可以包括晶体管的漏极区,其中,该漏极区具有第一导电类型。该电子器件还可以包括晶体管的沟道区,其中,该沟道区具有与第一导电类型相反的第二导电类型。该电子器件还可以包括具有第一导电类型的第一掺杂区,其中,该第一掺杂区从漏极区向沟道区延伸。该电子器件还可以包括具有第一导电类型的第二掺杂区,其中,该第二掺杂区设置在第一掺杂区与沟道区之间。
在第一方面的一实施例中,第一掺杂区和第二掺杂区中的每一个沿半导体层的主表面布置。在另一实施例中,第二掺杂区具有是第一掺杂区的深度的至少0.11倍的宽度。在一具体实施例中,第二掺杂区具有不大于第一掺杂区的深度的大约5倍的宽度。在又一实施例中,第二掺杂区具有第一掺杂区的深度的大约0.3倍至大约2倍的范围中的宽度。在又一实施例中,第二掺杂区的宽度不大于第一掺杂区的宽度的大约0.5倍。在一具体实施例中,第二掺杂区的宽度至少为第一掺杂区的宽度的大约0.05倍。在进一步的实施例中,第二掺杂区具有不大于大约0.3微米的宽度。在一具体实施例中,第二掺杂区具有至少大约0.05微米的宽度。
在第一方面的又一实施例中,第二掺杂区的峰值掺杂物浓度大于第一掺杂区的峰值掺杂物浓度。在又一实施例中,第二掺杂区的峰值掺杂物浓度不大于第一掺杂区的峰值掺杂物浓度的大约9倍。在另一实施例中,第二掺杂区的峰值掺杂物浓度处于第一掺杂区的峰值掺杂物浓度的大约2倍至大约5倍的范围中。在又一实施例中,第二掺杂区的峰值掺杂物浓度大于沟道区的峰值掺杂物浓度。在一具体实施例中,第二掺杂区的峰值掺杂物浓度不大于沟道区的峰值掺杂物浓度的大约20倍。在又一实施例中,第二掺杂区的峰值掺杂物浓度处于第一掺杂区的峰值掺杂物浓度的大约5倍至大约11倍的范围中。
在第二方面,形成电子器件的方法可以包括形成晶体管的漏极区,其中,漏极区沿半导体层的主表面形成并且具有第一导电类型。该方法还可以包括沿主表面形成具有所述第一导电类型的第一掺杂区,沿主表面形成具有第一导电类型的第二掺杂区,以及形成晶体管的沟道区,其中,沟道区沿主表面形成并且具有与第一导电类型相反的第二导电类型。在形成漏极区、第一掺杂区、第二掺杂区以及沟道区之后,第一掺杂区设置在漏极区与第二掺杂区之间;而第二掺杂区设置在第一掺杂区与沟道区之间。
在第二方面的一实施例中,在形成漏极区和第一掺杂区之后并在形成沟道区之前执行形成第二掺杂区的步骤。在另一实施例中,该方法还包括形成第一间隔体,和去除第一间隔体,其中,执行形成第二掺杂区的步骤使得第二掺杂区在半导体层内的、下面去除第一间隔体的位置处。在一具体实施例中,利用选择性自对准技术来执行形成第二掺杂区的步骤。
在第二方面的另一具体实施例中,该方法还包括在主表面上形成第一层,将第一层构图以限定第一层开口,在形成第一间隔体之后,在主表面上形成第二层,以及去除第二层的与第一层交叠的部分,其中,在去除第一间隔体之前执行去除部分的步骤。在更具体的实施例中,形成间隔体的步骤包括在第一层上并在第一层开口内形成第一间隔体层,并且各向异性蚀刻第一间隔体层以形成第一间隔体。在另一更具体的实施例中,第一层具有与第一侧壁间隔体和第二层不同的组分,而第二层具有与第一侧壁间隔体不同的组分。
在第二方面的又一更具体的实施例中,该方法还包括在形成第一层之前在主表面上形成第三层,构图第三层以限定第三层开口,以及在形成第一侧壁间隔体之前形成第二侧壁间隔体。在更加具体的实施例中,第一层具有与第一侧壁间隔体、第二层以及第三层不同的组分;而第二层具有与第一侧壁间隔体、第二侧壁间隔体以及第三层不同的组分。第三层具有与第一侧壁间隔体不同的组分,而第一侧壁间隔体具有与第二侧壁间隔体不同的组分。在另一更加具体的实施例中,第一层和第二侧壁间隔体中的每一个都包括氮化物,第二层包括有机抗蚀剂材料,第三层包括氧化物,而第一侧壁间隔体包括非晶硅或多晶硅。
在另一具体实施例中,第二掺杂区的宽度和第一侧壁间隔体在其基部处的宽度大致相等。在又一实施例中,形成第一掺杂区的步骤包括将第一掺杂物注入到半导体层中,并且形成第二掺杂区的步骤包括将第二掺杂物注入到第一掺杂区的一部分中。在一具体实施例中,形成第二掺杂区的步骤以大约2×1012个离子/cm2至大约2×1013个离子/cm2的范围中的剂量来执行。在另一具体实施例中,形成第二掺杂区的步骤利用磷离子以大约60keV至大约160KeV的范围中的能量来执行。
应注意到,在上述一般描述或示例中的活动不是全部都需要,可能不需要具体活动的一部分,并且除了所述那些活动以外,还可以执行一个或多个另外活动。更进一步地,列出活动的次序不必是执行它们的次序。
为清楚起见,此处在分离的实施例的背景下描述的特定特征还可以在单一实施例中组合提供。相反,为简短起见,在单一实施例的背景下描述的各种特征还可以分离地或以任意的子组合提供。而且,对范围中规定的值的引用包括该范围中的各个和每一个值。
上面,已经关于具体实施例对益处、其它优点以及针对问题的解决方案进行了描述。然而,可以导致任何益处、优点、或解决方案出现或变得更突出的益处、优点、针对问题的解决方案以及任何特征都不被解释为任何或所有权利要求的关键性、必需、或基本的特征。
在此描述的实施例的说明书和例示图旨在提供对各种实施例的结构的一般性理解。该说明书和例示图不意图用作使用在此描述的结构或方法的装置和***的所有要素和特征的排它性和全面性描述。还可以在单一实施例中组合地提供分离实施例,而相反地,为简短起见,在单一实施例背景下描述的各种特征还可以分离或以任何子组合来提供。而且,针对范围中规定的值的引用包括该范围内的各个或每一个值。本领域技术人员仅在阅读本说明书之后可以清楚许多其它实施例。其它实施例可以被使用并且从本公开导出,使得可以在不脱离本公开的范围的情况下,进行结构性替代、逻辑替代,或另一改变。因此,本公开被视为例示性的而非限制性的。
Claims (17)
1.一种电子器件,包括:
晶体管的漏极区,其中,所述漏极区具有第一导电类型;
所述晶体管的沟道区,其中,所述沟道区具有与所述第一导电类型相反的第二导电类型;
具有所述第一导电类型的第一掺杂区,其中,所述第一掺杂区从所述漏极区向所述沟道区延伸;以及
具有所述第一导电类型的第二掺杂区,其中,所述第二掺杂区设置在所述第一掺杂区与所述沟道区之间。
2.根据权利要求1所述的电子器件,其中,所述第一掺杂区和所述第二掺杂区中的每一个沿半导体层的主表面布置。
3.根据权利要求1所述的电子器件,其中,所述第二掺杂区具有以下宽度,该宽度:
是所述第一掺杂区的深度的至少0.11倍;
是所述第一掺杂区的深度的至少0.3倍;
不大于所述第一掺杂区的深度的大约2倍;
不大于所述第一掺杂区的深度的大约5倍;
在所述第一掺杂区的深度的大约0.3倍至大约2倍的范围中;
是所述第一掺杂区的宽度至少大约0.05倍;
不大于所述第一掺杂区的宽度的大约0.5倍;或
不大于大约0.3微米或至少大约0.05微米。
4.根据权利要求1所述的电子器件,其中,所述第二掺杂区的峰值掺杂物浓度:
大于所述第一掺杂区的峰值掺杂物浓度;
是所述第一掺杂区的峰值掺杂物浓度的至少大约2倍;
不大于所述第一掺杂区的峰值掺杂物浓度的大约5倍;
不大于所述第一掺杂区的峰值掺杂物浓度的大约9倍;或
在所述第一掺杂区的峰值掺杂物浓度的大约2倍至大约5倍的范围中。
5.根据权利要求1所述的电子器件,所述电子器件还包括栅电极和导电电极,其中:
所述栅电极和所述导电电极分开一定距离;并且
所述第一掺杂区的宽度不大于所述距离的大约1.5倍。
6.一种形成电子器件的方法,包括以下步骤:
形成晶体管的漏极区,其中,所述漏极区沿半导体层的主表面形成并且具有第一导电类型;
沿所述主表面形成具有所述第一导电类型的第一掺杂区;
沿所述主表面形成具有所述第一导电类型的第二掺杂区;以及
形成所述晶体管的沟道区,其中,所述沟道区沿所述主表面形成并且具有与所述第一导电类型相反的第二导电类型,
其中,在形成所述漏极区、所述第一掺杂区、所述第二掺杂区以及所述沟道区之后:
所述第一掺杂区设置在所述漏极区与所述第二掺杂区之间;并且
所述第二掺杂区设置在所述第一掺杂区与所述沟道区之间。
7.根据权利要求6所述的方法,还包括以下步骤:
形成第一侧壁间隔体;和
去除所述第一侧壁间隔体,
其中,执行形成所述第二掺杂区的步骤,使得所述第二掺杂区在所述半导体层内的某一位置处,在该位置下面去除所述第一侧壁间隔体。
8.根据权利要求7所述的方法,还包括以下步骤:
在所述主表面上形成第一层;
将所述第一层构图以限定第一层开口;
在形成所述第一侧壁间隔体之后,在所述主表面上形成第二层;以及
去除所述第二层的与所述第一层交叠的部分,其中,在去除所述第一侧壁间隔体之前执行去除部分的步骤。
9.根据权利要求8所述的方法,还包括以下步骤:
在形成所述第一层之前,在所述主表面上形成第三层;
将所述第三层构图以限定第三层开口;以及
在形成所述第一侧壁间隔体之前形成第二侧壁间隔体。
10.根据权利要求9所述的方法,其中:
所述第一层具有与所述第一侧壁间隔体、所述第二层以及所述第三层不同的组分;
所述第二层具有与所述第一侧壁间隔体、所述第二侧壁间隔体以及所述第三层不同的组分;
所述第三层具有与所述第一侧壁间隔体不同的组分;以及
所述第一侧壁间隔体具有与所述第二侧壁间隔体不同的组分。
11.根据权利要求6所述的方法,其中,所述第二掺杂区的宽度和所述第一侧壁间隔体在其基部处的宽度大致相等。
12.根据权利要求6所述的方法,其中:
形成所述第一掺杂区的步骤包括将第一掺杂物注入到所述半导体层中;以及
形成所述第二掺杂区的步骤包括将第二掺杂物注入到所述第一掺杂区的一部分中。
13.根据权利要求7所述的方法,其中,形成所述第二掺杂区的步骤以大约2×1012个离子/cm2至大约2×1013个离子/cm2的范围中的剂量来执行。
14.一种电子器件,包括:
晶体管的漂移区,该漂移区包括具有第一导电类型的水平取向掺杂区;
沟道区,该沟道区具有与所述第一导电类型相反的第二导电类型;
主体区,该主体区具有所述第二导电类型,其中,与所述主体区相比,所述沟道区具有较浅的深度并且进一步向所述水平取向掺杂区延伸;
源极区,该源极区设置在所述主体区上,其中,所述沟道区设置在所述源极区与所述水平取向掺杂区之间;以及
栅电极,该栅电极设置在所述沟道区上,其中,所述主体区最靠近所述水平取向掺杂区的边缘大致对准至所述栅电极的垂直边缘。
15.根据权利要求14所述的电子器件,还包括第一掺杂区,该第一掺杂区设置在所述水平取向掺杂区与所述沟道区之间,其中,所述第一掺杂区具有所述第一导电类型。
16.一种形成电子器件的方法,包括以下步骤:
在半导体层内形成水平取向掺杂区,其中,所述水平取向掺杂区具有第一导电类型并且是晶体管的漂移区的一部分;
在所述水平取向掺杂区上形成绝缘层,其中,所述绝缘层被构图以限定开口;
利用所述半导体层形成沟道区,其中,所述沟道区具有与所述第一导电类型相反的第二导电类型,并且所述沟道区形成在所述绝缘层中的所述开口之下;
在形成所述沟道区之后,在所述沟道区上形成栅电极;
在所述半导体层内形成主体区,其中:
所述主体区具有所述第二导电类型;
所述沟道区设置在所述主体区与所述水平取向掺杂区之间;以及
在形成所述栅电极之后形成所述主体区。
17.根据权利要求16所述的方法,还包括以下步骤:
在所述绝缘层的所述开口内形成牺牲部件,其中,所述牺牲部件与所述绝缘层分隔开;并且
在所述半导体层内、没有被所述牺牲部件或所述绝缘层覆盖的位置处形成第一掺杂区,其中,所述第一掺杂区具有所述第一导电类型;以及
去除所述牺牲部件。
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CN110556412B (zh) * | 2018-05-30 | 2022-10-21 | 台湾积体电路制造股份有限公司 | 具有混合掺杂区的绝缘体上硅半导体器件 |
Also Published As
Publication number | Publication date |
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KR20110092221A (ko) | 2011-08-17 |
TWI436482B (zh) | 2014-05-01 |
KR101753076B1 (ko) | 2017-07-03 |
US20110193143A1 (en) | 2011-08-11 |
CN102169887B (zh) | 2017-01-18 |
TW201140833A (en) | 2011-11-16 |
US8298886B2 (en) | 2012-10-30 |
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