CN102163622B - 包含具有超级结的沟槽mosfet的半导体器件 - Google Patents
包含具有超级结的沟槽mosfet的半导体器件 Download PDFInfo
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Abstract
本申请描述了将MOSFET架构与PN超级结结构相结合的半导体器件以及用于制造该器件的方法。所述MOSFET架构能够被利用包含栅极的沟槽结构制造,所述栅极被夹在顶部的厚绝缘层和沟槽底部之间。超级结结构的PN结被形成在沟槽侧壁中的n-型掺杂区域和p-型外延层之间。沟槽MOSFET的栅极被利用栅极绝缘层与超级结结构隔离。这些半导体器件相对于屏蔽沟槽MOSFET器件能够具有较低的电容和较高的击穿电压并且能够在中压到高压范围内替代这些器件。还描述了其它实施例。
Description
技术领域
本申请涉及半导体器件和用于制造该半导体器件的方法。更特别地,本申请描述了将金属氧化物半导体场效应管(MOSFET)架构与PN超级结结构相结合的半导体器件以及用于制造该器件的方法。
背景技术
包含集成电路(IC)或分立元件的半导体器件被广泛应用于电子设备。IC元件(或芯片,或者分立元件)包括在半导体材料的基材上制造的小型化电子电路。所述电路包括很多重叠的层,包括包含能够扩散到基材内的掺杂剂(称为扩散层)或被注入基材内的离子(注入层)。其它层是导体(多晶硅或金属层)或者导电层之间的连接(通路或接触层)。IC元件或分立元件以叠层工艺制作,所述叠层工艺采用多个步骤的组合,包括生长层、成像、沉积、刻蚀、掺杂和清洗。典型地用硅片作为基材,并且利用光刻术掩膜基材的将要被掺杂的不同区域或者沉积和定义多晶硅、绝缘体、或金属层。
半导体器件的一种类型,金属氧化物半导体场效应管(MOSFET)器件,能够被广泛应用于大量的电子设备中,包括汽车电子设备、驱动设备和供电设备。通常,这些器件用作开关,并且被用于将供电设备连接到负载上。一些MOSFET器件能够以沟槽的形式形成,所述沟槽在基材上形成。使得沟槽结构有吸引力的一个特征是垂直通过MOSFET沟道(channel)的电流。这使得比其它MOSFET具有较高的原胞和/或电流沟道密度,在所述其它MOSFET中电流水平流过沟道并且然后垂直流过漏极。较大的原胞和/或电流沟道密度通常意味着每单位面积的基材上能够制造更多的MOSFET和/或电流沟道,因此增加了包含沟槽MOSFET的半导体 器件的电流密度。
发明内容
本申请描述了将MOSFET架构与PN超级结结构相结合的半导体器件以及用于制造该器件的方法。可以利用包含栅极的沟槽构造制造MOSFET架构,所述栅极夹在顶部的厚绝缘层和沟槽底部之间。超级结结构的PN结形成在沟槽侧壁上的n型掺杂剂区域和N-沟道MOSFET的p-型外延层之间。掺杂剂类型对于P-沟道MOSFET可以相反。沟槽MOSFET的栅极被利用绝缘层与超级结结构分离开。这样的半导体器件相对于屏蔽(shield-based)沟槽MOSFET器件具有较低电容和较高击穿电压并且能够在中压范围内替换这些器件。
附图说明
根据附图能够更好的理解下面的描述,其中:
图1示出了用于制造半导体结构的方法的一些实施例,所述半导体结构包含基材和在其自身表面上具有掩膜的外延层;
图2示出了用于制造包含形成在外延层中的沟槽结构的半导体结构的方法的一些实施例;
图3示出了用于制造具有形成在沟槽中的第一氧化区域的半导体结构的方法的一些实施例;
图4a和4b示出了用于制造具有形成在沟槽中的栅极和栅极绝缘层的半导体结构的方法的一些实施例;
图5a和5b示出了用于制造具有形成在沟槽中栅极上的绝缘盖和形成在外延层中的接触区域的半导体结构的方法的一些实施例;
图6示出了用于制造具有形成在绝缘盖和接触区域上的源极的半导体结构的方法的一些实施例;
图7示出了用于制造具有形成在结构底部的漏极的半导体结构的方法的一些实施例;
图8示出了图7描述的半导体结构的运行的一些实施例;
图9和图10示出了能够出现半导体结构中的PN结的一些实施例。
这些附图描述了半导体器件的特定方面以及用于制造这些器件的方法。结合下面的描述,这些附图描述并解释了这些方法以及通过这些方法产生的结构。在附图中,为了清楚,放大了层和区域的厚度。也可以理解,当一层、部件或基材被称为在另一层、部件或基材“之上”时,该层、部件或基材可以直接位于所述另一层、部件或基材之上,或者还可以存在中间层。不同附图中的相同附图标记代表相同的部件,并且因此将不重复对部件的描述。
具体实施方式
下面的描述提供了具体细节,以提供彻底的理解。然而,本领域技术人员能够理解,不采用这些具体细节,也能够实施和利用这些半导体器件以及制造和利用这些器件的相关方法。实际上,能够通过修改示出的器件和方法将这些半导体器件和相关方法投入实践并且能够结合工业中传统使用的任何其它设备和技术利用这些半导体器件和相关方法。例如,虽然描述了沟槽(trench)MOSFET器件,为了获得形成在沟槽中的其它半导体器件可以对所述沟槽MOSFET器件进行修改,例如静电感应晶体管(SIT)、静电感应晶闸管(SITh)、结型场效应晶体管(JFET)和晶闸管元件。同样地,尽管参考特定类型的传导性(P或N)描述器件,可以通过适当的修改通过相同类型的掺杂剂的结合配置器件或者采用相反类型的传导性(分别N或P)配置器件。
图1-10示出了半导体器件的一些实施例以及用于制造这些器件的方法。在一些实施例中,如图1中所述,当首先提供半导体基材105时,所述方法开始。本领域中公知的任何基材都能够用于本发明。合适的基材包括硅片、外延硅层、例如用于绝缘层上覆硅(SOI)技术中使用的绑定晶圆片,和/或非晶硅层,所有这些基材可以掺杂也可以不掺杂。而且,能够采用用于电子器件的其它半导体材料,包括锗、硅锗、碳化硅、氮化镓、砷化镓、InxGayAsz、AlxGayAsz,和/或任何纯的或合成的半导体材料,例如III-V或II-VI以及它们的变体。在一些实施例中,基材105 能够被利用任何n-型掺杂剂重掺杂。
在一些实施例中,基材105包含一个或多个位于其上表面的外延硅层(单独地或共同地描述为外延层110)。例如,轻掺杂N外延层存在于基材105和外延层110之间。能够利用本领域公知的任意工艺提供外延层110,包括任何公知的外延沉积工艺。外延层能够被利用p-型掺杂剂轻掺杂。
在一些构造中,外延层110内的掺杂浓度是不均匀的。特别地,外延层110能够在上部分具有较高的掺杂浓度以及在下部分具有较低的掺杂浓度。在一些实施例中,外延层能够具有贯穿其深度的浓度梯度,靠近上表面或在上表面上具有较高的浓度以及靠近与基材105的接触面或在与基材105的接触面处具有较低的浓度。沿外延层长度的浓度梯度可以是连贯的减小、阶梯的减小或二者的结合。
在一些获得这样的浓度梯度的构造中,在基材105上提供多个外延层并且每个外延层包含不同的掺杂浓度。外延层的数量可以是从2到更多所需要的数量。在这些构造中,每个接连的外延层沉积在下面的外延层(或基材)上同时通过任何公知的外延层生长方法现场(in-situ)掺杂成较高浓度。外延层110的一个例子包括具有第一浓度的第一外延硅层、具有较高浓度的第二外延硅层、具有更高浓度的第三外延硅层,以及具有最高浓度的第四外延硅层。
接着,如图2所示,沟槽结构120能够形成在外延层110中,并且沟槽的底部能够达到外延层110或者基材105的任何位置。沟槽结构120能够通过任何公知工艺形成。在一些实施例中,可以在外延层110上形成掩膜115。能够通过首先沉积期望掩膜材料的层形成掩膜115并且然后利用光刻和刻蚀工艺在该层上形成图形,从而形成掩膜115的期望图形。在完成用于形成沟槽的蚀刻工艺之后,在相邻的沟槽之间形成台面结构112。
然后通过任何公知工艺蚀刻外延层110直到沟槽120在外延层110中达到期望的深度和宽度。能够控制沟槽120的深度和宽度,还有宽度与深度的纵横比,使得后续沉积的氧化层适当地填充到沟槽中并且避免 形成空缺。在一些实施例中,沟槽的深度可以从大约0.1到大约100μm。在一些实施例中,沟槽的宽度范围可以从大约0.1到大约50μm。基于这样的深度和宽度,沟槽的纵横比范围可以从大约1∶1到大约1∶50。在其它实施例中,沟槽的纵横比范围可以从大约1∶5到大约1∶8.3。
在一些实施例中,沟槽的侧壁不垂直于外延层110的上表面。相反,沟槽侧壁相对于外延层110上表面的角度范围可以从大约90度(垂直侧壁)到大约60度。可以控制沟槽角度,从而后续沉积的氧化层或者任何其它材料适当地填充沟槽并避免形成空缺。
接着,如图2所示,沟槽结构120的侧壁能够用n-型掺杂剂掺杂,使得在靠近沟槽侧壁的外延层中形成侧壁掺杂区域125。可以利用任何掺杂工艺执行侧壁掺杂工艺,所述掺杂工艺将n-型掺杂剂注入到期望的宽度。在掺杂工艺之后,可以利用任何公知的扩散或推阱(drive-in)工艺进一步扩散掺杂剂。侧壁掺杂区域125的宽度可以调节,使得当半导体器件关闭并且电流被阻止时,邻近任何沟槽的台面112能够部分或充分地耗尽(如图8所描述)。在一些实施例中,能够利用任何倾斜注入工艺(angled implant process)、气相掺杂工艺、扩散工艺、沉积掺杂材料(多晶硅、硼磷硅玻璃(BPSG)等)和将掺杂剂推入到侧壁中,或者它们的组合来执行侧壁掺杂工艺。在另一些实施例中,倾斜注入工艺可以采用从大约0度(垂直注入工艺)到大约45度的角度,如箭头113所示。在一些构造中,台面112的宽度、沟槽120的深度、注入角度和沟槽侧壁的角度能够被用于确定侧壁的n-型掺杂区域125的宽度和深度。因此,在这些构造中,其中沟槽的深度范围从大约0.1到大约100μm以及沟槽侧壁的角度范围从大约70度到大约90度,台面的宽度范围从大约0.1到大约100μm。
沟槽具有如在此描述的侧壁角度的情况下,外延层110中的不同掺杂剂浓度帮助形成具有明确PN结的PN超级结结构。由于侧壁角度,随着沟槽深度的增加,沟槽宽度略微减小。当在该侧壁上执行倾斜注入工艺时,在p-型外延层110上形成的n-型侧壁掺杂区域将具有基本类似的角度。PN结的最终结构包含比n-型区域相对大的p-型区域,由于该结构 可能会电荷不平衡,因此有损于PN超级结的性能。通过如上所述的修改外延层110中的掺杂浓度以及增加从器件底部到顶部的掺杂浓度,倾斜注入工艺产生基本笔直(straigher)的PN结而不是如图9和10所示的倾斜PN结。图9示出了包含n-区域225、倾斜沟槽205、栅极210、绝缘层215和外延层200的半导体结构,所述外延层200包括均匀的掺杂浓度。从一个沟槽到另一个沟槽的n-区域255被外延层的P-区域中的距离A分离开。然而距离A比恰当的电荷平衡和耗尽所需要的距离要宽。另一方面,图10中描述的半导体结构包含类似结构,但是外延层200’包含在此描述的梯度掺杂浓度。梯度浓度允许具有较宽底部的n-区域225’的形成和调节,使得n-区域225’之间的距离A’比A小。该构造的结果能够得到相对于图9中的结构更加电荷平衡的半导体结构。
返回图3,氧化层130(或其它绝缘或半绝缘材料)然后能够形成在沟槽120中。氧化层130能够通过本领域公知的任何工艺形成。在一些实施例中,氧化层130能够通过沉积氧化材料直到氧化材料溢出沟槽120为止而形成。氧化层130的厚度能够被调节成填充沟槽120所需要的任何厚度。能够利用任何公知的沉积工艺执行氧化材料的沉积,包括任何化学气相沉积(CVD)工艺,例如能够在沟槽内产生很好的保角阶梯覆盖性(a highly conformal step coverage)的亚常压化学气相沉积(SACVD)。如果需要,可以采用回流工艺以回流氧化材料,这样将有助于减少氧化层中的空缺或缺陷。沉积完氧化层130之后,能够利用回刻工艺以移除额外的氧化材料。在回刻工艺之后,在沟槽120的底部形成氧化区域140,如图4a和4b所示。此外还可以采用平面化工艺,例如本领域公知的任何化学的和/或机械的抛光,或者利用平面化工艺代替回刻工艺。
可选地,可以在沉积氧化层130之前形成高质量的氧化层。在这些实施例中,可以通过在包含氧化物的大气中氧化外延层110直到生长成期望厚度的高质量的氧化层,从而形成所述高质量的氧化层。高质量的氧化层可以用于改善氧化层的完整性和填充系数,从而使得氧化层130成为更好的绝缘体。
底部氧化区域140形成之后,栅极绝缘层(例如栅极氧化层133)在沟槽120的没有被底部氧化区域140覆盖的暴露侧壁上生长,如图4所示。栅极氧化层133通过将沟槽侧壁上的暴露的硅氧化直到生长成期望厚度的任何工艺而形成。
随后,可以在底部氧化区域140上沉积位于沟槽120下、中或上部的导电层。导电层可以包括本领域公知的任何导电的和/或半导电的材料,包括任何金属、硅化物、半导体材料、掺杂多晶硅或它们的组合。导电层可以通过任何公知的沉积工艺进行沉积,包括化学气相沉积工艺(CVD/PECVD/LPCVD)或利用期望金属作为溅射靶材的溅射工艺。
导电层可以被沉积,使得其填充沟槽120的上部分并从沟槽120的上部分溢出。然后,可以利用任何本领域公知的工艺从导电层形成栅极150。在一些实施例中,可以通过利用任何本领域公知的工艺移除导电层的上部分,所述本领域公知的工艺包括任何回刻工艺。移除工艺的结果使得导电层(栅极150)覆盖在沟槽120中的第一氧化区域140上并且夹在栅极氧化层133之间,如图4a所示。在一些实施例中,可以形成栅极150,使得其上表面与外延层110的上表面基本在同一平面上。
然后,能够在外延层110的上部分中形成p-区域145,如图5a和5b所示。可以利用本领域公知的任何工艺形成p-区域。在一些实施例中,能够通过在外延层110的上表面中注入p-型掺杂剂并随后利用任何公知的工艺推阱掺杂剂而形成p-区域145。
接着,可以在外延层110的暴露上表面上形成接触区域135。可以利用本领域公知的任何工艺形成接触区域135。在一些实施例中,能够通过在外延层110的上表面注入n-型掺杂剂并随后利用任何公知的工艺推阱所述掺杂剂而形成接触区域135。图5a和5b示出了形成接触区域135后的最终结构。
然后,利用上覆的绝缘层覆盖栅极的上表面。所述上覆的绝缘层可以是本领域公知的任何绝缘材料。在一些实施例中,所述上覆的绝缘层包括任何包含硼或磷的绝缘材料,包括硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)或硼硅玻璃(BSG)材料。在一些实施例中,可以利用任何CVD 工艺沉积上覆的绝缘层,直到获得期望的厚度。CVD工艺的例子包括等离子体增强化学气相沉积(PECVD)、常压化学气相沉积(APCVD)、亚常压化学气相沉积(SACVD)、低压化学气相沉积(LPCVD)、高密度等离子化学气相沉积(HDPCVD)或它们的组合。当BPSG、PSG或BSG材料被用于上覆的绝缘层时,这些材料能够被回流。
然后上覆的绝缘层的一部分被移除,以剩下绝缘盖。在图5b描述的实施例中,利用任何公知的掩膜和刻蚀程序移除上覆的绝缘层,该掩膜和刻蚀程序移去除栅极150之外的其它位置处的材料。因此,在栅极150上形成绝缘盖165。在图5a描述的实施例中,能够利用任何回刻或平面化工艺移除绝缘层,使得氧化层盖160形成与接触区域135基本同一平面的上表面。
然后,如图6所示,接触区域135和p-区域145能够被刻蚀以形成***区域167。图6(和图7-8)示出了包含栅极150和绝缘盖160的实施例,但是类似的工艺能够用于制造包含栅极150和绝缘盖165的类似半导体器件。能够利用任何公知的掩膜和刻蚀工艺直到达到期望的深度(进入p-区域145)从而形成***区域167。如果期望,如本领域所公知,能够利用p-型掺杂剂执行重体注入(heavy body implant)以形成PNP区域。
接着,如图6所示,源极层(或区域)170能够被在绝缘盖160和接触区域135的上部分上沉积。源极层170可以包括本领域公知的任何导电的和/或半导电的材料,包括任何金属、硅化物、多晶硅或它们的组合。可以通过任何公知的沉积工艺沉积源极层170,包括化学气相沉积工艺(CVD、PECVD、LPCVD)或利用期望金属作为溅射靶材的溅射工艺。源极层170还填充到***区域167。
在源极层170形成之后(或之前),可以利用本领域公知的任意工艺在基材105的背面上形成漏极180。在一些实施例中,能够利用本另一公知的任意工艺通过打薄基材105的背面在背面上形成漏极180,包括磨削、抛光或刻蚀工艺。然后,如本领域所公知,如图6所示,在基材105的背面上沉积导电层直到形成漏极的期望厚度的导电层。
这些制造方法具有几个有用的特点。利用这些方法,能够容易地利用自定位(self-alignment)方法制作接触***区域167(如图5a和6所示)。还有,超级结结构能够以相比于例如长期选择性外延生长的传统工艺低的成本制造。
图7和8示出了由这些方法制造的半导体器件100(包含栅极150和绝缘盖160)的一个例子。在图7中,半导体器件100包括位于器件100上部的源极层170和位于器件底部的漏极180。沟槽MOSFET的栅极150被隔离在底部氧化区域140和绝缘盖160之间。同时,栅极150还与n-型侧壁掺杂区域125隔离,所述n-型掺杂区域125与p-型外延层110一起形成超级结结构的PN结。对于这样的构造,MOSFET的栅极150能够被用于控制半导体器件100中的电流路径。
半导体器件100的运行类似于其它MOSFET器件。例如,类似MOSFET器件,半导体器件通常运行在具有栅极电压为0的关断状态下。当采用低于阈值电压的栅极电压将反向偏置应用到源极和漏极时,耗尽区域185能够扩大并且夹止漂移区域,如图8所示。
半导体器件100具有具备几个特点的架构。首先,半导体器件能够获得高击穿电压(≥大约200v)而不需要高成本的较长外延生长工艺。第二,其具有较低电容,当与较高击穿电压结合时可以替代中压范围(大约200v)运行的屏蔽MOSFET器件。并且相对于屏蔽MOSFET器件,由于减少了工艺步骤在此描述的器件能够以较低费用制造,并且因为这些器件不包含屏蔽氧化物或屏蔽多晶硅结构从而具有较低的热量预算。第三,相对于平面构造,在此描述的器件需要较小的面积并且更适合自定位配置。
半导体器件100还能够相对于其它器件具有较少的与缺陷有关的问题。对于在此描述的器件,一旦形成耗尽区域185,电场方向在厚底部氧化(TBO)区域接近垂直。并且即使在TBO区域形成一些缺陷,器件仍然具有很高的氧化厚度(沿着垂直长度)以承受电压。因此,在此描述的器件还能够具有较低的漏电风险。
并且将沟槽中的MOSFET结构与超级结结构结合能够增加漂移掺杂浓 度并且还能够定义较小的斜度(pitch),所述较小的倾斜能够改善电流传导性和频率(开关速度)。并且由于由N沟槽侧壁和P外延层的结形成的超级结,漂移区域掺杂浓度能够比其它MOSFET结构高的多。
可以理解,在此提供的所有材料的类型仅为了说明的目的。因此,在此描述的实施例中的各种绝缘层中的一个或多个可以包括低-k或高-k绝缘材料。另外,虽然为n-型和p-型掺杂剂指定了特定的掺杂剂,但任何其它公知的n-型或p-型掺杂剂(或其组合)能够用于半导体器件。还有,尽管参考特定的传导性类型(P或N)描述了本发明的器件,器件可以被配置成具有相同类型掺杂剂的组合或者通过适当的修改被配置成相反类型的传导性(分别为N或P)。
在一些实施例中,用于制造半导体器件的方法包括:提供用第一传导性类型的掺杂剂重掺杂的半导体基材;提供位于基材上的外延层,所述外延层被用第二传导性类型的掺杂剂以浓度梯度轻掺杂;提供形成在外延层中的沟槽,所述沟槽包括没有屏蔽电极的MOSFET结构并且还包括用第一传导性类型的掺杂剂轻掺杂的侧壁;提供接触外延层上表面和MOSFET结构上表面的源极层;并且提供接触基材底部的漏极。
在一些实施例中,用于制造半导体器件的方法包括:提供用第一传导性类型的掺杂剂重掺杂的半导体基材,在基材上沉积外延层,所述外延层被用第二传导性类型的掺杂剂轻掺杂并且包含当其靠近基材时具有减小的掺杂浓度,在外延层中形成沟槽,所述沟槽包括从大约90度(垂直侧壁)到大约70度的侧壁角度,利用倾斜注入工艺在沟槽侧壁中形成掺杂区域,所述掺杂区域被利用第一传导类型的掺杂剂轻掺杂,在沟槽的下部分形成第一绝缘区域,在沟槽的上部分形成栅极绝缘区域,在传导性栅极上形成第二绝缘区域,在外延层的上表面上形成接触区域,所述接触区域被用第一传导性类型的掺杂剂重掺杂,在接触层的上表面上和第二绝缘区域的上表面上沉积源极,并且在基材的底部部分上形成漏极。
除了前面描述的修改,本领域技术人员可以在不脱离本发明的精神和范围的情况下进行大量的其它改变和可选的设置,并且所附的权利要 求覆盖这些修改和设置。因此,虽然在上面结合目前最可行的和最优选的方面以特定性和具体细节描述了本发明的信息,但是在不脱离在此描述的原理和主旨的情况下可以进行对于包括但不限于形态、功能、运行和利用方式的大量修改,这对于本领域普通技术人员是显而易见的。而且,如在此所采用的,实施例仅用于说明,而不以任何方式解释成限定。
Claims (15)
1.一种半导体器件,包括:
用第一传导性类型的掺杂剂重掺杂的半导体基材;
基材上的外延层,所述外延层被以第二传导性类型的掺杂剂轻掺杂,其中,所述外延层包含在上表面具有较高浓度和在靠近基材处具有较低浓度的浓度梯度;
形成在外延层中的沟槽,所述沟槽包含没有屏蔽电极的MOSFET结构并且还包含具有从90度到70度的角度范围的侧壁,所述侧壁被用第一传导性类型的掺杂剂轻掺杂,使得在靠近所述侧壁的外延层中形成侧壁掺杂区域,并且所述沟槽的底部的所述第一传导性类型的掺杂剂的扩散宽度大于所述沟槽的顶部的所述第一传导性类型的掺杂剂的扩散宽度,从而减小在沟槽的底部在沟槽之间的所述第二传导性类型的掺杂区域同时形成基本笔直的PN结,其中在相邻的沟槽之间形成台面,所述侧壁掺杂区域的宽度被调节,使得当所述半导体器件关闭且电流被阻止时,邻近任何沟槽的台面能够部分或充分地耗尽;
接触外延层的上表面和MOSFET结构的上表面的源极层;和
接触基材底部的漏极。
2.根据权利要求1所述的器件,其特征在于,所述第一传导性类型的掺杂剂是n-型掺杂剂以及所述第二传导性类型的掺杂剂是p-型掺杂剂。
3.根据权利要求1所述的器件,其特征在于,所述浓度梯度以均匀的或阶梯的方式从所述上表面到基材减小。
4.根据权利要求1所述的器件,其特征在于,所述MOSFET结构包括通过沉积的绝缘材料在沟槽内垂直绝缘的栅极。
5.根据权利要求4所述的器件,其特征在于,所述栅极被以栅极绝缘层与外延层隔离。
6.根据权利要求1所述的器件,其特征在于,所述沟槽侧壁的掺杂剂被以从大于0度到40度范围的角度注入,角度为0时表示垂直于基材表面。
7.一种半导体器件,包括:
用第一传导性类型重掺杂的半导体基材;
基材上的外延层,所述外延层被用第二传导性类型的掺杂剂轻掺杂,其中,所述外延层包含在上表面具有较高浓度和在靠近基材处具有较低浓度的浓度梯度;
形成在外延层中的沟槽,所述沟槽包含具有从90度到70度的角度范围的侧壁,通过底部氧化区域和绝缘盖在沟槽内垂直绝缘的栅极,所述侧壁被用第一传导性类型的掺杂剂轻掺杂,使得在靠近所述侧壁的外延层中形成侧壁掺杂区域,并且所述沟槽的底部的所述第一传导性类型的掺杂剂的扩散宽度大于所述沟槽的顶部的所述第一传导性类型的掺杂剂的扩散宽度,从而减小在沟槽的底部在沟槽之间的所述第二传导性类型的掺杂区域同时形成基本笔直的PN结,其中在相邻的沟槽之间形成台面,所述侧壁掺杂区域的宽度被调节,使得当所述半导体器件关闭且电流被阻止时,邻近任何沟槽的台面能够部分或充分地耗尽,并且在此所述栅极通过栅极绝缘层与外延层隔离;
接触外延层的上表面和绝缘盖的上表面的源极层;和
接触基材的底部的漏极。
8.根据权利要求7所述的器件,其特征在于,所述第一传导性类型的掺杂剂是n-型掺杂剂以及所述第二传导性类型的掺杂剂是p-型掺杂剂。
9.根据权利要求7所述的器件,其特征在于,所述浓度梯度以均匀的或阶梯的方式从所述上表面到基材减小。
10.根据权利要求7所述的器件,其特征在于,所述沟槽侧壁的掺杂剂被以从大于0度到40度范围的角度注入。
11.一种包含半导体器件的电子设备,包括:
用第一传导性类型的掺杂剂重掺杂的半导体基材;
基材上的外延层,所述外延层被用第二传导性类型的掺杂剂轻掺杂,其中,所述外延层包含具有上表面处的较高浓度和靠近基材处的较低浓度的浓度梯度;
形成在外延层中的沟槽,所述沟槽包含具有从90度到70度的角度范围的侧壁,被通过底部氧化区域和绝缘盖在沟槽内垂直绝缘的栅极,所述侧壁被用第一传导性类型的掺杂剂轻掺杂,使得在靠近所述侧壁的外延层中形成侧壁掺杂区域,并且所述沟槽的底部的所述第一传导性类型的掺杂剂的扩散宽度大于所述沟槽的顶部的所述第一传导性类型的掺杂剂的扩散宽度,从而减小在沟槽的底部在沟槽之间的所述第二传导性类型的掺杂区域同时形成基本笔直的PN结,其中在相邻的沟槽之间形成台面,所述侧壁掺杂区域的宽度被调节,使得当所述半导体器件关闭且电流被阻止时,邻近任何沟槽的台面能够部分或充分地耗尽,并且在此栅极被通过栅极绝缘层与外延层隔离;
接触外延层的上表面和绝缘盖的上表面的源极层;和
接触基材的底部的漏极。
12.根据权利要求11所述的设备,其特征在于,所述第一传导性类型的掺杂剂是n-型掺杂剂以及所述第二传导性类型的掺杂剂是p-型掺杂剂。
13.根据权利要求11所述的设备,其特征在于,所述浓度梯度以均匀的或阶梯的方式从所述上表面到基材减小。
14.根据权利要求11所述的设备,其特征在于,所述沟槽侧壁的掺杂剂被以从大于0度到40度范围的角度注入。
15.根据权利要求11所述的设备,其特征在于,进一步包括位于基材和所述外延层之间的以第一传导性类型的掺杂剂掺杂的另一外延层。
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2010
- 2010-02-17 US US12/707,323 patent/US20110198689A1/en not_active Abandoned
-
2011
- 2011-02-17 CN CN201110041239.XA patent/CN102163622B/zh not_active Expired - Fee Related
- 2011-02-17 KR KR1020110014085A patent/KR20110095207A/ko active Application Filing
- 2011-02-17 TW TW100105299A patent/TWI442569B/zh active
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2012
- 2012-11-29 KR KR1020120136934A patent/KR101294917B1/ko active IP Right Grant
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Also Published As
Publication number | Publication date |
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US20110198689A1 (en) | 2011-08-18 |
CN102163622A (zh) | 2011-08-24 |
KR20110095207A (ko) | 2011-08-24 |
KR20120138726A (ko) | 2012-12-26 |
KR101294917B1 (ko) | 2013-08-08 |
TWI442569B (zh) | 2014-06-21 |
TW201208066A (en) | 2012-02-16 |
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