CN102157560B - 一种高压ldmos器件 - Google Patents
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Abstract
本发明涉及一种高压LDMOS器件,包括衬底、位于衬底之上的外延层,位于外延层之上靠漏区一侧且下表面与外延层的下表面重合的漂移区,位于LDMOS器件两端的漏区和源区,在衬底和外延层的交界面上跨过外延层的下表面具有交替排列的至少一对n型半导体区和p型半导体区,n型半导体区和p型半导体区的交接面与所述功率器件工作时的表面电压降方向平行,所述n型半导体区和p型半导体区紧贴排列相互形成PN结。本发明的有益效果是:本发明中的n型半导体区和p型半导体区也被合称为体内降低表面电场层,这种具有体内降低表面电场层的LDMOS器件有效的解决了现有的LDMOS器件提高反向耐压和降低正向导通电阻的矛盾。
Description
技术领域
本发明涉及电子技术领域内的半导体高压低阻器件,尤其涉及在体硅上制造的高压功率器件。
背景技术
随着半导体行业的迅猛发展,PIC(Power Integrated Circuit,功率集成电路)不断在多个领域中使用,如电机控制、平板显示驱动控制、电脑外设的驱动控制等等,PIC电路中所使用的功率器件中,LDMOS(Lateral Double Diffused MOSFET,横向双扩散金属氧化物半导体场效应管)高压器件具有工作电压高、工艺简单、易于同低压CMOS(ComplementaryMetal Oxide Semiconductor,互补金属氧化物半导体)电路在工艺上兼容等特点而受到广泛关注。但是对于用Si(硅)材料制成的半导体高压功率器件,LDMOS器件的正向导通电阻相比于VDMOS(Vertical Double Diffused MOSFET,垂直双扩散金属氧化物半导体场效应晶体管)的大,而较大的正向导通电阻导致了器件尺寸的增大,从而增加了制造成本。图1是N外延的常规LDMOS器件结构示意图,图中,LDMOS器件包括衬底1、外延层2、漂移区3、漏区4、阱区5、源区6、漏极7、源极8、栅极9,衬底1为p型,外延层2为n型。当LDMOS器件为n型时,阱区5为p型,漂移区3为n-型,漏区4、源区6为n+型,反之;当LDMOS器件为p型时,阱区5为n型,漂移区3为p-型,漏区4、源区6为p+型。图2是P外延的常规N沟道LDMOS器件结构示意图,图中,LDMOS器件包括衬底1、外延层2、漂移区3、漏区4、源区6、漏极7、源极8、栅极9,衬底1、外延层2为p型,漂移区3为n-型,漏区4、源区6为n+型,漏极7、源极8、栅极9为金属电极。图3是P外延的常规P沟道LDMOS器件结构示意图,图中,LDMOS器件包括衬底1、外延层2、漂移区3、漏区4、阱区5、源区6、漏极7、源极8、栅极9,衬底1、外延层2为p型,阱区5为n型,漂移区3为p-型,漏区4、源区6为p+型。LDMOS器件中用于承担耐压的漂移区3需要用低浓度掺杂,但另一方面,要降低LDMOS器件正向导通时的导通电阻,又要求作为电流通道的漂移区3具有高掺杂浓度,这就形成了击穿电压BV与导通电阻Ron之间的矛盾。以常见MOS(Metal-Oxide-Semiconductor,金属-氧化物-半导体)器件为例,其具体关系式如下:
其中,LD是漂移区长度,ND为漂移区浓度,μn和μp分别为电子和空穴的迁移率,q为电子电量。由此可见,MOS器件的导通电阻与漂移区长度成正比,与其浓度成反比。长度越短,浓度越高,则导通电阻越小,由于LDMOS器件是MOS器件中的一种,因此LDMOS器件具有MOS器件的通用特性。因此为了保证一定的耐压,LDMOS器件的漂移区3的长度不能做得太短;其浓度也不能做得太高,否则会在栅极9下阱区5的PN结附近发生击穿,使LDMOS器件的反向耐压降低。
发明内容
本发明的目的是为了解决现有的LDMOS器件提高反向耐压和降低正向导通电阻的矛盾,提供了一种高压LDMOS器件。
为了实现上述目的,本发明的技术方案是一种高压LDMOS器件,包括衬底、位于衬底之上的外延层,位于外延层之上靠漏区一侧且下表面与外延层的下表面重合的漂移区,位于LDMOS器件两端的漏区和源区,在衬底和外延层的交界面上跨过外延层的下表面具有交替排列的至少一对n型半导体区和p型半导体区,n型半导体区和p型半导体区的交接面与所述功率器件工作时的表面电压降方向平行,所述n型半导体区和p型半导体区紧贴排列相互形成PN结。
本发明的有益效果是:本发明中的n型半导体区和p型半导体区也被合称为体内降低表面电场(RESURF)层,这种具有体内降低表面电场层的LDMOS器件有效的解决了现有的LDMOS器件提高反向耐压和降低正向导通电阻的矛盾,从而在相同反向耐压的情况下可以有效降低正向导通电阻,或者在相同正向导通电阻的情况下可以有效提高反向耐压。
附图说明
图1是N外延的常规的LDMOS器件结构示意图。
图2是P外延的常规的N沟道LDMOS器件结构示意图。
图3是P外延的常规的P沟道LDMOS器件结构示意图。
图4是本发明实施例一的LDMOS器件结构示意图。
图5是本发明实施例二的LDMOS器件结构示意图。
图6是本发明实施例三的LDMOS器件结构示意图。
图7是本发明实施例四的LDMOS器件结构示意图。
图8是本发明实施例五的LDMOS器件结构示意图。
图9是本发明实施例六的LDMOS器件结构示意图。
图10是本发明实施例七的LDMOS器件结构示意图。
图11是本发明实施例八的LDMOS器件结构示意图。
附图标记说明:衬底1、外延层2、漂移区3、漏区4、阱区5、源区6、漏极7、源极8、栅极9、n型半导体区10、p型半导体区11、顶埋层12。
具体实施方式
下面结合附图和具体实施例对本发明做进一步的说明。
实施例一:如图4所示,LDMOS器件包括衬底1、外延层2、漂移区3、漏区4、源区6、漏极7、源极8、栅极9,本实施例中LDMOS器件为P外延的N沟道LDMOS器件,所以衬底1、外延层2为p型,漂移区3为n-型,漏区4、源区6为n+型,外延层2位于衬底1之上,漂移区3位于外延层2靠漏区4一侧且下表面跨过外延层2的下表面,漏区4和源区6位于LDMOS器件两端,在衬底1和外延层2的交界面上跨过外延层2的下表面具有交替排列的两对n型半导体区10和p型半导体区11,n型半导体区10和p型半导体区11的交界面与所述功率器件工作时的表面电压降方向平行,长度与漂移区3长度一致,n型半导体区10和p型半导体区11紧贴排列相互形成PN结。
本实施例中n型半导体区11和p型半导体区12可以根据需要任意设定对数、形状、宽度、长度和掺杂浓度,实施例中的对数、形状、宽度、长度不能被理解为对本发明的限定。
以本实施例为例说明本发明的工作原理:
首先,本实施例中的n型半导体区10和p型半导体区11也被合称为体内降低表面电场(RESURF)层。LDMOS器件正向导通时,与漂移区3掺杂特性相同的降低表面电场层的半导体区构成一个与漂移区3并联的等效电阻,因此可以有效降低LDMOS器件整体的导通电阻,从而达到降低导通损耗的目的。如公式:Ron=Rcontact+Rsource+Rchannel+Rdrain+RdriftRresurf/(Rdrift+Rresurf)所示,式中,Ron为导通电阻,Rcontact是接触电阻,Rsource是源电阻,Rchannel是沟道电阻,Rdrift=ρd·Ldrift是漂移区电阻,Rdrain是漏区电阻,Rresurf是降低表面电场层的电阻,ρd是外延层电阻率,Ldrift是漂移区长度。
LDMOS器件反向耐压时,降低表面电场层中掺杂特性相反的n型半导体区10和p型半导体区11形成的横向PN结在横向上相互耗尽,与漂移区3掺杂特性相反的半导体区与漂移区3形成的纵向PN结在纵向上与漂移区3相互耗尽。横向上,体内降低表面电场层平坦的电场会影响表面电场使之变得较为平坦,提高了LDMOS器件的表面耐压。同时纵向上,与漂移区3掺杂特性相反的半导体区与漂移区3形成PN结,同样会影响体内纵向电场使之变得平坦,从而提高了纵向击穿电压。在常规LDMOS器件中,体内纵向击穿电压BV=EC*tepi,体内纵向击穿电压BV由纵向临界电场EC(位于外延层2和衬底1之间)与外延层2厚度tepi决定。增加了降低表面电场层后,若要维持相同的纵向击穿电压,则外延层厚度tepi可以大大降低。在降低表面电场层实现时,外延层2的掺杂浓度Nepi与厚度tepi满足公式Nepi*tepi=ε*Ec/q*sqrt(Nsub/(Nepi+Nsub)),式中ε为介电常数,q为电子电量,Nsub为衬底1的掺杂浓度。当纵向临界电场EC确定时,Nepi*tepi可视为常数,所以当外延层2厚度tepi降低时,外延层2掺杂浓度Nepi就会提高。可见,本实施例提供的结构在引入降低表面电场层后,可以大幅度降低正向导通电阻,使器件的导通损耗减小,在相同正向导通电阻的情况下提高LDMOS器件的耐压效果;并且在保证耐压的同时可以减小外延层2厚度,增加漂移区浓度,降低漂移区的正向导通电阻。
实施例二:如图5所示,在实施例一的基础上,为了防止n型半导体区10和p型半导体区11形成的PN结影响漏区4的电场,n型半导体区10和p型半导体区11的长度可以缩短至漏区4向中心一侧与漂移区3的交界面处。
实施例三:如图6所示,在实施例一或实施例二的基础上,为了防止n型半导体区10和p型半导体区11对源区6造成影响,可以把n型半导体区10和p型半导体区11的长度缩短至不与漂移区3向源区6一侧与外延层2的交界面相连。
实施例四:如图7所示,在实施例一或实施例二或实施例三的基础上,为了调节LDMOS器件反向耐压时n型半导体区10和p型半导体区11与漂移区3的电荷平衡,使其尽量达到完全耗尽,在漂移区3的上表面添加顶埋层(top)12,所述顶埋层12的掺杂特性与漂移区3相反。
实施例五:如图8所示,LDMOS器件包括衬底1、外延层2、漂移区3、漏区4、阱区5、源区6、漏极7、源极8、栅极9,本实施例中LDMOS器件为N外延的N沟道LDMOS器件。衬底1、阱区5为p型,外延层2为n型,漂移区3为n-型,漏区4、源区6为n+型,外延层2位于衬底1之上,漂移区3位于外延层靠近漏区4一侧且漂移区3的下表面与衬底1和外延层2的交界面重合,漏区4和源区6位于LDMOS器件两端,在衬底1和外延层2的交界面上跨过外延层2的下表面具有交替排列的两对n型半导体区10和p型半导体区11,n型半导体区10和p型半导体区11的交界面与所述功率器件工作时的表面电压降方向平行,长度从源端下方一直延伸至漏端下方,n型半导体区10和p型半导体区11紧贴排列相互形成PN结。本实施例的工作原理与实施例一相同。
本实施例中n型半导体区11和p型半导体区12也可以根据需要任意设定对数、形状、宽度、长度和掺杂浓度,实施例中的对数、形状、宽度、长度不能被理解为对本发明的限定。
实施例六:如图9所示,在实施例五的基础上,为了防止n型半导体区10和p型半导体区11形成的PN结影响漏区4的电场,n型半导体区10和p型半导体区11的长度可以缩短至漏区4向中心一侧与漂移区3的交界面。
实施例七:如图10所示,为了防止n型半导体区10和p型半导体区11对源区6造成影响,可以把n型半导体区10和p型半导体区11的长度缩短至源区6向中心一侧与阱区5的交界面。
实施例八:如图11所示,在实施例五或实施例六或实施例七的基础上,为了调节LDMOS器件反向耐压时n型半导体区10和p型半导体区11与漂移区3的电荷平衡,使其尽量达到完全耗尽,在漂移区3的上表面添加顶埋层(top)12,所述顶埋层12的掺杂特性与漂移区3相反。
本领域的普通技术人员将会意识到,这里所述的实施例是为了帮助读者理解本发明的原理,应被理解为本发明的保护范围并不局限于这样的特别陈述和实施例。本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合,这些变形和组合仍然在本发明的保护范围内。
Claims (7)
1.一种高压LDMOS器件,包括衬底(1)、位于衬底(1)之上的外延层(2),位于外延层(2)之上靠漏区(4)一侧且下表面与外延层(2)的下表面重合的漂移区(3),位于LDMOS器件两端的漏区(4)和源区(6),其特征在于,在衬底(1)和外延层(2)的交界面上跨过外延层(2)的下表面具有交替排列的至少一对n型半导体区(10)和p型半导体区(11),n型半导体区(10)和p型半导体区(11)的交接面与所述功率器件工作时的表面电压降方向平行,所述n型半导体区(10)和p型半导体区(11)紧贴排列相互形成PN结。
2.根据权利要求1所述的一种高压LDMOS器件,其特征在于,所述高压LDMOS器件为P外延的N沟道LDMOS器件。
3.根据权利要求2所述的一种高压LDMOS器件,其特征在于,所述n型半导体区(10)和p型半导体区(11)的长度可以缩短至漏区(4)向中心一侧与漂移区(3)的交界面处。
4.根据权利要求2所述的一种高压LDMOS器件,其特征在于,在漂移区(3)的上表面添加顶埋层(12),所述顶埋层(12)的掺杂特性与漂移区(3)相反。
5.根据权利要求1所述的一种高压LDMOS器件,其特征在于,所述高压LDMOS器件为N外延的N沟道LDMOS器件。
6.根据权利要求5所述的一种高压LDMOS器件,其特征在于,所述n型半导体区(10)和p型半导体区(11)的长度可以缩短至漏区(4)向中心一侧与漂移区(3)的交界面处。
7.根据权利要求5所述的一种高压LDMOS器件,其特征在于,在漂移区(3)的上表面添加顶埋层(12),所述顶埋层(12)的掺杂特性与漂移区(3)相反。
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CN102468335A (zh) * | 2010-11-19 | 2012-05-23 | 无锡华润上华半导体有限公司 | Ldmos器件及其制造方法 |
CN103066109B (zh) * | 2011-10-18 | 2015-09-30 | 旺宏电子股份有限公司 | 半导体结构及其形成方法 |
CN103091533B (zh) * | 2011-11-03 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | 用ldmos器件实现的电流采样电路 |
CN102427077B (zh) * | 2011-12-02 | 2013-11-27 | 日银Imp微电子有限公司 | 一种用于桥式驱动电路中的高压隔离环结构 |
CN102709325A (zh) * | 2012-06-25 | 2012-10-03 | 电子科技大学 | 一种高压ldmos器件 |
CN102790092A (zh) * | 2012-08-24 | 2012-11-21 | 电子科技大学 | 一种横向高压dmos器件 |
CN105762192B (zh) * | 2014-12-19 | 2019-01-29 | 北大方正集团有限公司 | 横向高压半导体器件 |
US9553142B2 (en) * | 2015-06-12 | 2017-01-24 | Macronix International Co., Ltd. | Semiconductor device having buried layer |
CN106876464A (zh) * | 2016-12-29 | 2017-06-20 | 西安电子科技大学 | 一种横向双扩散金属氧化物半导体场效应管 |
CN114220847B (zh) * | 2022-02-22 | 2022-05-17 | 北京芯可鉴科技有限公司 | 一种ldmosfet、制备方法及芯片和电路 |
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