CN102157556B - Oxidizing-dephlegmation-based silicon-based wrap gate transistor with buried-channel structure and preparation method thereof - Google Patents
Oxidizing-dephlegmation-based silicon-based wrap gate transistor with buried-channel structure and preparation method thereof Download PDFInfo
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Abstract
The invention provides a silicon-based wrap gate transistor with a buried-channel structure, and belongs to the field of electronic semiconductor devices. The transistor comprises a channel region, a gate medium, a gate region, a source region, a drain region and a source/drain terminal epitaxial region, wherein the channel region has a silicon nanowire structure with three layers, a cylindrical channel region lower layer is arranged inside the channel region, and the channel region and the channel region upper layer are wrapped outside the channel region lower layer respectively; impurities with opposite types are mixed into the channel region upper layer and the channel region lower layer; a layer of gate medium region is covered outside the channel region upper layer; and the gate region is positioned on the outer layer of the gate medium. In a preparation method, the silicon-based wrap gate transistor with the buried-channel structure which is suitable to be applied to high-speed circuits is prepared on the basis of an oxidizing dephlegmation technology, so that the phenomena of descending in mobility and serious random telegraph noise which are caused by the polycrystal orientation of wrap gate devices are avoided.
Description
Technical field
The present invention is about wrap gate field-effect transistor in the semiconductor microelectronics devices field, is specifically related to a kind ofly be fit to be applied in the structure silicon-based gate transistor that encloses of buried channel in the high-speed low-power-consumption circuit based on oxidation fractional condensation technology.
Background technology
Along with very lagre scale integrated circuit (VLSIC) constantly reduces cost, increases integrated level, improves performance, the cmos device characteristic size is constantly dwindled, the leakage current of device constantly increases, and short channel effect (SCE:Short-Channel-Effect) seems more and more serious.In order to overcome the subject matter that hinders device dimensions shrink, one of them effective way is exactly to improve the control ability of grid to raceway groove with multi-gate structure, improves device property, makes device can adapt to the work of small size field better.The multiple-grid device architecture is dual-gate MOS (DGMOS:Double-Gate-MOSFET), double grid FinFET (Fin-Field-Effect-Transistor), three grid Ω gate devices and enclose gate device for example.Wherein enclose the grid structure and have the strongest grid-control ability, because whole channel region will be surrounded by grid, therefore this grid structure of enclosing has eliminated the turning effect as the cylindrical structure of the silicon fiml of channel region, helps the raising of mobility and the reliability of raising device.Simultaneously, silica-based technology and the traditional silicon base CMOS process compatible that encloses gate device makes and to enclose the gate device low cost of manufacture, helps integratedly on a large scale, is applicable to various pursuit high performance circuit chips.
Yet; A silica-based unavoidable problem of enclosing gate device be the raceway groove polycrystalline to because polycrystalline has also increased the weight of carrier scattering (scattering) and thump telegraph repeater phenomenon (RTN:Random-Telegraph-Noise) at random when the dangling bonds that produce have increased trap (traps) density.When charge carrier flow through surface channel, charge carrier can be attracted or repels by trapped charge, changed to transport direction, had reduced the mobility of charge carrier rate, thereby had reduced the transmission speed of channel direction.Simultaneously, catch and release action because trap exists charge carrier, polycrystalline is caught the charge carrier in the conducting electric current or is discharged to the trap that brings, and the part trap can have considerable influence to channel current in this process, form thump telegraph repeater phenomenon at random.Making is enclosed in the technology of gate device and is introduced certain surface roughness (surface roughness) inevitably, and this also can cause silica-based mobility of enclosing gate device to reduce.
Therefore, how further optimizing the silica-based gate device that encloses, improve and enclose the gate device carrier mobility, improve thump telegraph repeater phenomenon at random, is one of difficult point of enclosing the gate device area research.
Summary of the invention
The present invention is directed to prior art, provide a kind of and be fit to be applied in the structure silicon-based gate transistor that encloses of buried channel in the high speed circuit based on oxidation fractional condensation technology.
Technical scheme of the present invention is:
The structure silicon-based gate transistor (as shown in Figure 1) that encloses of a kind of buried channel comprises channel region, channel region lower floor, channel region upper strata, gate medium, grid region, source region, drain region, drain terminal epitaxial region, source.Said channel region is the core (as shown in Figure 2) of field-effect transistor, is silicon nanowire structure, comprises three layers; Inside is columniform channel region lower floor; Be wrapped in its outer two-layer be respectively channel region and channel region upper strata, channel region upper strata and channel region lower floor are doped with the impurity of type opposite, cover one deck gate medium district outside the channel region upper strata; The grid region is positioned at the skin of gate medium, and grid region and gate medium surround silicon nanowires fully.The length value in channel region, channel region lower floor, channel region upper strata, gate medium, grid region is consistent, and scope is 10 nanometers～10 micron.Channel region annulus thickness span is 10 nanometers～1 micron, and undoping or being equivalent to undopes.Channel region upper strata annulus thickness span is 10 nanometers～1 micron, and the doping content scope is 10
16～10
18Cm
-3The diameter span of channel region lower floor column structure is 10 nanometers～3 micron, and the doping content scope is 10
16～10
18Cm
-3The channel region upper strata is opposite with channel region lower floor doping type.The doping content of said channel region, channel region upper strata, channel region lower floor is to utilize the oxidation fractional condensation to form.
Said grid medium thickness span is 1～10 nanometer.The grid region thickness range is 10 nanometers～5 micron.
Said source region and drain region upper and lower surfaces flush, and connect drain terminal epitaxial region, source respectively.Adopt high-concentration dopant, the doping content span is 10
20～10
21Cm
-3
Drain terminal epitaxial region, said source is positioned between source region or drain region and the raceway groove (channel region, channel region upper strata, channel region lower floor), it is characterized in that its doping content is identical with source region and drain region, to reach very little resistance.Its length span is 20 nanometers～100 nanometers.The reason that keeps certain-length is to reduce the parasitic capacitance in drain region and grid region.Its doping content span is 10
20～10
21Cm
-3
The structure silicon-based preparation method who encloses gate transistor of buried channel of the present invention is based on oxidation fractional condensation technology, specifically may further comprise the steps:
(1) choose the body silicon chip, utilize hard mask definition source region, the drain region, high concentration n type mixes;
(2) remove hard mask in (1), utilize the hard mask of another sheet that raceway groove is carried out two kinds of dissimilar doping impurity;
(3) remove hard mask in (2), electron beam definition hachure carries out the silicon strip that oxidation forms suspension, and impurity carries out the oxidation fractional condensation in the oxidizing process, forms the three-decker of channel region, channel region upper strata, channel region lower floor;
(4) wet etching falls the silicon dioxide of formation, carries out thermal oxidation and forms the layer of silicon dioxide gate medium;
(5) make the grid region;
(6) get into the conventional cmos later process at last.
Compared with prior art, effect of the present invention is:
Based on oxidation fractional condensation technology be fit to be applied in the structure silicon-based gate transistor that encloses of buried channel in the high speed circuit, avoided enclosing the gate device polycrystalline and descended the serious phenomenon of thump telegraph repeater at random to the mobility of bringing.The three-decker raceway groove of channel region upper strata, channel region, channel region lower floor makes the carrier flow zone be restricted to channel region; Carrier flow path principle is enclosed the gate device surface like this; Reduced polycrystalline to the influence of the trap of introducing to charge carrier; Thereby increased the transmission speed of charge carrier, increased the mobility of charge carrier rate at channel direction.Also can reduce simultaneously and enclose of the influence of gate device rough surface charge carrier.Make mobility further improve, be applicable to high performance types of applications.
Description of drawings
Fig. 1 is the structure silicon-based top cross-sectional view of introducing among the present invention of enclosing gate transistor of buried channel based on oxidation fractional condensation technology.Among the figure:
1-channel region lower floor, 2-channel region, 3-channel region upper strata, 4-gate medium, 5-grid region, drain terminal epitaxial region, 6-source, 7-source region, 8-drain region.
Fig. 2 encloses gate device channel part structural profile sketch map, among the figure:
1-channel region lower floor, 2-channel region, 3-channel region upper strata, 4-gate medium, 5-grid region.
Fig. 3 is the impurity segregation sketch map.
Among Fig. 3:
Ordinate is a doping content.Abscissa is the profile thickness direction, and arrow points is enclosed grid structure centre A.14, the silicon dioxide that 17-is obtained by oxidizing process, 15, the equivalence that the 18-oxidizing process produces is undoped channel region upper strata and channel region; 16,19-channel region lower floor, in the 20-oxidizing process, segregation coefficient is less than 1 the distribution of impurity in silicon dioxide; In the 21-oxidizing process, segregation coefficient is less than 1 the distribution of impurity in silicon, in the 22-oxidizing process; Segregation coefficient is greater than 1 the distribution of impurity in silicon dioxide, and in the 22-oxidizing process, segregation coefficient is greater than 1 the distribution of impurity in silicon.20,21 is impurity of the same race, and 22,23 is impurity .20 of the same race, and 21 dopant type is opposite with 22,23 dopant type.
Fig. 4 is the total doping content sketch map of equivalence after the impurity segregation.
Among Fig. 4:
24-channel region upper strata, the 25-channel region, 26-channel region lower floor, 27 channel region upper strata Impurity Distribution, 28-channel region lower floor magazine distributes.Wherein 27,28 dopant type are different.Have the dissimilar impurity of equivalent in 25 channel regions simultaneously, equivalence is a non-impurity-doped.
Fig. 5-Fig. 8 the present invention is based on the structure silicon-based flow chart that encloses gate transistor of buried channel of oxidation fractional condensation technology for preparation;
Among Fig. 5:
The 29-source region, 30-drain region, 31-channel mask version 1,32-silicon substrate.
Among Fig. 6:
33-channel mask version 2, the zone that two kinds of dissimilar doping impurity of 34-are crossed.
Among Fig. 7:
35-comprises the raceway groove of channel region upper strata, channel region, channel region lower floor.The 36-raceway groove is unsettled.
Among Fig. 8:
The 37-grid region, the 38-gate dielectric layer.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:
Fig. 1 structure is the structure silicon-based top cross-sectional view of introducing among the present invention of enclosing the gate transistor core of buried channel based on oxidation fractional condensation technology.Its structure and general conventional silica-basedly enclose the gate transistor difference and be:
Raceway groove is divided into three-decker: channel region, channel region upper strata, channel region lower floor.These three layers have formed a buried channel structure, make the carrier flow path away from silicon-silicon dioxide interface.Thereby reduced of the influence of silicon-silicon dioxide trap at the interface to charge carrier.Avoided the influence of surface roughness simultaneously to mobility.
Its structure and general conventional planar structure buried channel device difference are:
Enclose the grid structure, have very strong grid-control ability, because whole channel region will be surrounded by grid, therefore this grid structure of enclosing has eliminated the turning effect as the cylindrical structure of the silicon fiml of channel region, helps the raising of mobility and the reliability of raising device.Obtained high-performance when reducing various short-channel effect.
Simultaneously, the difference of buried channel technology is:
The present invention oxidation attenuate silicon form enclose gate device before, it is highly doped that silicon is carried out two kinds of dissimilar impurity.When forming cylindrical structural, utilize oxidation to divide coagulation phenomena to form three layers of doped structure naturally: the channel region upper strata at oxidation attenuate silicon strip: in high magazine concentration; Channel region: equivalence is for undoping; Channel region lower floor: middle high-dopant concentration.Wherein the dopant type of channel region upper strata and channel region lower floor is opposite.Thereby form buried channel, simple and reliable process naturally.
Above-mentioned various difference helps improving the structure silicon-based performance that transports of enclosing gate transistor of buried channel based on oxidation fractional condensation technology.
The present invention can realize that n type and p type are based on the technological structure silicon-based gate transistor that encloses of buried channel of oxidation fractional condensation.
Be the main flow process of making of example explanation with the n type based on the structure silicon-based gate transistor that encloses of the buried channel of oxidation fractional condensation technology below:
(1) choose the body silicon chip, utilize hard mask definition source region, the drain region, high concentration n type mixes.The doping content span is 10
20～10
21Cm
-3Source region, the drain region degree of depth are 100 nanometers～1 micron.Shown in Fig. 5 side cut away view.
(2) remove hard mask in (1), utilize the hard mask of another sheet that raceway groove is carried out two kinds of dissimilar doping impurity,, for formation channel region upper strata, channel region, channel region lower floor prepare.For buried channel structure silicon-based the enclose gate transistor of n type based on oxidation fractional condensation technology, two kinds of impurity are selected boron and phosphorus respectively.Wherein the doping content scope of boron is 10
17～10
18Cm
-3The doping content scope of phosphorus is 10
16～10
17Cm
-3, guaranteeing that channel region lower floor boron is main impurity, semiconductor type is the p type.Shown in Fig. 6 side cut away view.
(3) remove hard mask in (2), electron beam definition hachure carries out the silicon strip that oxidation forms suspension, and impurity carries out the oxidation fractional condensation in the oxidizing process, forms the three-decker of channel region, channel region upper strata, channel region lower floor.As shown in Figure 7.
(4) silicon dioxide that fall to form of wet etching, carry out thermal oxidation and be channel region form one deck around the silicon dioxide gate medium, thickness span 1～10 nanometer.
(5) make the grid region, the grid region thickness range is 10 nanometers～5 micron.As shown in Figure 8.
The technological process of back and conventional silicon nanowires MOS transistor are just the same.Successively carry out: planarization, deposit separator, lithography fair lead, depositing metal, photoetching lead-in wire, passivation or the like.
More than described through detailed example and provided by the present inventionly to be fit to be applied in the structure silicon-based gate transistor that encloses of buried channel in the high speed circuit based on oxidation fractional condensation technology; Above-described application scenarios and embodiment; Be not to be used to limit the present invention, any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can do various changes and retouching, so protection scope of the present invention is looked the claim scope definition.
Claims (9)
1. the structure silicon-based gate transistor that encloses of buried channel comprises channel region, gate medium, grid region, source region, drain region and drain terminal epitaxial region, source, it is characterized in that; Said channel region is a silicon nanowire structure, comprises three layers, and inside is columniform channel region lower floor; Be wrapped in its outer two-layer be respectively channel region and channel region upper strata; Channel region upper strata and channel region lower floor are doped with the impurity of type opposite, cover one deck gate medium district outside the channel region upper strata, and the grid region is positioned at the skin of gate medium.
2. the structure silicon-based gate transistor that encloses of buried channel as claimed in claim 1 is characterized in that, the length span in channel region, gate medium and grid region is 10 nanometers～10 micron.
3. the structure silicon-based gate transistor that encloses of buried channel as claimed in claim 1 is characterized in that channel region is circular, and its thickness span is 10 nanometers～1 micron, and undoping or being equivalent to undopes.
4. the structure silicon-based gate transistor that encloses of buried channel as claimed in claim 1 is characterized in that the channel region upper strata is circular, and its thickness span is 10 nanometers～1 micron, and the doping content scope is 10
16～10
18Cm
-3
5. the structure silicon-based gate transistor that encloses of buried channel as claimed in claim 1 is characterized in that channel region lower floor is a column structure, and its diameter span is 10 nanometers～3 micron, and the doping content scope is 10
16～10
18Cm
-3
6. the structure silicon-based gate transistor that encloses of buried channel as claimed in claim 1 is characterized in that said grid medium thickness span is 1～10 nanometer, and the grid region thickness range is 10 nanometers～5 micron.
7. the structure silicon-based gate transistor that encloses of buried channel as claimed in claim 1 is characterized in that, high-concentration dopant is adopted in said source region and drain region, and the doping content span is 10
20～10
21Cm
-3, and source region and drain region upper and lower surfaces flush, and connects drain terminal epitaxial region, source respectively.
8. the structure silicon-based gate transistor that encloses of buried channel as claimed in claim 1; It is characterized in that drain terminal epitaxial region, said source is between source region or drain region and raceway groove, its doping content is identical with source region and drain region; Its length span is 20 nanometers～100 nanometers, and its doping content span is 10
20～10
21Cm
-3
9. the structure silicon-based preparation method who encloses gate transistor of buried channel as claimed in claim 1 may further comprise the steps:
(1) choose the body silicon chip, utilize hard mask definition source region, drain region, high concentration n type mixes, and the doping content span is 10
20～10
21Cm
-3
(2) remove hard mask in (1), utilize the hard mask of another sheet that raceway groove is carried out two kinds of dissimilar doping impurity;
(3) remove hard mask in (2), electron beam definition hachure carries out the silicon strip that oxidation forms suspension, and impurity carries out the oxidation fractional condensation in the oxidizing process, forms the three-decker of channel region, channel region upper strata, channel region lower floor;
(4) wet etching falls the silicon dioxide of formation, carries out thermal oxidation and forms the layer of silicon dioxide gate medium;
(5) make the grid region;
(6) get into the conventional cmos later process at last.
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| CN102569262B (en) * | 2012-01-10 | 2014-08-13 | 北京大学 | Test structure and test method of nano-wire enclosure device heat radiation properties |
| CN102569261B (en) * | 2012-01-10 | 2014-02-19 | 北京大学 | Structure and method for testing heat radiating characteristic of nanoscale device |
| CN103915484B (en) * | 2012-12-28 | 2018-08-07 | 瑞萨电子株式会社 | With the field-effect transistor and production method for being modified to the raceway groove core for back-gate bias |
| CN103872140B (en) * | 2014-03-06 | 2017-09-29 | 北京大学 | A kind of planar rings gate transistor based on nano wire and preparation method thereof |
| CN104282575B (en) * | 2014-09-26 | 2017-06-06 | 北京大学 | A kind of method for preparing nanoscale field-effect transistor |
| CN107451330B (en) * | 2017-06-28 | 2020-07-28 | 北京大学 | Accelerated transient simulation method for random telegraph noise in circuit |
| US11088246B2 (en) * | 2019-07-18 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor |
| CN112885724A (en) * | 2021-01-15 | 2021-06-01 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1688027A (en) * | 2005-05-13 | 2005-10-26 | 湖北工业大学 | Nano-line silicone carbide metal oxide semiconductor field effect transistor |
| CN101060135A (en) * | 2007-06-05 | 2007-10-24 | 北京大学 | A double silicon nanowire wrap gate field-effect transistor and its manufacture method |
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| CN1688027A (en) * | 2005-05-13 | 2005-10-26 | 湖北工业大学 | Nano-line silicone carbide metal oxide semiconductor field effect transistor |
| CN101060135A (en) * | 2007-06-05 | 2007-10-24 | 北京大学 | A double silicon nanowire wrap gate field-effect transistor and its manufacture method |
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