CN101060135A - A double silicon nanowire wrap gate field-effect transistor and its manufacture method - Google Patents
A double silicon nanowire wrap gate field-effect transistor and its manufacture method Download PDFInfo
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Abstract
The provided double-silicon nano line enclose-grid FET belonged to MOSFET technique in ULSI comprises: a silicon substrate, double silicon lines as the channels, a grid anode and multicrystal silicon grid enclosing the nano lines to form the enclose-grid structure, both source and drain connecting with the substrate, and a thick SiO2 layer between the right bottom of channel and substrate. This invention is compatible to common CMOS technique, reduces cost and power consumption, and has wide application.
Description
Technical field
The invention belongs to mos field effect transistor (the MetalOxide Silicon Field Effect Transistor-MOSFET) technical field in the very lagre scale integrated circuit (VLSIC) (ULSI), be specifically related to a kind of double silicon nanowire wrap gate field-effect transistor and preparation method thereof.
Background technology
Along with the extensive use and the high speed development of very lagre scale integrated circuit (VLSIC), the MOSFET technology entered the nanometer field (＜100nm).But long scaled after inferior 50nm when the grid of the MOSFET (can abbreviate device as) of the single grid of routine, grid-control ability, short channel effect worsen, leakage current is big and problem such as ON state drive current deficiency will show more and more seriously.For the grid-control ability that improves MOSFET as much as possible, reduce leakage current, improve the ON state drive current, increase on-off ratio, suppress short channel effect, people have proposed a lot of double grids or multiple-grid device, as FinFET double-gated devices (along the cross-section structure of raceway groove vertical direction shown in Fig. 1 (a)), tri-gate devices (shown in Fig. 1 (b)), Ω gate device (shown in Fig. 1 (c)) with enclose grid (Gate-all-around, be called for short GAA, shown in Fig. 1 (d)) device etc.Under similarity condition, the grid-control ability of enclosing gate device is the strongest, and characteristic also is optimum.Along with the grid of device are long scaled, in order to keep good electrology characteristic, strengthen the grid-control ability, reduce leakage current, the size of the raceway groove cross section of double grid or multiple-grid device will be reduced to about 10nm, and these devices just become silicon nanowires (Si nanowire) device.Silicon nanowires multiple-grid or enclose gate device,, short channel effect strong with its grid-control ability suppresses obviously, device property is excellent, causes that people greatly pay close attention to and research enthusiasm.
But the silicon nanowires multiple-grid of having reported now or enclose gate device perhaps is subjected to the limitation of structure itself, perhaps can bring difficulty on the prepared etc., makes silicon nanowires multiple-grid or the advantage of enclosing gate device often can not demonstrate fully.
For example, document 1 (F.L.Yang, D.H.Lee, H.Y. Chen, et al., " 5nm-gate nanowire FinFET ", in Symp.VLSl Tech.Dig, 2004, pp:196-197) the nano wire Ω gate device shown in (shown in Fig. 2 (a)-(d)), there are the following problems: (1) prepares on the SOI substrate, and cost is very high; (2) because the preparation silicon nanowires needs very thin top silicon surface, the raceway groove on the SOI substrate is identical with the silicon film thickness that leak in the source, and shown in Fig. 2 (c), the parasitic series resistance that leak in the source that makes increases, and the ON state drive current is limited; (3) simultaneously, the cross-section structure along the raceway groove vertical direction of this silicon nanowires device is Ω grid structures, as Fig. 2 (b) with (d), is not to enclose the grid structure, and the grid-control ability awaits further to improve.
At the problem in the document 1, document 2 (S.D.Suk, S.Y. Lee, et al., " High performance 5nm radiusTwin Silicon Nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer; characteristics, andreliability ", in IEDM Tech.Dig., 2005, pp:717-720) proposed silicon nanowire wrap gate field-effect transistor shown in Fig. 3 (a)-(c), it has reduced the substrate cost based on the body silicon substrate; The source all links to each other with the body silicon substrate with leaking, and can adopt darker source-and-drain junction, reduces the parasitic series resistance that leak in the source, increases the ON state drive current; As Fig. 3 (b) with (c), the raceway groove on the body silicon substrate is that identical cross-section structure is circular double silicon nanowire, and is centered on by grid oxygen and polysilicon gate, forms the double silicon nanowire wrap gate device; Can significantly improve the grid-control ability, suppress short channel effect, and improve nearly one times ON state drive current.
But, also there is a very serious problem in the device of this structure: as Fig. 3 (b) with (c), and the body surface of silicon under double silicon nanowire, there is a phost line, forms by the grid oxygen of parasitism, the raceway groove of parasitism and shared source, leakage and polysilicon gate.Promptly in other words, the device of this structure shown in the document 2, two field-effect transistors are arranged simultaneously, and one is double silicon nanowire wrap gate device field-effect transistor (can be described as this expropriation and management), the phost line that is the body surface of silicon (need avoid as far as possible or eliminate) that design needs.Therefore, the device of this structure shown in the document 2, its shortcoming is: (1) phost line makes that the leakage current of entire device increases, on-off ratio reduces, and makes device power consumption increase, and is unsuitable for low-power logic (Low-power Logic) and uses; (2) gate capacitance of phost line also makes total gate capacitance increase, and makes the AC characteristic of device worsen, and has also reduced devices switch speed, is unsuitable for high speed logic (High-speed Logic) and uses; (3) simultaneously, in prepared, the SiGe of document 2 corrosion sacrifice layer and all be epitaxially grown as the silicon raceway groove of nano wire, the technology cost is still very high.
Therefore, how further to optimize the silicon nanowire wrap gate device device architecture and its preparation process, raising device performance, demonstrate fully the advantage of silicon nanowire wrap gate device of making, the difficult point and the focus of MOSFET area research in the world now just.
Summary of the invention
The problem that exists at above-mentioned silicon nanowire wrap gate device for further optimised devices DC characteristic and AC characteristic, raising devices switch speed, the present invention proposes a kind of double silicon nanowire wrap gate field-effect transistor.
A kind of double silicon nanowire wrap gate field-effect transistor, based on the body silicon substrate, raceway groove is that identical cross-section structure is circular double silicon nanowire, double silicon nanowire is centered on by grid oxygen and polysilicon gate, the grid structure is enclosed in formation, the source all links to each other with the body silicon substrate with leaking, under the raceway groove and the silicon dioxide insulating layer of a bed thickness, the structure of formation raceway groove on insulating barrier arranged between the body silicon substrate.
Diameter≤the 10nm of described double silicon nanowire.
The junction depth of described source and leakage is 30～50nm greater than the diameter of double silicon nanowire.
Under the described raceway groove and the silicon dioxide insulating layer between the body silicon substrate, its thickness is 200～300nm.
Another object of the present invention provides a kind of above-mentioned double silicon nanowire wrap gate preparation of devices method.This preparation method shown in Fig. 6 (a)-(n), comprises the steps:
1) on the body silicon substrate, deposit silicon dioxide and silicon nitride, the photoetching of active area version, etch silicon nitride and silicon dioxide form double-deck hard mask;
2) silicon of etching place, the size autoregistration of etching has defined the height H of the cross-section structure of double silicon nanowire; Deposit silicon dioxide, etching silicon dioxide forms side wall, with the protection raceway groove;
3) silicon of etching place once more forms shallow slot; Isotropic etching silicon makes that the silicon under the raceway groove is carved sky;
4) remove the silicon dioxide side wall, the wet etching silicon nitride; The lateral encroaching size autoregistration of silicon nitride has defined the width W of the cross-section structure of double silicon nanowire; For the double silicon nanowire of circle, height H and width W equate;
5) deposit silicon dioxide, planarization forms shallow-trench isolation; Form the structure of raceway groove on insulating barrier simultaneously, and the source links to each other with the body silicon substrate still with leakage;
6) deposit silicon nitride layer, the photoetching of grid version; Grid version and above-mentioned steps 4) in the covering of position of silicon nitride lateral encroaching, the position of autoregistration definition double silicon nanowire; The two-layer silicon nitride of etching;
7) etching silicon dioxide, etch silicon again, autoregistration is formed on the double silicon nanowire on the insulating barrier;
8) wet etching silicon dioxide makes double silicon nanowire unsettled; Adopt and optimize technology, make double silicon nanowire become circle, attenuate, dry-oxygen oxidation forms grid oxygen;
9) the deposit polysilicon mixes and activation as grid material, and planarization forms polysilicon gate, and grid oxygen and polysilicon gate all center on double silicon nanowire, form to enclose the grid structure;
10) remove silicon nitride, mixing forms n+ source and leakage.
In the described step 1), the width of the channel region of active area version is 50～80nm.
Described step 2) etching size of the silicon of place equates with the lateral encroaching size of silicon nitride in the described step 4 in, all is 15～20nm.
In the described step 3), the etching size of the silicon of place is 250～350nm, is the degree of depth of shallow slot; Isotropic etching silicon is 30～50nm, greater than a half width of the channel region of active area version as claimed in claim 6.
In the described step 5), the thickness of deposit silicon dioxide is 350～500nm, greater than the degree of depth of shallow slot as claimed in claim 8.
Some key structure parameters of the double silicon nanowire wrap gate device of the BOI structure of the present invention that obtains at last are as thickness, the diameter D of double silicon nanowire, the long L of grid of the silicon dioxide insulating layer of BOI structure
G, gate oxide thickness, raceway groove and the source doping content and the distribution of leaking, can make adjustment to technological parameter according to the needs of design.Preparation method of the present invention, adopt the technology of conventional cmos preparation, as oxidation, deposit, etching and corrosion etc., by the integrated (ProcessIntegration of new technology, the combination of established technology), the double silicon nanowire wrap gate device of can autoregistration on the body silicon substrate realizing BOI structure (body is on insulating barrier).This preparation method and existing conventional CMOS technology are compatible fully, do not need the SOI substrate, also need expensive technologies such as extension, when realizing the device property of optimizing, also can reduce substrate cost and prepared cost.
Double silicon nanowire wrap gate field-effect transistor of the present invention, adopt the advantage of this BOI structure to be: (1) can eliminate the phost line of the body surface of silicon under raceway groove, and the leakage path of blocking-up phost line reduces leakage current, improve the on-off ratio of device, reduce device power consumption; Reduce parasitic gate capacitance when (2) eliminating phost line, can reduce total gate capacitance, optimized the AC characteristic of double silicon nanowire wrap gate device, improved devices switch speed.Therefore, double silicon nanowire wrap gate field-effect transistor of the present invention all has a clear superiority in low-power consumption, high speed logic circuit application.
Compare document 2, technique effect of the present invention is (as Fig. 5 (a) with (b)): (1) can eliminate the phost line on the substrate, leakage current (I
Off) reduce by 25 times, ON state drive current (I
On) approximately equal, i.e. on-off ratio (I
On/ I
Off) can improve a multiple order of magnitude; (2) gate capacitance (C
G) can reduce 36%; (3) devices switch speed is (with I
On/ C
GV
DdWeigh V
DdBe operating voltage) can improve 38%; (4) can be on the body silicon substrate, the double silicon nanowire wrap gate device of autoregistration organizator on insulating barrier, the preparation method is simple, and is compatible fully with existing conventional CMOS technology.
Therefore, the body proposed by the invention double silicon nanowire wrap gate device of (BOI structure) on insulating barrier, on DC characteristic, AC characteristic and devices switch speed, all demonstrate clear superiority, remarkable advantages and wide application prospect are all arranged in low-power consumption and high speed logic circuit application.
Description of drawings
Fig. 1 is that conventional several double grids and the cross-sectional view (along the vertical direction of raceway groove) of multiple-grid device: Fig. 1 (a) is the FinFET double-gated devices, and Fig. 1 (b) is a tri-gate devices, and Fig. 1 (c) is the Ω gate device, and Fig. 1 (d) is for enclosing gate device.
Among Fig. 1 (a)-(d), identical label is represented identical parts:
The silicon dioxide buried regions (Buried-Oxide) of the back side silicon 102-SOI silicon chip substrate of 101-SOI silicon chip substrate
The polysilicon gate of 103-FinFET double-gated devices (Poly-Si Gate)
The hard mask of the silicon dioxide of 104-FinFET double-gated devices
The grid oxygen of the Fin of 105-FinFET double-gated devices (fin type) raceway groove 106-FinFET double-gated devices
The raceway groove of the grid oxygen 109-tri-gate devices of the polysilicon gate 108-tri-gate devices of 107-tri-gate devices
The raceway groove of the grid oxygen 112-Ω gate device of the polysilicon gate 111-Ω gate device of 110-Ω gate device
The grid oxygen 115-that the polysilicon gate 114-that 113-encloses gate device encloses gate device encloses the raceway groove of gate device
Fig. 2 is the domain and the structure chart of the silicon nanowires Ω gate device of document 1: Fig. 2 (a) is the domain schematic diagram of this device, and M1 is the active area version, and M2 is the grid version; Fig. 2 (b) is the cross-sectional view of the vertical direction along raceway groove (A1A2 direction) of this device; Fig. 2 (c) is the cross-sectional view along channel direction (B1B2 direction) of this device; Fig. 2 (d) is the stereoscan photograph of the correspondence of Fig. 2 (b).
Among Fig. 2 (b)-(d), identical label is represented identical parts:
The silicon dioxide buried regions of the back side silicon 202-SOI silicon chip substrate of 201-SOI silicon chip substrate
The polysilicon gate (Poly-Si Gate) of 203-silicon nanowires Ω gate device
The raceway groove of the grid oxygen 205-silicon nanowires Ω gate device of 204-silicon nanowires Ω gate device
The leakage of the source 207-silicon nanowires Ω gate device of 206-silicon nanowires Ω gate device
Fig. 3 is that the domain and the structural representation of the double silicon nanowire wrap gate device of document 2: Fig. 3 (a) is the domain schematic diagram of this device, and M1 is the active area version, and M2 is the grid version, and dark part is a double silicon nanowire; Fig. 3 (b) is the cross-sectional view of the vertical direction along raceway groove (A1A2 direction) of this device, can see that raceway groove is a double silicon nanowire, has phost line under the while double silicon nanowire; Fig. 3 (c) is the cross-sectional view along channel direction (B1B2 direction) of this device.
Fig. 3 (b) and (c) in, identical label is represented identical parts:
The silicon dioxide of the place that 301-body silicon substrate (p-doping) 302-STI isolates
The grid oxygen of 303-polysilicon gate (Poly-Si Gate) 304-double silicon nanowire wrap gate device
305-double silicon nanowire (raceway groove)
The grid oxygen of the phost line of the body surface of silicon under the 306-double silicon nanowire (raceway groove)
The leakage of the source 309-double silicon nanowire wrap gate device of the raceway groove 308-double silicon nanowire wrap gate device of 307-phost line
Fig. 4 is that the domain and the structural representation of body provided by the present invention double silicon nanowire wrap gate device of (BOI structure) on insulating barrier: Fig. 4 (a) is the domain schematic diagram of this device, and M1 is the active area version, and M2 is the grid version, and dark part is a double silicon nanowire; Fig. 4 (b) is the cross-sectional view of the vertical direction along raceway groove (A1A2 direction) of this device, can see that raceway groove is a double silicon nanowire, simultaneously raceway groove under and the silicon dioxide insulating layer of a bed thickness is arranged between the body silicon substrate, can eliminate the phost line of body surface of silicon; Fig. 4 (c) is the cross-sectional view along channel direction (B1B2 direction) of this device, can see that the position of raceway groove is the BOI structure, and the source links to each other with the body silicon substrate still with leakage.
Fig. 4 (b) and (c) in, identical label is represented identical parts:
The silicon dioxide of the place that 401-body silicon substrate (p-doping) 402-STI isolates
403-polysilicon gate (Poly-Si Gate) 404-grid oxygen
405-double silicon nanowire (raceway groove)
Under the 406-double silicon nanowire (raceway groove) and the thick silicon dioxide insulating layer between the body silicon substrate
407-source 408-leaks
Fig. 5 (a) and (b) (comprise leakage current I for the drain terminal electric current of the double silicon nanowire wrap gate device of BOI structure provided by the invention
Off, ON state drive current I
On), gate capacitance (C
G) with the comparison chart of document 2.
Fig. 6 (a)-(n) be one embodiment of the invention based on the technological process of body double silicon nanowire wrap gate preparation of devices method of (BOI structure) on insulating barrier of body silicon substrate and the schematic diagram of each step institute corresponding product structure thereof.
Among Fig. 6 (a)-(n), identical label is represented identical parts:
601-body silicon substrate (p-doping) 602-makes the SiO of hard mask
2Layer
603-makes the Si of hard mask
3N
4The SiO of layer 604-protection silicon raceway groove
2Side wall
The silicon raceway groove (its thickness can define the height H of the cross-section structure of double silicon nanowire) that 605-is unsettled
Overhead positions under the 606-silicon raceway groove (is used for filling SiO
2Make insulating barrier)
607-Si
3N
4Layer by the position of lateral encroaching (position of definition double silicon nanowire, the dimension definitions of lateral encroaching the width W of cross-section structure of double silicon nanowire, for the silicon nanowires of circle, height H and width W equate)
The silicon dioxide of the place that 608-STI isolates
Under the 609-raceway groove and the silicon dioxide insulating layer between the body silicon substrate
610-stops the Si of layer as planarization
3N
4Layer
611-double silicon nanowire (raceway groove) 612-grid oxygen 613-polysilicon gates (Poly-Si Gate)
614-source 615-leaks
Embodiment
Describe double silicon nanowire wrap gate field-effect transistor provided by the present invention and preparation method thereof in detail below in conjunction with accompanying drawing, but be not construed as limiting the invention.
As shown in Figure 4, be the double silicon nanowire wrap gate device of present embodiment.Be depicted as the domain of this device as Fig. 4 (a), M1 active area version by the part that M2 grid version covers be channel region, the part that is not capped is source region and drain region, the width of channel region (A1A2 direction) is 50nm, the length of channel region (B1B2 direction) is the long 30nm of grid.As Fig. 4 (b) with (c) be respectively the vertical direction along raceway groove (A1A2 direction) of this device and along the cross-section structure of channel direction (B1B2 direction).In Fig. 4 (b): the section as the double silicon nanowire 405 of raceway groove is 10nm for circular, diameter, by thickness is that the grid oxygen 404 of 1.2nm centers on, centered on by the polysilicon gate 403 of thick 150nm again, have above thick 100nm polysilicon, below the polysilicon of thick 40nm is arranged; The silicon dioxide insulating layer 406 that one bed thickness 250nm is arranged under the double silicon nanowire 405, the organizator BOI structure on insulating barrier.In Fig. 4 (c): the silicon dioxide 002 thick 400nm of the place that STI isolates; Because adopt the BOI structure, double silicon nanowire 405 and polysilicon gate 403 all are formed on the insulating barrier; Source 407, leakage 408 still link to each other with body silicon substrate 401, can adopt bigger junction depth 30nm, to reduce the parasitic series resistance of source and leakage, increase the ON state drive current.Thick silicon dioxide insulating layer 406 can have been eliminated the phost line that may exist on body silicon substrate 401 surfaces under the raceway groove, reduces leakage current, improves on-off ratio, reduces gate capacitance, optimizes AC characteristic, improves devices switch speed.
Double silicon nanowire wrap gate device of the present invention is based on body silicon substrate (Bulk Si Wafer).From the cross-section structure along the vertical direction of raceway groove, shown in Fig. 4 (b), raceway groove is the silicon nanowires (Twin Si Nanowire) of two identical circles, i.e. double silicon nanowire, its diameter≤10nm; Double silicon nanowire is centered on by grid oxygen (Gate Oxide) and then is centered on by grid (Gate), forms and encloses gate device; Raceway groove be double silicon nanowire under and between the substrate, the silicon dioxide insulating layer of a bed thickness 200～300nm is arranged, form the structure (Body-on-Insulator, BOI structure) of raceway groove (abbreviating body as) on insulating barrier of double silicon nanowire; From the cross-section structure along channel direction, shown in Fig. 4 (c), body is on insulating barrier, and the source all links to each other with substrate with leakage, and the junction depth of source and leakage can reach 30～50nm greater than the diameter of double silicon nanowire, to reduce the parasitic series resistance of source and leakage.
The DC characteristic and the AC characteristic of the double silicon nanowire wrap gate device of the BOI structure in the present embodiment are with the comparison of document 2, respectively as Fig. 5 (a) with (b).Parameters such as the grid length of two kinds of devices, gate oxide thickness, threshold voltage, junction depth, silicon nanowires diameter are identical.Fig. 5 (a) (comprises leakage current I for the drain terminal electric current of DC characteristic
Off, ON state drive current I
On) comparison: abscissa is gate voltage (V among the figure
G), ordinate is drain terminal electric current (I
D), leak when pressing 1.1V (volt) I during grid voltage 0V
DBe defined as leakage current I
Off, device of the present invention is compared the device of document 2, can be so that I
OffReduce 25 times; I during grid voltage 1.1V
DBe defined as ON state drive current I
On, two kinds of device approximately equals; Therefore, device provided by the present invention also can be so that on-off ratio I
On/ I
OffImprove a multiple order of magnitude.Fig. 5 (b) is the gate capacitance (C of AC characteristic
G) comparison: abscissa is gate voltage (V among the figure
G), ordinate is gate capacitance (C
G), device of the present invention as can be seen since eliminated substrate phost line, reduced parasitic gate capacitance, can significantly reduce total gate capacitance, at grid voltage 1.1V, can be so that gate capacitance reduces 36%.Because devices switch speed is with I
On/
CGV
DdWeigh V
DdFor operating voltage, get 1.1V, device of the present invention is compared the device of document 2, devices switch speed can improve 38%.
The present invention prepares the method for double silicon nanowire wrap gate field-effect transistor, and this preparation method comprises the steps:
Step 1: on the body silicon substrate, deposit silicon dioxide (SiO
2) and silicon nitride (Si
3N
4); Raceway groove injects boron; The photoetching of active area version, the width of the channel region of active area version are 50～80nm, and etch silicon nitride and oxide layer form double-deck hard mask.
Step 2: the silicon 15～20nm of etching place, the height H of the cross-section structure of this size autoregistration ground definition silicon nanowires; Deposit SiO
2, etching SiO
2Form side wall, with the protection raceway groove.
Step 3: the silicon 250～350nm of etching place once more forms shallow slot; Isotropic etching silicon 30～50nm greater than a half width of the channel region of active area version, makes that the silicon below the channel region position is all carved empty.
Step 4: remove SiO
2Side wall, wet etching Si
3N
415～20nm (wet etching is isotropic).The width W of the cross-section structure of the size autoregistration definition silicon nanowires of lateral encroaching; For the silicon nanowires of circle, height H and width W equate.
Step 5: deposit SiO
2Thickness 350～500nm is greater than the degree of depth of shallow slot; With Si
3N
4For stopping layer, chemico-mechanical polishing (CMP) planarization forms shallow-trench isolation (STI); Form the BOI structure simultaneously, raceway groove is on silicon dioxide insulating layer, and the source still links to each other with the body silicon substrate with leakage.
Step 6: the Si of deposit for the second time
3N
4Layer; The photoetching of grid version; The covering of the position of silicon nitride lateral encroaching in grid version and the above-mentioned steps 4, the position of autoregistration definition double silicon nanowire; The two-layer Si of etching
3N
4
Step 7: etching SiO
2, etch silicon again is with SiO
2For the mask autoregistration is formed on double silicon nanowire on the insulating barrier.
Step 8: corrode silicon dioxide 50～80nm makes double silicon nanowire unsettled; Adopt and optimize technology, make silicon nanowires become circle, attenuate, form double silicon nanowire circular, diameter D≤10nm.Dry-oxygen oxidation forms grid oxygen.
Step 9: the deposit polysilicon is as grid material, and phosphorus doping and RTP (rapid thermal annealing) activate, cmp planarizationization.Form the raceway groove that grid oxygen and polysilicon gate all center on double silicon nanowire, promptly enclose the grid structure.
Step 10: remove Si
3N
4, the source is leaked to mix and is injected As (arsenic), forms n+ source and the leakage of junction depth 30～50nm.
As shown in Figure 6.Each structure shown in Fig. 6 (a)-(n) is corresponding with each step among the preparation method.
Below in conjunction with accompanying drawing this preparation method is elaborated:
Step 1: at p (100) body silicon substrate, deposit SiO
2Layer 30nm and Si
3N
4Layer 100nm; Raceway groove injects boron; The photoetching of M1 active area version, the width of the channel region of active area version is 60nm; Etching Si
3N
4And SiO
2, form double-deck hard mask.Form the cross-section structure (along the vertical direction of raceway groove, the A1A2 direction shown in 4 (a)) shown in Fig. 6 (a).
Step 2: the silicon 15nm of etching place, the height H of the cross-section structure of this height autoregistration ground definition silicon nanowires; Deposit SiO again
2, etching forms side wall, protection silicon raceway groove.Form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (b).
Step 3: the silicon 300nm of etching place once more; Isotropic etching silicon 40nm makes that the silicon below the channel region position is all carved empty.Form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (c).
Step 4: remove SiO
2Side wall, wet etching Si
3N
4About 15nm.Corrosion Si
3N
4The position and the position that covers of M2 grid version can autoregistration definition double silicon nanowire the position; The size of lateral encroaching can autoregistration have defined the width W of the cross-section structure of silicon nanowires; For the silicon nanowires of circle, height H and width W equate.Form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (d).
Step 5: deposit SiO
2About 500nm is with the Si of hard mask
3N
4For stopping layer, chemico-mechanical polishing (CMP) planarization, form shallow-trench isolation; Form the BOI structure simultaneously, raceway groove is on insulating barrier, and the source still links to each other with the body silicon substrate with leakage.Form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (e), the cross-section structure of corresponding B1B2 direction is shown in Fig. 6 (f).
Step 6: the Si of deposit for the second time
3N
4Layer is shown in Fig. 6 (g) (along the A1A2 direction).The photoetching of M2 grid version, the two-layer Si of etching
3N
4, form the grid groove.
Step 7: etching SiO
2About 30nm, etch silicon again is with SiO
2For the mask autoregistration is formed on double silicon nanowire on the insulating barrier.Form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (h).
Step 8: the SiO of corrosion 60nm
2, make double silicon nanowire unsettled (but under the double silicon nanowire also have thicker silicon dioxide insulating layer); Form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (i), the cross-section structure of corresponding B1B2 direction is shown in Fig. 6 (j).The structure of process optimization double silicon nanowire is at H
2950 ℃ of high temperature furnaces of environment were annealed about 2 hours, and sacrificial oxidation repeatedly, made double silicon nanowire become circle, attenuate, and diameter is reduced to 10nm.Again 850 ℃ of dry-oxygen oxidations, generate grid oxygen 1.2nm, form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (k).
Step 9: the about 250nm of deposit polysilicon, Doping Phosphorus (P) about 1 * 10
16Cm
-2/ 40KeV, 950 ℃ of RTP (rapid thermal annealing), 10s activate, cmp planarizationization.Grid oxygen and polysilicon gate all center on the raceway groove of double silicon nanowire, form to enclose gate device.Form the cross-section structure (along the B1B2 direction) shown in Fig. 6 (1).
Step 10: remove Si
3N
4, doping As (arsenic) about 5 * 10 is leaked in the source
15Cm
-2/ 40KeV.Form the cross-section structure (along the A1A2 direction) shown in Fig. 6 (m), the cross-section structure of corresponding B1B2 direction is shown in Fig. 6 (n).
Step 11: further carry out conventional subsequent technique, deposit hypoxemia layer, the RTP activator impurity of anneal, photoetching, etching fairlead, splash-proofing sputtering metal, photoetching, etching formation metal wire, alloy, passivation.
Obtain the body that can be used to test double silicon nanowire wrap gate device at last in insulating barrier (BOI structure), under the long 30nm of grid, double silicon nanowire diameter 10nm, the double silicon nanowire and body silicon claim that the silicon dioxide insulating layer thickness at the end is 250nm.
More than by specific embodiment double silicon nanowire wrap gate device provided by the present invention and preparation method thereof has been described, those skilled in the art is to be understood that, in the scope that does not break away from essence of the present invention, can make certain deformation or modification to device architecture of the present invention; Its preparation method also is not limited to disclosed content among the embodiment.
Claims (9)
1, a kind of double silicon nanowire wrap gate field-effect transistor, based on the body silicon substrate, raceway groove is that identical cross-section structure is circular double silicon nanowire, double silicon nanowire is centered on by grid oxygen and polysilicon gate, the grid structure is enclosed in formation, the source all links to each other with the body silicon substrate with leaking, and it is characterized in that: under the raceway groove and the silicon dioxide insulating layer of a bed thickness, the structure of formation raceway groove on insulating barrier arranged between the body silicon substrate.
2, double silicon nanowire wrap gate field-effect transistor as claimed in claim 1 is characterized in that, the diameter≤10nm of described double silicon nanowire.
3, double silicon nanowire wrap gate field-effect transistor as claimed in claim 1 is characterized in that, the junction depth of described source and leakage is 30～50nm greater than the diameter of double silicon nanowire.
4, double silicon nanowire wrap gate field-effect transistor as claimed in claim 1 is characterized in that, under the described raceway groove and the silicon dioxide insulating layer between the body silicon substrate, its thickness is 200～300nm.
5, a kind of method for preparing double silicon nanowire wrap gate field-effect transistor as claimed in claim 1 is characterized in that, may further comprise the steps:
1) on the body silicon substrate, deposit silicon dioxide and silicon nitride, the photoetching of active area version, etch silicon nitride and silicon dioxide form double-deck hard mask;
2) silicon of etching place, the size autoregistration of etching has defined the height H of the cross-section structure of double silicon nanowire; Deposit silicon dioxide, etching silicon dioxide forms side wall, with the protection raceway groove;
3) silicon of etching place once more forms shallow slot; Isotropic etching silicon makes that the silicon under the raceway groove is carved sky;
4) remove the silicon dioxide side wall, the wet etching silicon nitride; The lateral encroaching size autoregistration of silicon nitride has defined the width W of the cross-section structure of double silicon nanowire; For the double silicon nanowire of circle, height H and width W equate;
5) deposit silicon dioxide, planarization forms shallow-trench isolation; Form the structure of raceway groove on insulating barrier simultaneously, and the source links to each other with the body silicon substrate still with leakage;
6) deposit silicon nitride layer, the photoetching of grid version; Grid version and above-mentioned steps 4) in the covering of position of silicon nitride lateral encroaching, the position of autoregistration definition double silicon nanowire; The two-layer silicon nitride of etching;
7) etching silicon dioxide, etch silicon again, autoregistration is formed on the double silicon nanowire on the insulating barrier;
8) wet etching silicon dioxide makes double silicon nanowire unsettled; Adopt and optimize technology, make double silicon nanowire become circle, attenuate, dry-oxygen oxidation forms grid oxygen;
9) the deposit polysilicon mixes and activation as grid material, and planarization forms polysilicon gate, and grid oxygen and polysilicon gate all center on double silicon nanowire, form to enclose the grid structure;
10) remove silicon nitride, mixing forms n+ source and leakage.
6, preparation method as claimed in claim 5 is characterized in that, in the described step 1), the width of the channel region of active area version is 50～80nm.
As claim 5 or 6 described preparation methods, it is characterized in that 7, described height H and width W all are 15～20nm.
As claim 5 or 6 described preparation methods, it is characterized in that 8, in the described step 3), the etching size of the silicon of place is 250～350nm, is the degree of depth of shallow slot; Isotropic etching silicon is 30～50nm.
As claim 5 or 8 described preparation methods, it is characterized in that 9, in the described step 5), the thickness of deposit silicon dioxide is 350～500nm.
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