CN103872140B - A kind of planar rings gate transistor based on nano wire and preparation method thereof - Google Patents
A kind of planar rings gate transistor based on nano wire and preparation method thereof Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention discloses a kind of planar rings gate transistor based on nano wire and preparation method thereof, its structure is：Conducting channel material is parallel to the low-resistance nano wire of substrate；Gate medium and gate electrode radially surround low-resistance nano wire along nano wire successively；Source-drain electrode and gate medium, gate electrode have certain interval at nanowire sidewalls；Source-drain electrode surrounds low-resistance nano wire.The invention also discloses above-mentioned planar rings gate transistor preparation method, gate electrode is first prepared, source-drain electrode is then prepared again；Gate electrode window is initially formed, gate dielectric layer and evaporation gate electrode is grown with atomic layer deposition method, then metal-coated membrane formation source-drain electrode；Low resistance contacts resistance is the method acquisition to intrinsic or low-doped nano wire heavy doping or with metal alloy.The transistor arrangement and preparation method can prepare the shorter device of raceway groove, and effectively reduce parasitic capacitance, strengthen ability of regulation and control of the grid level to raceway groove, so as to improve the performance of device.
Description
Technical field
The invention belongs to nanoelectronics technical field, and in particular to a kind of planar rings gate transistor based on nano wire and
Its preparation method.
Background technology
With the development of semi-conductor industry, the size of single metal-oxide-semiconductor is less and less, and size reduction can bring asking for some
Topic, wherein relatively more significant is exactly short-channel effect.For the ability of regulation and control of reinforcing grid to suppress short-channel effect, Ren Menti
Go out a variety of gate design schemes, from double grid to Fin grid.In all grid structures, gate-all-around structure most effective can be carried in theory
The ability of high grid regulation and control, suppresses short-channel effect.Compared to conventional blocks material, the one-dimensional material such as nano wire has easily prepared
The inherent advantage of gate-all-around structure.
A critically important index for characterizing semi-conducting material electric property is carrier mobility, and for current main-stream
For silicon technology, the electric property of the silicon used is simultaneously non-optimal, and its mobility is relatively low, and the carrier of III-V material is moved
Shifting rate, especially electron mobility are far above silicon, in the development of following semi-conductor industry, particularly in radio frequency electronics
Field, III-V material probably substitutes silicon materials.
There are many seminar to possess the ability for growing iii-v nano wire on a silicon substrate both at home and abroad at present：It is auspicious
Lars Samuelson of allusion quotation Lund universities et al. are delivered in Journal of Crystal Growth334 (2011) 51-56
Entitled " Self-seeded, position-controlled InAs nanowire growth on Si:A growth
In parameter study " article, the method growth nano thread ordered battle arrays of InAs on a silicon substrate using self-catalysis are disclosed
The achievement of row；Takashi Fukui of Hokkaido, Japan university et al. deliver entitled " A in Nature488 (2012) 189
III–V nanowire channel on silicon for high-performance vertical transistors”
Article, also possess on a silicon substrate grow iii-v nano wire cyclic array ability.
From the point of view of the electric property of material and current progress, iii-v nano wire is very possible in radio frequency electric
Devices field is further applied.The work for being currently based on the planar rings grid radio-frequency devices of iii-v nano wire comes from
(its work is published in Nano Lett., entitled " Realizing Lateral Wrap-Gated to Lund universities of Sweden
Nanowire FETs:Controlling Gate Length with Chemistry Rather than
Lithography”.) and NTT companies of Japan (its work is published in the entitled Encapsulated gate-all-around of APL
InAs nanowire field-effect transistors), but the former technique is complex, it is larger to sample damage, and
Then the latter shifts nano wire using bottom gate thin film is first carried out, and layer of metal is finally wrapped again, forms ring grid, that is, wraps up nanometer
The metal of line is plated in two times, so middle to form a fixed gap, so that nano wire can not be wrapped up very well.
The content of the invention
The purpose of the present invention is to prepare more rapidly, preferably suppress short-channel effect, improve grid-control ability
Planar rings gate transistor based on nano wire.
To achieve these goals, the present invention uses following technical scheme：
A kind of planar rings gate transistor based on nano wire includes：Substrate, suspension and nano wire parallel to substrate and
Positioned at substrate and radially surround the source electrode being arranged in order, gate electrode and the drain electrode of the nano wire；
The conducting channel of the transistor is the nano wire radially surrounded by gate electrode, the gate electrode and the nano wire
Between have gate medium；
The source electrode and drain electrode have spacing with gate electrode respectively, between the source electrode and gate medium, gate electrode
And between drain electrode and gate medium, gate electrode in nanowire sidewalls without being electrically connected.
Preferably, the above-mentioned planar rings gate transistor based on nano wire, its substrate is monocrystalline silicon or covering silica
Monocrystalline silicon.
Preferably, the nano wire is auto-dope low-resistance nano wire, and its material is III-V material.
Preferably, the gate medium is high dielectric constant material.
Preferably, source electrode, gate electrode and the extremely metal electrode that leaks electricity.Wherein, the source electrode and drain metal will
The metal of Ohmic contact can be formed with nano wire by asking, including gold, aluminium, nickel etc..
The above-mentioned planar rings gate transistor preparation method based on nano wire, comprises the following steps：
1) one layer of glue is got rid of first in substrate, nano wire, and positioning nanowires are then shifted on the even substrate for crossing glue；Again
One layer of glue is got rid of, nano wire is mingled with the middle of two layers of glue；
2) output gate electrode window and gate electrode window is carried out to go cull to handle, then erode under gate electrode window
Native oxide layer on nano wire；
3) gate medium is grown on the nano wire under gate electrode window；Gate electrode is prepared, is then peeled off；
4) source electrode window and drain electrode window are outputed, and source electrode window and drain electrode window go at cull
Reason, then erodes the native oxide layer on the nano wire under source electrode window and drain electrode window；
5) source electrode and drain electrode are prepared, is then peeled off.
Preferably, step 1）Described in glue be PMMA（Polymethyl methacrylate）, the nano wire is to be given birth to
The auto-dope introduced during long nano wire.
Preferably, step 1）In, the substrate is markd substrate, and localization method is existing using ESEM
Positioned on the substrate of mark.
Preferably, step 2）In, by positioning, exposed and developed, fixing, define gate electrode area, exposure method
For electron beam exposure, the method for cull is gone to remove cull for oxygen plasma, it is acid using thiamines solution or HCL and IPA mixing
Solution is corroded.
Preferably, step 3）In, the method for growth gate medium is ald；The preparation method of gate electrode is splashed for magnetic control
Plated film is penetrated, is peeled off using acetone.
Preferably, the method peeled off using acetone is：Steep 1 hour of acetone heated in 60 C water baths, Ran Houzai
Dropper suction acetone blows several times.
Preferably, step 4）In, by spin coating, exposed and developed, fixing, define source electrode area and drain electrode
Area, exposure method is electron beam exposure, goes the method for cull to remove cull for oxygen plasma, uses thiamines solution or HCL and IPA
Mixed acid solution corroded.
Preferably, step 5）In, the preparation method of source electrode and drain electrode is thermal evaporation plated film, electron beam plated film or splashed
Penetrate.
Beneficial effect：
The planar rings gate transistor based on nano wire of the present invention, nano wire is low-resistance nano wire, can be largely
Reduce the dead resistance between gate electrode and source electrode and drain electrode；The width of gate electrode determines by there is exposure to define window, because
This can realize short gate device, so that the mutual conductance of device is improved, the operating rate of boost device；Gate electrode and gate medium are to open
Go out what is and then completed after gate electrode window, therefore gate electrode is self aligned；And gate electrode is radially wrapped up along nano wire, phase
There is stronger grid ability of regulation and control than existing other grid structures, so as to effectively suppress short-channel effect.
Brief description of the drawings
Fig. 1 is the domain of the planar rings gate transistor based on nano wire in the embodiment of the present invention（Overlook）Schematic diagram.In figure,
101- low-resistance nano wires；102- nano wire native oxide layers；The oxide layer of 103- growths；104- gate electrodes；105- drain electrodes；
106- sources electricity level.
Fig. 2 is the section knot in the A-A ' directions along along Fig. 1 of the planar rings gate transistor based on nano wire in the embodiment of the present invention
Structure schematic diagram.In figure, 201- substrates；202- nano wires；203- native oxide layers；204- drain electrodes；205- source electrodes；206- grid
Medium；207- gate electrodes.
The cross-sectional view that Fig. 3 (a) to Fig. 3 (l) is formed for device in the embodiment of the present invention in each step.In figure
301- substrates；302- nano wires；303- native oxide layers；304- drain electrodes；305- source electrodes；306- gate mediums；307- grid electricity
Pole；308- electron beam resists.
Fig. 4（a）Transfer characteristic curve is measured for the probe station of a device in the embodiment of the present invention.
Fig. 4（b）To change into the situation measurement result under semilog coordinate.
Embodiment
Below in conjunction with the accompanying drawings, further is made to the present invention by embodiment of the planar rings gate transistor based on InAs nano wires
It is described in detail.
Fig. 1 is the domain of the planar rings gate transistor based on nano wire in the embodiment of the present invention（Overlook）Schematic diagram, wherein
101 be low-resistance nano wire, and 102 be the native oxide layer surrounded outside nano wire, and 103 be the HfO grown with ALD methods2, 104 are
Gate electrode, 105 be drain electrode, and 106 be source electrode.
Fig. 2 is the diagrammatic cross-section in the A-A ' directions along along Fig. 1.Substrate 201 is monocrystalline of the surface covered with one layer of silica
Silicon；The above section of substrate 201 from left to right includes source electrode 205, gate electrode 207 and drain electrode 204 respectively；Transistor is led
Electric raceway groove is that the nano wire 202 suspended parallel to substrate 201 is surrounded by gate electrode 207, and the not besieged outer layer of nano wire 202 is
Native oxide layer 203；There is gate medium 206, gate electrode 207 and gate medium 206 are wrapped between gate electrode 207 and nano wire 202
Nano wire 202 is enclosed so that nano wire 202 is separated and suspended with substrate 201；Source electrode 205 and the parcel nano wire 202 of drain electrode 204
And it is at regular intervals with gate electrode 207 and gate medium 206.
The above-mentioned planar rings gate transistor preparation method based on nano wire is as follows：
1）200nm thickness SiO is being covered with using sol evenning machine2Monocrystalline silicon on get rid of one layer of PMMA A2（Whirl coating speed is 1500
Rev/min, 60 seconds time）, about 100 nanometers of thickness, shown in such as Fig. 3 (a), 301 be substrate in figure, and 308 be beamwriter lithography
Glue.
2）By nano wire（By the Chinese Academy of Sciences, semiconductor is provided）On the substrate for being transferred to even one layer of PMMA of mistake, such as Fig. 3
(b) shown in, 302 be the InAs nano wires for being naturally introduced by doping in figure, and 303 be the native oxide layer of nano wire outer layer.Wherein serve as a contrast
Bottom is markd substrate, and its preparation process is completed using a series of micro-nano electronic technology, exposes institute using photoetching technique first
The marker graphic needed, then developing fixing, then carry out plated film with electron beam plated film instrument is peeled off etc. and to prepare mark.
3）One layer of PMMA A4 is got rid of again（Whirl coating speed is 4000 revs/min, 60 seconds time）, about 200 nanometers of thickness, such as
Fig. 3（c）It is shown.
4）Output gate window, such as Fig. 3（d）Shown, specific technical process is：Draw domain and define gate electrode region
（About 1 micron of gate electrode width）；Electron beam exposure；Develop and fixing；
5）Remove the oxide of intrinsic or low-doped nanowire surface, optional minimizing technology have ammonium sulfate solution or other
Acid solution corrodes.
6）Gate medium 306 is grown, gate medium is grown using ald (ALD) method, thickness is 12 nanometers, optionally
Gate medium has hafnium oxide, zirconium oxide, aluminum oxide and other medium materials that there is the permittivity magnitude relative to vacuum to be more than 6
Material.As shown in Fig. 3 (e), 306 be gate medium in figure.
7）Prepare gate electrode 307：After growth gate dielectric layer, plated film directly is carried out with magnetron sputtering plating instrument, thickness is big
About 10nm/200nm, membrane material is metal Ti/Au, such as Fig. 3（f）It is shown.
8）Form gate electrode 307：After plated film, peeled off with acetone, such as Fig. 3（g）It is shown.
9）Source and drain window is outputed, detailed process is to pass through picture domain, spin coating electron beam resist PMMA A4（Whirl coating speed
For 4000 revs/min, 60 seconds time）, about 200 nanometers of thickness, electron beam exposure, development and fixing expose source electricity
Pole and the region of drain electrode（Source electrode and drain electrode width are about
500nm）, such as Fig. 3（h）And Fig. 3（i）It is shown.
10）Remove removing oxide layer：Optional minimizing technology has ammonium sulfate solution or the corrosion of other acid solutions, such as Fig. 3（j）Institute
Show.
11）Source electrode 305 and drain electrode 304 are prepared to form Ohmic contact, specific technical process is：
Electron beam plated film or sputtering plating metal（5nm/90nm Ti/Au）；Peel off.Such as Fig. 3（k）And Fig. 3（l）It is shown.
Fig. 4（a）Transfer characteristic curve result is measured for the probe station of a device in the embodiment of the present invention, wherein, VgTable
Show gate voltage, IdsRepresent source-drain current.Fixed source-drain voltage Vds=10mV, with 10mV step-lengths go scan grid, Vg from -3V to
3V.Fig. 4（b）To change into the situation measurement result under semilog coordinate, wherein, VgRepresent gate voltage, IdsRepresent source-drain current.
Its performance indications extracted from the graph are about as follows, on-off ratio about 104To 105；Carrier mobility is 629.3cm2/ Vs,
The sub-threshold slope amplitude of oscillation is 450mV/dec.
Claims (4)
1. a kind of preparation method of the planar rings gate transistor based on InAs nano wires, comprises the following steps：
1) one layer of PMMA A2 glue is got rid of first in substrate, the then InAs nano wires in transfer on the even substrate for crossing glue, and using sweeping
Retouch Electronic Speculum positioning InAs nano wires；One layer of PMMA A4 glue is got rid of again, InAs nano wires is mingled with the middle of two layers of glue, the InAs receives
Rice noodles are the auto-dope low-resistance nano wires that doping is naturally introduced by during growth InAs nano wires are carried out, and the substrate is
Markd substrate；
2) by positioning, exposed and developed, fixing, gate electrode area is defined, electron beam exposure outputs gate electrode window simultaneously
Gate electrode window is carried out to go cull to handle, the native oxide layer of the InAs nano wires under gate electrode window is then eroded；
3) gate medium of high-k is grown on the InAs nano wires under gate electrode window using Atomic layer deposition method；
Grow after gate dielectric layer, directly carry out plated film with magnetron sputtering plating instrument, prepare gate electrode, then peeled off using acetone；
4) by drawing domain, spin coating electron beam resist PMMA A4, electron beam exposure, development and fixing, expose source electricity
Pole and the region of drain electrode, output source electrode window and drain electrode window, and source electrode window and drain electrode window are gone
Cull processing, then erodes the native oxide layer of the InAs nano wires under source electrode window and drain electrode window；
5) source electrode and drain electrode are prepared to form Ohmic contact, is then peeled off.
2. the preparation method of the planar rings gate transistor as claimed in claim 1 based on InAs nano wires, it is characterised in that step
It is rapid 2) and 4) in, go the method for cull to remove cull for oxygen plasma, the mixing acidity using thiamines solution or HCL and IPA is molten
Liquid is corroded.
3. the preparation method of the planar rings gate transistor as claimed in claim 1 based on InAs nano wires, it is characterised in that step
It is rapid 5) in, the preparation method of the source electrode and drain electrode is thermal evaporation plated film, electron beam plated film or sputtering.
4. the planar rings grid crystal based on InAs nano wires prepared using the preparation method described in claim 1-3 any one
Pipe, the conducting channel of the planar rings gate transistor based on InAs nano wires is to be surrounded to suspend parallel to substrate by gate electrode
InAs nano wires, gate electrode and gate medium surround InAs nano wires and cause InAs nano wires to separate and suspend with substrate；Source electricity
Pole and drain electrode wrap up InAs nano wires and have spacing between gate electrode and gate medium.
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|---|---|---|---|---|
| CN102157556A (en) * | 2011-01-27 | 2011-08-17 | 北京大学 | Oxidizing-dephlegmation-based silicon-based wrap gate transistor with buried-channel structure and preparation method thereof |
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| CN102157556A (en) * | 2011-01-27 | 2011-08-17 | 北京大学 | Oxidizing-dephlegmation-based silicon-based wrap gate transistor with buried-channel structure and preparation method thereof |
Non-Patent Citations (2)
| Title |
|---|
| Facile fabrication of lateral nanowire wrap-gate devices with improved performance;Sajal Dhara et al;《Applied Physics Letters》;20111024;第1页第1段-第3页最后1段，图1 * |
| Realizing Lateral Wrap-Gated Nanowire FETs: Contr olling Gate Length with Chemistry Rather than Lithography;Kristian Storm et al;《Nano Letters》;20110215;全文 * |
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| CN103872140A (en) | 2014-06-18 |
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