CN102130055A - Method for improving breakdown voltage of trench double gate MOS (Metal Oxide Semiconductor) device - Google Patents
Method for improving breakdown voltage of trench double gate MOS (Metal Oxide Semiconductor) device Download PDFInfo
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- CN102130055A CN102130055A CN2010100273299A CN201010027329A CN102130055A CN 102130055 A CN102130055 A CN 102130055A CN 2010100273299 A CN2010100273299 A CN 2010100273299A CN 201010027329 A CN201010027329 A CN 201010027329A CN 102130055 A CN102130055 A CN 102130055A
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Abstract
The invention discloses a method for improving a breakdown voltage of a trench double gate MOS (Metal Oxide Semiconductor) device, comprising the following steps of: preparing an oxide layer between double gates in the MOS device by adopting a thermal oxidization process; and etching an interlayer film to form a contact hole, then carrying out ion implantation at the bottom of the contact hole, and forming a second well region at the bottom of the contact hole, wherein the conduction type of the implanted ions is same as the conduction type of a body region. The method disclosed by the invention ensures that the breakdown voltage of a drain source is further improved at the same time of shortening the switching time and reducing the switching loss of the MOS device.
Description
Technical field
The present invention relates to a kind of preparation method of puncture voltage of groove type double-layer grid MOS device.
Background technology
In semiconductor integrated circuit, existing more advanced slot type dual layer grid power MOS device construction as shown in Figure 1.The transistor bucking electrode of this structure separates switch electrode (being grid) and drain region (i.e. shielding), effectively reduces gate leakage capacitance (that is the miller capacitance in the circuit), thereby reduces the switching time and the switching loss of device.This structure can make miller capacitance further reduce by improvement, the breakdown voltage resistant further raising of drain-source.
Summary of the invention
Technical problem to be solved by this invention is further to reduce the miller capacitance of groove type double-layer grid MOS device and further improve puncture voltage.
For solving the problems of the technologies described above, the method for improving the puncture voltage of groove type double-layer grid MOS device of the present invention, the oxide layer between the wherein double-deck grid adopt hot oxygen prepared to form; And film forms after the contact hole between etch layer, and contact hole bottom ion is injected, and forms second well region in described contact hole bottom, and the ionic conduction type of being injected is identical with the tagma, and second well region extends to epitaxial loayer.
Method of the present invention, make the epitaxial loayer between adjacent trenches and second well region charge carrier device by the time exhaust mutually, therefore the grid leak miller capacitance further reduces, thereby the switching time and the switching loss while drain-source breakdown voltage that reduce device further improve.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of existing groove type double-layer grid MOS device;
Fig. 2 is the structural representation of the groove type double-layer grid MOS device implementing to form after the method for the present invention;
Fig. 3 is for implementing the structural representation behind the etching groove in the method for the present invention;
Fig. 4 is the structural representation after lower-layer gate forms in the enforcement method of the present invention;
Fig. 5 is the structural representation after implementing method of the present invention grid forming at the middle and upper levels;
Fig. 6 is the structural representation after the source region forms in the enforcement method of the present invention;
Fig. 7 is the structural representation after contact hole etching forms in the enforcement method of the present invention;
Fig. 8 is for implementing the structural representation after contact hole twice injection in bottom in the method for the present invention.
Embodiment
The method of improving the puncture voltage of groove type double-layer grid MOS device of the present invention on the basis of original structure, has increased by second well region of contact hole below, and the conduction type of second well region is identical with the device tagma, and second well region extends to epitaxial loayer; And adopt oxide layer between the double-deck grid of hot oxygen prepared.
Concrete preparation flow is described below:
1) under the protection that hard barrier layer is arranged, the epitaxial loayer on the etched substrate forms the groove (see figure 3);
2) then being the oxide layer growth of trench wall, is the deposit and time quarter of ground floor polysilicon afterwards, forms lower-layer gate (be the bucking electrode of this device, see Fig. 4).Before the oxide layer growth of trench wall, also can carry out the growth of sacrificial oxide layer and remove technology.
3) then be the oxide layer that adopts on the hot oxygen technology growth lower-layer gate.A kind of concrete way is injected into trenched side-wall surface (being the flute surfaces that is not covered by lower-layer gate) for adopting ion implantation technology earlier with the nitrogen ion, and the lower-layer gate surface under not being injected into; Then carry out hot oxide growth, make the silicon of trenched side-wall and the polysilicon oxidation on lower-layer gate surface generate oxide layer, slower because of the oxidation rate that the trenched side-wall that the nitrogen ion exists is arranged than the oxidation rate of polysilicon, therefore can form the oxide layer of enough thick and even compact on the lower-layer gate surface.In the nitrogen ion implantation technology, the nitrogen ion dose that is injected is: 10
11～10
16Atom/cm
2, the angle of nitrogen ion beam and substrate vertical axis is: 0～89 degree, the injection energy is: 1～500KeV.And another kind of way is injected into the surface of lower-layer gate for adopting earlier ion implantation technology with fluorine ion, and trenched side-wall does not inject fluorine ion; Carry out hot oxide growth afterwards, make the silicon of trenched side-wall and the polysilicon oxidation on lower-layer gate surface generate oxide layer, also can on lower-layer gate, form the oxide layer of enough thick and even compact.In the fluorine ion injection technology, the implantation dosage of fluorine ion is: 1011～10
16Atom/cm
2, the injection energy is: 1～2000KeV.
4) then be the deposit of second layer polysilicon, form upper strata grid (see figure 6) (being also referred to as switch electrode) after the etching.
5) then be that the ion that adopts common process to carry out the tagma injects and the ion in source region injects equally, and in film, then film formation contact hole (see figure 7) between etch layer between illuvium on the substrate that has formed said structure.
6) after contact hole etching forms, two secondary ions inject, and the ionic conduction type of being injected is identical with the tagma, form second well region respectively and form the ohmic contact regions (see figure 8) in the contact hole lower surface below contact hole, second well region is deeper than ohmic contact regions, extends to epitaxial loayer.Be vertical injection for twice, the ion that forms second well region injects, and injects energy and is set to 10-2000KeV, and the ion dose that is injected is 10
12～10
14Atom/cm
2Form in the ion implantation technology of ohmic contact regions, the injection energy is 1-200KeV, and the ion dose that is injected is 10
14～10
16Atom/cm
2
The double-deck grate MOS device processing procedure of follow-up other technology and traditional groove is in full accord, the final device architecture that forms as shown in Figure 2.
Claims (4)
1. method of improving the puncture voltage of groove type double-layer grid MOS device is characterized in that:
Oxide layer in the described groove type double-layer grid MOS device between the double-deck grid adopts hot oxygen prepared to form;
And film forms after the contact hole between etch layer, ion is carried out in the contact hole bottom inject, and forms second well region in described contact hole bottom, and the ionic conduction type of being injected is identical with the tagma, and described second well region extends in the epitaxial loayer.
2. method according to claim 1 is characterized in that: described after second well region is formed on the contact hole bottom, and also carry out ion and be infused in described contact hole lower surface formation ohmic contact regions.
3. method according to claim 1 is characterized in that: the ion of described formation ohmic contact regions injects, and the ion dose that is injected is 10
14～10
16Atom/cm
2, the injection energy is 1-200KeV.
4. according to the described method of each claim in the claim 1 to 3, it is characterized in that: in the ion implantation technology of described contact hole bottom, be vertical injection twice, the ion of described formation second well region injects, inject energy and be set to 10-2000KeV, the ion dose that is injected is 10
12～10
14Atom/cm
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100273299A CN102130055A (en) | 2010-01-20 | 2010-01-20 | Method for improving breakdown voltage of trench double gate MOS (Metal Oxide Semiconductor) device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100273299A CN102130055A (en) | 2010-01-20 | 2010-01-20 | Method for improving breakdown voltage of trench double gate MOS (Metal Oxide Semiconductor) device |
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|---|---|
| CN102130055A true CN102130055A (en) | 2011-07-20 |
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| CN2010100273299A Pending CN102130055A (en) | 2010-01-20 | 2010-01-20 | Method for improving breakdown voltage of trench double gate MOS (Metal Oxide Semiconductor) device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060273386A1 (en) * | 2005-05-26 | 2006-12-07 | Hamza Yilmaz | Trench-gate field effect transistors and methods of forming the same |
| US7470953B2 (en) * | 2003-10-08 | 2008-12-30 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
-
2010
- 2010-01-20 CN CN2010100273299A patent/CN102130055A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7470953B2 (en) * | 2003-10-08 | 2008-12-30 | Toyota Jidosha Kabushiki Kaisha | Insulated gate type semiconductor device and manufacturing method thereof |
| US20060273386A1 (en) * | 2005-05-26 | 2006-12-07 | Hamza Yilmaz | Trench-gate field effect transistors and methods of forming the same |
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Application publication date: 20110720 |